target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch

   1 From a10349f1710a11239c58da3a7e5b353c6b2070c2 Mon Sep 17 00:00:00 2001
   2 From: Chaotian Jing <chaotian.jing@mediatek.com>
   3 Date: Mon, 16 Oct 2017 09:46:32 +0800
   4 Subject: [PATCH 153/224] mmc: mediatek: add pad_tune0 support
   5
   6 from mt2701, the register of PAD_TUNE has been phased out,
   7 while there is a new register of PAD_TUNE0
   8
   9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
  10 Tested-by: Sean Wang <sean.wang@mediatek.com>
  11 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  12 ---
  13  drivers/mmc/host/mtk-sd.c | 51 ++++++++++++++++++++++++++++++-----------------
  14  1 file changed, 33 insertions(+), 18 deletions(-)
  15
  16 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
  17 index ab2fbbbdfda3..bcd83d6f2b86 100644
  18 --- a/drivers/mmc/host/mtk-sd.c
  19 +++ b/drivers/mmc/host/mtk-sd.c
  20 @@ -75,6 +75,7 @@
  21  #define MSDC_PATCH_BIT   0xb0
  22  #define MSDC_PATCH_BIT1  0xb4
  23  #define MSDC_PAD_TUNE    0xec
  24 +#define MSDC_PAD_TUNE0   0xf0
  25  #define PAD_DS_TUNE      0x188
  26  #define PAD_CMD_TUNE     0x18c
  27  #define EMMC50_CFG0      0x208
  28 @@ -301,6 +302,7 @@ struct msdc_save_para {
  29  struct mtk_mmc_compatible {
  30         u8 clk_div_bits;
  31         bool hs400_tune; /* only used for MT8173 */
  32 +       u32 pad_tune_reg;
  33  };
  34
  35  struct msdc_tune_para {
  36 @@ -362,21 +364,25 @@ struct msdc_host {
  37  static const struct mtk_mmc_compatible mt8135_compat = {
  38         .clk_div_bits = 8,
  39         .hs400_tune = false,
  40 +       .pad_tune_reg = MSDC_PAD_TUNE,
  41  };
  42
  43  static const struct mtk_mmc_compatible mt8173_compat = {
  44         .clk_div_bits = 8,
  45         .hs400_tune = true,
  46 +       .pad_tune_reg = MSDC_PAD_TUNE,
  47  };
  48
  49  static const struct mtk_mmc_compatible mt2701_compat = {
  50         .clk_div_bits = 12,
  51         .hs400_tune = false,
  52 +       .pad_tune_reg = MSDC_PAD_TUNE0,
  53  };
  54
  55  static const struct mtk_mmc_compatible mt2712_compat = {
  56         .clk_div_bits = 12,
  57         .hs400_tune = false,
  58 +       .pad_tune_reg = MSDC_PAD_TUNE0,
  59  };
  60
  61  static const struct of_device_id msdc_of_ids[] = {
  62 @@ -581,6 +587,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
  63         u32 flags;
  64         u32 div;
  65         u32 sclk;
  66 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
  67
  68         if (!hz) {
  69                 dev_dbg(host->dev, "set mclk to 0\n");
  70 @@ -663,10 +670,10 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
  71          */
  72         if (host->sclk <= 52000000) {
  73                 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
  74 -               writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
  75 +               writel(host->def_tune_para.pad_tune, host->base + tune_reg);
  76         } else {
  77                 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
  78 -               writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
  79 +               writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
  80                 writel(host->saved_tune_para.pad_cmd_tune,
  81                        host->base + PAD_CMD_TUNE);
  82         }
  83 @@ -1224,6 +1231,7 @@ static irqreturn_t msdc_irq(int irq, void *dev_id)
  84  static void msdc_init_hw(struct msdc_host *host)
  85  {
  86         u32 val;
  87 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
  88
  89         /* Configure to MMC/SD mode, clock free running */
  90         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
  91 @@ -1239,7 +1247,7 @@ static void msdc_init_hw(struct msdc_host *host)
  92         val = readl(host->base + MSDC_INT);
  93         writel(val, host->base + MSDC_INT);
  94
  95 -       writel(0, host->base + MSDC_PAD_TUNE);
  96 +       writel(0, host->base + tune_reg);
  97         writel(0, host->base + MSDC_IOCON);
  98         sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
  99         writel(0x403c0046, host->base + MSDC_PATCH_BIT);
 100 @@ -1259,7 +1267,7 @@ static void msdc_init_hw(struct msdc_host *host)
 101         sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
 102
 103         host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
 104 -       host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
 105 +       host->def_tune_para.pad_tune = readl(host->base + tune_reg);
 106         dev_dbg(host->dev, "init hardware done!");
 107  }
 108
 109 @@ -1402,18 +1410,19 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
 110         struct msdc_delay_phase internal_delay_phase;
 111         u8 final_delay, final_maxlen;
 112         u32 internal_delay = 0;
 113 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
 114         int cmd_err;
 115         int i, j;
 116
 117         if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
 118             mmc->ios.timing == MMC_TIMING_UHS_SDR104)
 119 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 120 +               sdr_set_field(host->base + tune_reg,
 121                               MSDC_PAD_TUNE_CMDRRDLY,
 122                               host->hs200_cmd_int_delay);
 123
 124         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
 125         for (i = 0 ; i < PAD_DELAY_MAX; i++) {
 126 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 127 +               sdr_set_field(host->base + tune_reg,
 128                               MSDC_PAD_TUNE_CMDRDLY, i);
 129                 /*
 130                  * Using the same parameters, it may sometimes pass the test,
 131 @@ -1437,7 +1446,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
 132
 133         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
 134         for (i = 0; i < PAD_DELAY_MAX; i++) {
 135 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 136 +               sdr_set_field(host->base + tune_reg,
 137                               MSDC_PAD_TUNE_CMDRDLY, i);
 138                 /*
 139                  * Using the same parameters, it may sometimes pass the test,
 140 @@ -1462,12 +1471,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
 141                 final_maxlen = final_fall_delay.maxlen;
 142         if (final_maxlen == final_rise_delay.maxlen) {
 143                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
 144 -               sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
 145 +               sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
 146                               final_rise_delay.final_phase);
 147                 final_delay = final_rise_delay.final_phase;
 148         } else {
 149                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
 150 -               sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
 151 +               sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
 152                               final_fall_delay.final_phase);
 153                 final_delay = final_fall_delay.final_phase;
 154         }
 155 @@ -1475,7 +1484,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
 156                 goto skip_internal;
 157
 158         for (i = 0; i < PAD_DELAY_MAX; i++) {
 159 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 160 +               sdr_set_field(host->base + tune_reg,
 161                               MSDC_PAD_TUNE_CMDRRDLY, i);
 162                 mmc_send_tuning(mmc, opcode, &cmd_err);
 163                 if (!cmd_err)
 164 @@ -1483,7 +1492,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
 165         }
 166         dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
 167         internal_delay_phase = get_best_delay(host, internal_delay);
 168 -       sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
 169 +       sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
 170                       internal_delay_phase.final_phase);
 171  skip_internal:
 172         dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
 173 @@ -1545,12 +1554,13 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
 174         u32 rise_delay = 0, fall_delay = 0;
 175         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
 176         u8 final_delay, final_maxlen;
 177 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
 178         int i, ret;
 179
 180         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 181         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
 182         for (i = 0 ; i < PAD_DELAY_MAX; i++) {
 183 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 184 +               sdr_set_field(host->base + tune_reg,
 185                               MSDC_PAD_TUNE_DATRRDLY, i);
 186                 ret = mmc_send_tuning(mmc, opcode, NULL);
 187                 if (!ret)
 188 @@ -1565,7 +1575,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
 189         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 190         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
 191         for (i = 0; i < PAD_DELAY_MAX; i++) {
 192 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 193 +               sdr_set_field(host->base + tune_reg,
 194                               MSDC_PAD_TUNE_DATRRDLY, i);
 195                 ret = mmc_send_tuning(mmc, opcode, NULL);
 196                 if (!ret)
 197 @@ -1578,14 +1588,14 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
 198         if (final_maxlen == final_rise_delay.maxlen) {
 199                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 200                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
 201 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 202 +               sdr_set_field(host->base + tune_reg,
 203                               MSDC_PAD_TUNE_DATRRDLY,
 204                               final_rise_delay.final_phase);
 205                 final_delay = final_rise_delay.final_phase;
 206         } else {
 207                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 208                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
 209 -               sdr_set_field(host->base + MSDC_PAD_TUNE,
 210 +               sdr_set_field(host->base + tune_reg,
 211                               MSDC_PAD_TUNE_DATRRDLY,
 212                               final_fall_delay.final_phase);
 213                 final_delay = final_fall_delay.final_phase;
 214 @@ -1599,6 +1609,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 215  {
 216         struct msdc_host *host = mmc_priv(mmc);
 217         int ret;
 218 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
 219
 220         if (host->hs400_mode &&
 221             host->dev_comp->hs400_tune)
 222 @@ -1616,7 +1627,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 223         }
 224
 225         host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
 226 -       host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
 227 +       host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
 228         host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
 229         return ret;
 230  }
 231 @@ -1857,10 +1868,12 @@ static int msdc_drv_remove(struct platform_device *pdev)
 232  #ifdef CONFIG_PM
 233  static void msdc_save_reg(struct msdc_host *host)
 234  {
 235 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
 236 +
 237         host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
 238         host->save_para.iocon = readl(host->base + MSDC_IOCON);
 239         host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
 240 -       host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
 241 +       host->save_para.pad_tune = readl(host->base + tune_reg);
 242         host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
 243         host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
 244         host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
 245 @@ -1870,10 +1883,12 @@ static void msdc_save_reg(struct msdc_host *host)
 246
 247  static void msdc_restore_reg(struct msdc_host *host)
 248  {
 249 +       u32 tune_reg = host->dev_comp->pad_tune_reg;
 250 +
 251         writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
 252         writel(host->save_para.iocon, host->base + MSDC_IOCON);
 253         writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
 254 -       writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
 255 +       writel(host->save_para.pad_tune, host->base + tune_reg);
 256         writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
 257         writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
 258         writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
 259 --
 260 2.11.0
 261