ramips: add proper system clock and reset driver support for mt7621
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7628an_wiznet_wizfi630s.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7628an.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "wiznet,wizfi630s", "mediatek,mt7628an-soc";
10 model = "WIZnet WizFi630S";
11
12 chosen {
13 bootargs = "console=ttyS1,115200";
14 };
15
16 aliases {
17 led-boot = &led_run;
18 led-failsafe = &led_run;
19 led-running = &led_run;
20 led-upgrade = &led_run;
21 serial0 = &uart1;
22 serial1 = &uartlite;
23 };
24
25 leds {
26 compatible = "gpio-leds";
27
28 led_run: run {
29 label = "green:run";
30 gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
31 };
32
33 ledwps {
34 label = "green:wps";
35 gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
36 };
37
38 leduart1 {
39 label = "green:uart1";
40 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
41 };
42
43 leduart2 {
44 label = "green:uart2";
45 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
46 };
47 };
48
49 keys {
50 compatible = "gpio-keys";
51
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 reset {
56 label = "reset";
57 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
58 linux,code = <KEY_RESTART>;
59 };
60
61 wps {
62 label = "wps";
63 gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
64 linux,code = <KEY_WPS_BUTTON>;
65 };
66
67 scm1 {
68 label = "SCM1";
69 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
70 linux,code = <BTN_1>;
71 linux,input-type = <EV_SW>;
72 };
73
74 scm2 {
75 label = "SCM2";
76 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
77 linux,code = <BTN_2>;
78 linux,input-type = <EV_SW>;
79 };
80 };
81 };
82
83 &state_default {
84 gpio {
85 groups = "gpio", "i2s", "i2c", "wdt", "refclk", "p1led_an", "p2led_an";
86 function = "gpio";
87 };
88 };
89
90 &spi0 {
91 status = "okay";
92
93 pinctrl-names = "default";
94 pinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;
95
96 flash@0 {
97 compatible = "jedec,spi-nor";
98 reg = <0>;
99 spi-max-frequency = <40000000>;
100 broken-flash-reset;
101
102 partitions {
103 compatible = "fixed-partitions";
104 #address-cells = <1>;
105 #size-cells = <1>;
106
107 partition@0 {
108 label = "u-boot";
109 reg = <0x0 0x30000>;
110 read-only;
111 };
112
113 partition@30000 {
114 label = "u-boot-env";
115 reg = <0x30000 0x10000>;
116 read-only;
117 };
118
119 factory: partition@40000 {
120 label = "factory";
121 reg = <0x40000 0x10000>;
122 read-only;
123 };
124
125 partition@50000 {
126 compatible = "denx,uimage";
127 label = "firmware";
128 reg = <0x50000 0x1fb0000>;
129 };
130 };
131 };
132 };
133
134 &uart1 {
135 status = "okay";
136 };
137
138 &uart2 {
139 status = "okay";
140 };
141
142 &pwm {
143 status = "okay";
144 };
145
146 &ethernet {
147 nvmem-cells = <&macaddr_factory_2e>;
148 nvmem-cell-names = "mac-address";
149 };
150
151 &esw {
152 mediatek,portmap = <0x3e>;
153 mediatek,portdisable = <0x26>;
154 };
155
156 &sdhci {
157 status = "okay";
158 mediatek,cd-high;
159 };
160
161 &wmac {
162 status = "okay";
163
164 mediatek,mtd-eeprom = <&factory 0x0>;
165 };
166
167 &factory {
168 compatible = "nvmem-cells";
169 #address-cells = <1>;
170 #size-cells = <1>;
171
172 macaddr_factory_2e: macaddr@2e {
173 reg = <0x2e 0x6>;
174 };
175 };