/dts-v1/;
-#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/reset/mt7621-reset.h>
/ {
#address-cells = <1>;
bootargs = "console=ttyS0,57600";
};
- sysclock: sysclock {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* FIXME: there should be way to detect this */
- clock-frequency = <50000000>;
- };
-
palmbus: palmbus@1e000000 {
compatible = "palmbus";
reg = <0x1e000000 0x100000>;
sysc: syscon@0 {
compatible = "mediatek,mt7621-sysc", "syscon";
#clock-cells = <1>;
+ #reset-cells = <1>;
ralink,memctl = <&memc>;
clock-output-names = "xtal", "cpu", "bus",
"50m", "125m", "150m",
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_I2C>;
+ clock-names = "i2c";
- resets = <&rstctrl 16>;
+ resets = <&sysc MT7621_RST_I2C>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_I2S>;
- resets = <&rstctrl 17>;
+ resets = <&sysc MT7621_RST_I2S>;
reset-names = "i2s";
interrupt-parent = <&gic>;
compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
reg = <0x500 0x10>;
- resets = <&rstctrl 28>;
+ resets = <&sysc MT7621_RST_AUX_STCK>;
reset-names = "intc";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
};
- memc: syscon@5000 {
+ memc: memory-controller@5000 {
compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART1>;
+
+ resets = <&sysc MT7621_RST_UART1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ns16550a";
reg = <0xd00 0x100>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART2>;
+
+ resets = <&sysc MT7621_RST_UART2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ns16550a";
reg = <0xe00 0x100>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART3>;
+
+ resets = <&sysc MT7621_RST_UART3>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysc MT7621_CLK_BUS>;
+ clocks = <&sysc MT7621_CLK_SPI>;
+ clock-names = "spi";
- resets = <&rstctrl 18>;
+ resets = <&sysc MT7621_RST_SPI>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc MT7621_RST_GDMA>;
reset-names = "dma";
interrupt-parent = <&gic>;
compatible = "mediatek,mt7621-hsdma";
reg = <0x7000 0x1000>;
- resets = <&rstctrl 5>;
+ resets = <&sysc MT7621_RST_HSDMA>;
reset-names = "hsdma";
interrupt-parent = <&gic>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
sdhci: sdhci@1e130000 {
status = "disabled";
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
clock-names = "sys_ck";
interrupt-parent = <&gic>;
};
};
- nficlock: nficlock {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- clock-frequency = <125000000>;
- };
-
cpc: cpc@1fbf0000 {
compatible = "mti,mips-cpc";
reg = <0x1fbf0000 0x8000>;
0x1e003800 0x800>;
reg-names = "nfi", "ecc";
- clocks = <&nficlock>;
+ clocks = <&sysc MT7621_CLK_NAND>;
clock-names = "nfi_clk";
};
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
- clocks = <&sysc MT7621_CLK_FE>,
- <&sysc MT7621_CLK_ETH>;
+ clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
clock-names = "fe", "ethif";
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 6>, <&rstctrl 23>;
+ resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
reset-names = "fe", "eth";
interrupt-parent = <&gic>;
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
- resets = <&rstctrl 2>;
+ resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rstctrl 24>;
+ resets = <&sysc MT7621_RST_PCIE0>;
clocks = <&sysc MT7621_CLK_PCIE0>;
phys = <&pcie0_phy 1>;
phy-names = "pcie-phy0";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rstctrl 25>;
+ resets = <&sysc MT7621_RST_PCIE1>;
clocks = <&sysc MT7621_CLK_PCIE1>;
phys = <&pcie0_phy 1>;
phy-names = "pcie-phy1";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rstctrl 26>;
+ resets = <&sysc MT7621_RST_PCIE2>;
clocks = <&sysc MT7621_CLK_PCIE2>;
phys = <&pcie2_phy 0>;
phy-names = "pcie-phy2";
--- /dev/null
+From f383b0770612838e78986231710c0a3afee4db42 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 10 Jan 2022 12:49:27 +0100
+Subject: [PATCH 1/2] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add dt binding header for resets lines in Mediatek MT7621 SoCs.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mt7621-reset.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/mt7621-reset.h
+@@ -0,0 +1,37 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2021 Sergio Paracuellos
++ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
++ */
++
++#ifndef DT_BINDING_MT7621_RESET_H
++#define DT_BINDING_MT7621_RESET_H
++
++#define MT7621_RST_SYS 0
++#define MT7621_RST_MCM 2
++#define MT7621_RST_HSDMA 5
++#define MT7621_RST_FE 6
++#define MT7621_RST_SPDIFTX 7
++#define MT7621_RST_TIMER 8
++#define MT7621_RST_INT 9
++#define MT7621_RST_MC 10
++#define MT7621_RST_PCM 11
++#define MT7621_RST_PIO 13
++#define MT7621_RST_GDMA 14
++#define MT7621_RST_NFI 15
++#define MT7621_RST_I2C 16
++#define MT7621_RST_I2S 17
++#define MT7621_RST_SPI 18
++#define MT7621_RST_UART1 19
++#define MT7621_RST_UART2 20
++#define MT7621_RST_UART3 21
++#define MT7621_RST_ETH 23
++#define MT7621_RST_PCIE0 24
++#define MT7621_RST_PCIE1 25
++#define MT7621_RST_PCIE2 26
++#define MT7621_RST_AUX_STCK 28
++#define MT7621_RST_CRYPTO 29
++#define MT7621_RST_SDXC 30
++#define MT7621_RST_PPE 31
++
++#endif /* DT_BINDING_MT7621_RESET_H */
--- /dev/null
+From 64b2d6ffff862c0e7278198b4229e42e1abb3bb1 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 10 Jan 2022 12:49:30 +0100
+Subject: [PATCH 2/2] staging: mt7621-dts: align resets with binding documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
+to be used as a reset provider. Align reset related bits and system controller
+node with binding documentation along the dtsi file.
+
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20220110114930.1406665-5-sergio.paracuellos@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------
+ 1 file changed, 9 insertions(+), 12 deletions(-)
+
+--- a/drivers/staging/mt7621-dts/mt7621.dtsi
++++ b/drivers/staging/mt7621-dts/mt7621.dtsi
+@@ -1,6 +1,7 @@
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/mt7621-clk.h>
++#include <dt-bindings/reset/mt7621-reset.h>
+
+ / {
+ #address-cells = <1>;
+@@ -59,6 +60,7 @@
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
++ #reset-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+@@ -88,7 +90,7 @@
+
+ clocks = <&sysc MT7621_CLK_I2C>;
+ clock-names = "i2c";
+- resets = <&rstctrl 16>;
++ resets = <&sysc MT7621_RST_I2C>;
+ reset-names = "i2c";
+
+ #address-cells = <1>;
+@@ -161,7 +163,7 @@
+ clocks = <&sysc MT7621_CLK_SPI>;
+ clock-names = "spi";
+
+- resets = <&rstctrl 18>;
++ resets = <&sysc MT7621_RST_SPI>;
+ reset-names = "spi";
+
+ #address-cells = <1>;
+@@ -296,11 +298,6 @@
+ };
+ };
+
+- rstctrl: rstctrl {
+- compatible = "ralink,rt2880-reset";
+- #reset-cells = <1>;
+- };
+-
+ sdhci: sdhci@1e130000 {
+ status = "disabled";
+
+@@ -383,7 +380,7 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- resets = <&rstctrl 6 &rstctrl 23>;
++ resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
+ reset-names = "fe", "eth";
+
+ interrupt-parent = <&gic>;
+@@ -423,7 +420,7 @@
+ #size-cells = <0>;
+ reg = <0>;
+ mediatek,mcm;
+- resets = <&rstctrl 2>;
++ resets = <&sysc MT7621_RST_MCM>;
+ reset-names = "mcm";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+@@ -516,7 +513,7 @@
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rstctrl 24>;
++ resets = <&sysc MT7621_RST_PCIE0>;
+ clocks = <&sysc MT7621_CLK_PCIE0>;
+ phys = <&pcie0_phy 1>;
+ phy-names = "pcie-phy0";
+@@ -531,7 +528,7 @@
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rstctrl 25>;
++ resets = <&sysc MT7621_RST_PCIE1>;
+ clocks = <&sysc MT7621_CLK_PCIE1>;
+ phys = <&pcie0_phy 1>;
+ phy-names = "pcie-phy1";
+@@ -546,7 +543,7 @@
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rstctrl 26>;
++ resets = <&sysc MT7621_RST_PCIE2>;
+ clocks = <&sysc MT7621_CLK_PCIE2>;
+ phys = <&pcie2_phy 0>;
+ phy-names = "pcie-phy2";
--- /dev/null
+From 478b09fa2c00cbc40d25bc061befdf11f04a27ad Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Thu, 10 Feb 2022 10:48:58 +0100
+Subject: [PATCH 1/2] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
+
+Make system controller a reset provider for all the peripherals in the
+MT7621 SoC adding '#reset-cells' property.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ .../devicetree/bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+@@ -22,6 +22,11 @@ description: |
+
+ The clocks are provided inside a system controller node.
+
++ This node is also a reset provider for all the peripherals.
++
++ Reset related bits are defined in:
++ [2]: <include/dt-bindings/reset/mt7621-reset.h>.
++
+ properties:
+ compatible:
+ items:
+@@ -37,6 +42,12 @@ properties:
+ clocks.
+ const: 1
+
++ "#reset-cells":
++ description:
++ The first cell indicates the reset bit within the register, see
++ [2] for available resets.
++ const: 1
++
+ ralink,memctl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+@@ -61,6 +72,7 @@ examples:
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
++ #reset-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
--- /dev/null
+From 38a8553b0a22ed54f014d8402fedd268b529175c Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Thu, 10 Feb 2022 10:48:59 +0100
+Subject: [PATCH 2/2] clk: ralink: make system controller node a reset provider
+
+MT7621 system controller node is already providing the clocks for the whole
+system but must also serve as a reset provider. Hence, add reset controller
+related code to the clock driver itself. To get resets properly ready for
+the rest of the world we need to move platform driver initialization process
+to 'arch_initcall'.
+
+CC: Philipp Zabel <p.zabel@pengutronix.de>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20220210094859.927868-3-sergio.paracuellos@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 91 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/ralink/clk-mt7621.c
++++ b/drivers/clk/ralink/clk-mt7621.c
+@@ -11,14 +11,17 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/reset-controller.h>
+ #include <linux/slab.h>
+ #include <dt-bindings/clock/mt7621-clk.h>
++#include <dt-bindings/reset/mt7621-reset.h>
+
+ /* Configuration registers */
+ #define SYSC_REG_SYSTEM_CONFIG0 0x10
+ #define SYSC_REG_SYSTEM_CONFIG1 0x14
+ #define SYSC_REG_CLKCFG0 0x2c
+ #define SYSC_REG_CLKCFG1 0x30
++#define SYSC_REG_RESET_CTRL 0x34
+ #define SYSC_REG_CUR_CLK_STS 0x44
+ #define MEMC_REG_CPU_PLL 0x648
+
+@@ -398,6 +401,82 @@ free_clk_priv:
+ }
+ CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
+
++struct mt7621_rst {
++ struct reset_controller_dev rcdev;
++ struct regmap *sysc;
++};
++
++static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
++{
++ return container_of(dev, struct mt7621_rst, rcdev);
++}
++
++static int mt7621_assert_device(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct mt7621_rst *data = to_mt7621_rst(rcdev);
++ struct regmap *sysc = data->sysc;
++
++ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
++}
++
++static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct mt7621_rst *data = to_mt7621_rst(rcdev);
++ struct regmap *sysc = data->sysc;
++
++ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
++}
++
++static int mt7621_reset_device(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ int ret;
++
++ ret = mt7621_assert_device(rcdev, id);
++ if (ret < 0)
++ return ret;
++
++ return mt7621_deassert_device(rcdev, id);
++}
++
++static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
++ const struct of_phandle_args *reset_spec)
++{
++ unsigned long id = reset_spec->args[0];
++
++ if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)
++ return -EINVAL;
++
++ return id;
++}
++
++static const struct reset_control_ops reset_ops = {
++ .reset = mt7621_reset_device,
++ .assert = mt7621_assert_device,
++ .deassert = mt7621_deassert_device
++};
++
++static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
++{
++ struct mt7621_rst *rst_data;
++
++ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
++ if (!rst_data)
++ return -ENOMEM;
++
++ rst_data->sysc = sysc;
++ rst_data->rcdev.ops = &reset_ops;
++ rst_data->rcdev.owner = THIS_MODULE;
++ rst_data->rcdev.nr_resets = 32;
++ rst_data->rcdev.of_reset_n_cells = 1;
++ rst_data->rcdev.of_xlate = mt7621_rst_xlate;
++ rst_data->rcdev.of_node = dev_of_node(dev);
++
++ return devm_reset_controller_register(dev, &rst_data->rcdev);
++}
++
+ static int mt7621_clk_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+@@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platf
+ return ret;
+ }
+
++ ret = mt7621_reset_init(dev, priv->sysc);
++ if (ret) {
++ dev_err(dev, "Could not init reset controller\n");
++ return ret;
++ }
++
+ count = ARRAY_SIZE(mt7621_clks_base) +
+ ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
+@@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk
+ .of_match_table = mt7621_clk_of_match,
+ },
+ };
+-builtin_platform_driver(mt7621_clk_driver);
++
++static int __init mt7621_clk_reset_init(void)
++{
++ return platform_driver_register(&mt7621_clk_driver);
++}
++arch_initcall(mt7621_clk_reset_init);
--- /dev/null
+From bb3ababe7f986900672e0048153c31aa4a21f96b Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Sat, 17 Dec 2022 08:48:06 +0100
+Subject: [PATCH] MIPS: ralink: mt7621: avoid to init common ralink reset controller
+
+[ Upstream commit 76ce51798cb16738a4a28a6662e7344aaf7ef769 ]
+
+Commit 38a8553b0a22 ("clk: ralink: make system controller node a reset provider")
+make system controller a reset provider for mt7621 ralink SoCs. Ralink init code
+also tries to start previous common reset controller which at the end tries to
+find device tree node 'ralink,rt2880-reset'. mt7621 device tree file is not
+using at all this node anymore. Hence avoid to init this common reset controller
+for mt7621 ralink SoCs to avoid 'Failed to find reset controller node' boot
+error trace error.
+
+Fixes: 64b2d6ffff86 ("staging: mt7621-dts: align resets with binding documentation")
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/mips/ralink/of.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -21,6 +21,7 @@
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
+ #include <asm/prom.h>
++#include <asm/mach-ralink/ralink_regs.h>
+
+ #include "common.h"
+
+@@ -95,7 +96,8 @@ static int __init plat_of_setup(void)
+ __dt_register_buses(soc_info.compatible, "palmbus");
+
+ /* make sure that the reset controller is setup early */
+- ralink_rst_init();
++ if (ralink_soc != MT762X_SOC_MT7621AT)
++ ralink_rst_init();
+
+ return 0;
+ }
--- /dev/null
+From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 6 Feb 2023 09:33:05 +0100
+Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
+
+Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
+
+UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
+shift exponent 131072 is too large for 32-bit type 'long unsigned int'
+CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
+Stack : ...
+
+Call Trace:
+[<80009a58>] show_stack+0x38/0x118
+[<8045ce04>] dump_stack_lvl+0x60/0x80
+[<80458868>] ubsan_epilogue+0x10/0x54
+[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
+[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
+[<804bb774>] clk_core_is_enabled+0x34/0x90
+[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
+[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
+[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
+[<80aad900>] clk_disable_unused+0x78/0x120
+[<80002030>] do_one_initcall+0x54/0x1f0
+[<80a922a4>] kernel_init_freeable+0x280/0x31c
+[<808047c4>] kernel_init+0x20/0x118
+[<80003e58>] ret_from_kernel_thread+0x14/0x1c
+
+Shifting a value (131032) larger than the type (32 bit unsigned integer)
+is undefined behaviour in C.
+
+The problem is in 'mt7621_gate_is_enabled()' function which is using the
+'BIT()' kernel macro with the bit index for the clock gate to check if the
+bit is set. When the clock gates structure is created driver is already
+setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
+'BIT()' mask here. Removing it solve the problem and makes this function
+correct. However when clock gating is correctly working, the kernel starts
+disabling those clocks that are not requested. Some drivers for this SoC
+are older than this clock driver itself. So to avoid the kernel to disable
+clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
+flag on gates initialization code.
+
+Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/ralink/clk-mt7621.c
++++ b/drivers/clk/ralink/clk-mt7621.c
+@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
+ if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
+ return 0;
+
+- return val & BIT(clk_gate->bit_idx);
++ return val & clk_gate->bit_idx;
+ }
+
+ static const struct clk_ops mt7621_gate_ops = {
+@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
+ static int mt7621_gate_ops_init(struct device *dev,
+ struct mt7621_gate *sclk)
+ {
++ /*
++ * There are drivers for this SoC that are older
++ * than clock driver and are not prepared for the clock.
++ * We don't want the kernel to disable anything so we
++ * add CLK_IS_CRITICAL flag here.
++ */
+ struct clk_init_data init = {
+- .flags = CLK_SET_RATE_PARENT,
++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .num_parents = 1,
+ .parent_names = &sclk->parent_name,
+ .ops = &mt7621_gate_ops,
projects / openwrt / openwrt.git / commitdiff