target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/mii.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <ralink_regs.h>
  24
  25 #include "mtk_eth_soc.h"
  26 #include "gsw_mt7620.h"
  27
  28 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  29 {
  30         iowrite32(val, gsw->base + reg);
  31 }
  32
  33 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  34 {
  35         return ioread32(gsw->base + reg);
  36 }
  37
  38 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
  39 {
  40         struct fe_priv *priv = (struct fe_priv *)_priv;
  41         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  42         u32 status;
  43         int i, max = (gsw->port4_ephy) ? (4) : (3);
  44
  45         status = mtk_switch_r32(gsw, GSW_REG_ISR);
  46         if (status & PORT_IRQ_ST_CHG)
  47                 for (i = 0; i <= max; i++) {
  48                         u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
  49                         int link = status & 0x1;
  50
  51                         if (link != priv->link[i])
  52                                 mt7620_print_link_state(priv, i, link,
  53                                                         (status >> 2) & 3,
  54                                                         (status & 0x2));
  55
  56                         priv->link[i] = link;
  57                 }
  58         mt7620_handle_carrier(priv);
  59         mtk_switch_w32(gsw, status, GSW_REG_ISR);
  60
  61         return IRQ_HANDLED;
  62 }
  63
  64 static void gsw_reset_ephy(struct mt7620_gsw *gsw)
  65 {
  66         if (!gsw->rst_ephy)
  67                 return;
  68
  69         reset_control_assert(gsw->rst_ephy);
  70         usleep_range(10, 20);
  71         reset_control_deassert(gsw->rst_ephy);
  72         usleep_range(10, 20);
  73 }
  74
  75 static void mt7620_ephy_init(struct mt7620_gsw *gsw)
  76 {
  77         u32 i;
  78         u32 val;
  79         u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
  80
  81         if (gsw->ephy_disable) {
  82                 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
  83                         (gsw->ephy_base << 16) | (0x1f << 24),
  84                         GSW_REG_GPC1);
  85
  86                 pr_info("gsw: internal ephy disabled\n");
  87
  88                 return;
  89         } else if (gsw->ephy_base) {
  90                 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
  91                         (gsw->ephy_base << 16),
  92                         GSW_REG_GPC1);
  93                 gsw_reset_ephy(gsw);
  94
  95                 pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
  96         }
  97
  98         /* global page 4 */
  99         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
 100
 101         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
 102         if (is_BGA)
 103                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
 104         else
 105                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
 106
 107         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
 108         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
 109         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
 110         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
 111         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
 112         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
 113
 114         /* global page 3 */
 115         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
 116         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
 117
 118         /* global page 2 */
 119         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
 120         if (is_BGA) {
 121                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
 122                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
 123                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
 124                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
 125                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
 126                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
 127         } else {
 128                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
 129                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
 130                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
 131                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
 132                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
 133                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
 134         }
 135         /* global page 1 */
 136         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
 137         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
 138
 139         /* turn on all PHYs */
 140         for (i = 0; i <= 4; i++) {
 141                 val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
 142                 val &= ~BMCR_PDOWN;
 143                 val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
 144                 _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
 145         }
 146
 147         /* global page 0 */
 148         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
 149         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
 150         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
 151         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
 152         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
 153
 154         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
 155         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
 156         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
 157         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
 158
 159         /* global page 2 */
 160         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
 161         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
 162         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
 163         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
 164         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
 165
 166         /* setup port 4 */
 167         if (gsw->port4_ephy) {
 168                 val = rt_sysc_r32(SYSC_REG_CFG1);
 169
 170                 val |= 3 << 14;
 171                 rt_sysc_w32(val, SYSC_REG_CFG1);
 172                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);
 173                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
 174                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
 175                 pr_info("gsw: setting port4 to ephy mode\n");
 176         }
 177 }
 178
 179 static void mt7620_mac_init(struct mt7620_gsw *gsw)
 180 {
 181         /* Internal ethernet requires PCIe RC mode */
 182         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
 183
 184         /* Keep Global Clocks on Idle traffic */
 185         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 186
 187         /* Set Port 6 to Force Link 1G, Flow Control ON */
 188         mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 189
 190         /* Set Port 6 as CPU Port */
 191         mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
 192
 193         /* Enable MIB stats */
 194         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
 195 }
 196
 197 static const struct of_device_id mediatek_gsw_match[] = {
 198         { .compatible = "mediatek,mt7620-gsw" },
 199         {},
 200 };
 201 MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
 202
 203 int mtk_gsw_init(struct fe_priv *priv)
 204 {
 205         struct device_node *eth_node = priv->dev->of_node;
 206         struct device_node *phy_node, *mdiobus_node;
 207         struct device_node *np = priv->switch_np;
 208         struct platform_device *pdev = of_find_device_by_node(np);
 209         struct mt7620_gsw *gsw;
 210         const __be32 *id;
 211         int ret;
 212         u8 val;
 213
 214         if (!pdev)
 215                 return -ENODEV;
 216
 217         if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
 218                 return -EINVAL;
 219
 220         gsw = platform_get_drvdata(pdev);
 221         priv->soc->swpriv = gsw;
 222
 223         gsw->ephy_disable = of_property_read_bool(np, "mediatek,ephy-disable");
 224
 225         mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
 226         if (mdiobus_node) {
 227                 for_each_child_of_node(mdiobus_node, phy_node) {
 228                         id = of_get_property(phy_node, "reg", NULL);
 229                         if (id && (be32_to_cpu(*id) == 0x1f))
 230                                 gsw->ephy_disable = true;
 231                 }
 232
 233                 of_node_put(mdiobus_node);
 234         }
 235
 236         gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
 237
 238         if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
 239                 gsw->ephy_base = val;
 240         else
 241                 gsw->ephy_base = 0;
 242
 243         mt7620_mac_init(gsw);
 244
 245         mt7620_ephy_init(gsw);
 246
 247         if (gsw->irq) {
 248                 ret = request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
 249                                   "gsw", priv);
 250                 if (ret) {
 251                         dev_err(&pdev->dev, "Failed to request irq");
 252                         return ret;
 253                 }
 254                 mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 255         }
 256
 257         return 0;
 258 }
 259
 260 static int mt7620_gsw_probe(struct platform_device *pdev)
 261 {
 262         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 263         struct mt7620_gsw *gsw;
 264
 265         gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
 266         if (!gsw)
 267                 return -ENOMEM;
 268
 269         gsw->base = devm_ioremap_resource(&pdev->dev, res);
 270         if (IS_ERR(gsw->base))
 271                 return PTR_ERR(gsw->base);
 272
 273         gsw->dev = &pdev->dev;
 274
 275         gsw->irq = platform_get_irq(pdev, 0);
 276
 277         gsw->rst_ephy = devm_reset_control_get_exclusive(&pdev->dev, "ephy");
 278         if (IS_ERR(gsw->rst_ephy)) {
 279                 dev_err(gsw->dev, "failed to get EPHY reset: %pe\n", gsw->rst_ephy);
 280                 gsw->rst_ephy = NULL;
 281         }
 282
 283         platform_set_drvdata(pdev, gsw);
 284
 285         return 0;
 286 }
 287
 288 static int mt7620_gsw_remove(struct platform_device *pdev)
 289 {
 290         platform_set_drvdata(pdev, NULL);
 291
 292         return 0;
 293 }
 294
 295 static struct platform_driver gsw_driver = {
 296         .probe = mt7620_gsw_probe,
 297         .remove = mt7620_gsw_remove,
 298         .driver = {
 299                 .name = "mt7620-gsw",
 300                 .owner = THIS_MODULE,
 301                 .of_match_table = mediatek_gsw_match,
 302         },
 303 };
 304
 305 module_platform_driver(gsw_driver);
 306
 307 MODULE_LICENSE("GPL");
 308 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 309 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
 310 MODULE_VERSION(MTK_FE_DRV_VERSION);