1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
39 #include <asm/mach-ralink/ralink_regs.h>
41 #include "mtk_eth_soc.h"
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
64 #define SYSC_REG_RSTCTRL 0x34
66 static int fe_msg_level
= -1;
67 module_param_named(msg_level
, fe_msg_level
, int, 0);
68 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
70 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
71 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
72 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
73 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
74 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
75 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
76 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
77 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
78 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
79 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
80 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
81 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
82 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
83 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
84 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
85 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
86 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
89 static const u16
*fe_reg_table
= fe_reg_table_default
;
93 void (*action
)(struct fe_priv
*);
96 static void __iomem
*fe_base
;
98 void fe_w32(u32 val
, unsigned reg
)
100 __raw_writel(val
, fe_base
+ reg
);
103 u32
fe_r32(unsigned reg
)
105 return __raw_readl(fe_base
+ reg
);
108 void fe_reg_w32(u32 val
, enum fe_reg reg
)
110 fe_w32(val
, fe_reg_table
[reg
]);
113 u32
fe_reg_r32(enum fe_reg reg
)
115 return fe_r32(fe_reg_table
[reg
]);
118 void fe_m32(struct fe_priv
*eth
, u32 clear
, u32 set
, unsigned reg
)
122 spin_lock(ð
->page_lock
);
123 val
= __raw_readl(fe_base
+ reg
);
126 __raw_writel(val
, fe_base
+ reg
);
127 spin_unlock(ð
->page_lock
);
130 void fe_reset(u32 reset_bits
)
134 t
= rt_sysc_r32(SYSC_REG_RSTCTRL
);
136 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
137 usleep_range(10, 20);
140 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
141 usleep_range(10, 20);
144 static inline void fe_int_disable(u32 mask
)
146 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
147 FE_REG_FE_INT_ENABLE
);
149 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
152 static inline void fe_int_enable(u32 mask
)
154 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
155 FE_REG_FE_INT_ENABLE
);
157 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
160 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, unsigned char *mac
)
164 spin_lock_irqsave(&priv
->page_lock
, flags
);
165 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
166 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
168 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
171 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
173 int ret
= eth_mac_addr(dev
, p
);
176 struct fe_priv
*priv
= netdev_priv(dev
);
178 if (priv
->soc
->set_mac
)
179 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
181 fe_hw_set_macaddr(priv
, p
);
187 static inline int fe_max_frag_size(int mtu
)
189 /* make sure buf_size will be at least MAX_RX_LENGTH */
190 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
191 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
193 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
194 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
197 static inline int fe_max_buf_size(int frag_size
)
199 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
200 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
202 BUG_ON(buf_size
< MAX_RX_LENGTH
);
206 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
208 rxd
->rxd1
= dma_rxd
->rxd1
;
209 rxd
->rxd2
= dma_rxd
->rxd2
;
210 rxd
->rxd3
= dma_rxd
->rxd3
;
211 rxd
->rxd4
= dma_rxd
->rxd4
;
214 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
216 dma_txd
->txd1
= txd
->txd1
;
217 dma_txd
->txd3
= txd
->txd3
;
218 dma_txd
->txd4
= txd
->txd4
;
219 /* clean dma done flag last */
220 dma_txd
->txd2
= txd
->txd2
;
223 static void fe_clean_rx(struct fe_priv
*priv
)
225 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
230 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
231 if (ring
->rx_data
[i
]) {
232 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
233 dma_unmap_single(&priv
->netdev
->dev
,
234 ring
->rx_dma
[i
].rxd1
,
237 skb_free_frag(ring
->rx_data
[i
]);
240 kfree(ring
->rx_data
);
241 ring
->rx_data
= NULL
;
245 dma_free_coherent(priv
->dev
,
246 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
252 if (!ring
->frag_cache
.va
)
255 page
= virt_to_page(ring
->frag_cache
.va
);
256 __page_frag_cache_drain(page
, ring
->frag_cache
.pagecnt_bias
);
257 memset(&ring
->frag_cache
, 0, sizeof(ring
->frag_cache
));
260 static int fe_alloc_rx(struct fe_priv
*priv
)
262 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
265 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
270 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
271 ring
->rx_data
[i
] = page_frag_alloc(&ring
->frag_cache
,
274 if (!ring
->rx_data
[i
])
278 ring
->rx_dma
= dma_alloc_coherent(priv
->dev
,
279 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
281 GFP_ATOMIC
| __GFP_ZERO
);
285 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
289 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
290 dma_addr_t dma_addr
= dma_map_single(priv
->dev
,
291 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
294 if (unlikely(dma_mapping_error(priv
->dev
, dma_addr
)))
296 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
298 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
299 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
301 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
303 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
304 /* make sure that all changes to the dma ring are flushed before we
309 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
310 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
311 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
312 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
320 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
322 if (dma_unmap_len(tx_buf
, dma_len0
))
324 dma_unmap_addr(tx_buf
, dma_addr0
),
325 dma_unmap_len(tx_buf
, dma_len0
),
328 if (dma_unmap_len(tx_buf
, dma_len1
))
330 dma_unmap_addr(tx_buf
, dma_addr1
),
331 dma_unmap_len(tx_buf
, dma_len1
),
334 dma_unmap_len_set(tx_buf
, dma_addr0
, 0);
335 dma_unmap_len_set(tx_buf
, dma_addr1
, 0);
336 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
337 dev_kfree_skb_any(tx_buf
->skb
);
341 static void fe_clean_tx(struct fe_priv
*priv
)
344 struct device
*dev
= priv
->dev
;
345 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
348 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
349 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
355 dma_free_coherent(dev
,
356 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
362 netdev_reset_queue(priv
->netdev
);
365 static int fe_alloc_tx(struct fe_priv
*priv
)
368 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
370 ring
->tx_free_idx
= 0;
371 ring
->tx_next_idx
= 0;
372 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
375 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
380 ring
->tx_dma
= dma_alloc_coherent(priv
->dev
,
381 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
383 GFP_ATOMIC
| __GFP_ZERO
);
387 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
388 if (priv
->soc
->tx_dma
)
389 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
390 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
392 /* make sure that all changes to the dma ring are flushed before we
397 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
398 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
399 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
400 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
408 static int fe_init_dma(struct fe_priv
*priv
)
412 err
= fe_alloc_tx(priv
);
416 err
= fe_alloc_rx(priv
);
423 static void fe_free_dma(struct fe_priv
*priv
)
429 void fe_stats_update(struct fe_priv
*priv
)
431 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
432 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
435 u64_stats_update_begin(&hwstats
->syncp
);
437 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
438 hwstats
->rx_bytes
+= fe_r32(base
);
439 stats
= fe_r32(base
+ 0x04);
441 hwstats
->rx_bytes
+= (stats
<< 32);
442 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
443 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
444 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
445 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
446 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
447 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
448 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
449 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
450 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
451 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
452 stats
= fe_r32(base
+ 0x34);
454 hwstats
->tx_bytes
+= (stats
<< 32);
455 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
457 hwstats
->tx_bytes
+= fe_r32(base
);
458 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
459 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
460 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
461 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
462 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
463 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
464 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
465 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
466 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
467 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
468 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
471 u64_stats_update_end(&hwstats
->syncp
);
474 static void fe_get_stats64(struct net_device
*dev
,
475 struct rtnl_link_stats64
*storage
)
477 struct fe_priv
*priv
= netdev_priv(dev
);
478 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
479 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
483 netdev_stats_to_stats64(storage
, &dev
->stats
);
487 if (netif_running(dev
) && netif_device_present(dev
)) {
488 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
489 fe_stats_update(priv
);
490 spin_unlock_bh(&hwstats
->stats_lock
);
495 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
496 storage
->rx_packets
= hwstats
->rx_packets
;
497 storage
->tx_packets
= hwstats
->tx_packets
;
498 storage
->rx_bytes
= hwstats
->rx_bytes
;
499 storage
->tx_bytes
= hwstats
->tx_bytes
;
500 storage
->collisions
= hwstats
->tx_collisions
;
501 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
502 hwstats
->rx_long_errors
;
503 storage
->rx_over_errors
= hwstats
->rx_overflow
;
504 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
505 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
506 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
507 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
509 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
510 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
511 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
514 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
515 __be16 proto
, u16 vid
)
517 struct fe_priv
*priv
= netdev_priv(dev
);
518 u32 idx
= (vid
& 0xf);
521 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
522 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
525 if (test_bit(idx
, &priv
->vlan_map
)) {
526 netdev_warn(dev
, "disable tx vlan offload\n");
527 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
528 netdev_update_features(dev
);
530 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
534 vlan_cfg
|= (vid
<< 16);
536 vlan_cfg
&= 0xffff0000;
539 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
541 set_bit(idx
, &priv
->vlan_map
);
547 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
548 __be16 proto
, u16 vid
)
550 struct fe_priv
*priv
= netdev_priv(dev
);
551 u32 idx
= (vid
& 0xf);
553 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
554 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
557 clear_bit(idx
, &priv
->vlan_map
);
562 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
565 return (u32
)(ring
->tx_ring_size
-
566 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
567 (ring
->tx_ring_size
- 1)));
570 struct fe_map_state
{
572 struct fe_tx_dma txd
;
578 static void fe_tx_dma_write_desc(struct fe_tx_ring
*ring
, struct fe_map_state
*st
)
580 fe_set_txd(&st
->txd
, &ring
->tx_dma
[st
->ring_idx
]);
581 memset(&st
->txd
, 0, sizeof(st
->txd
));
582 st
->txd
.txd4
= st
->def_txd4
;
583 st
->ring_idx
= NEXT_TX_DESP_IDX(st
->ring_idx
);
586 static int __fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
587 struct page
*page
, size_t offset
, size_t size
)
589 struct device
*dev
= st
->dev
;
590 struct fe_tx_buf
*tx_buf
;
591 dma_addr_t mapped_addr
;
593 mapped_addr
= dma_map_page(dev
, page
, offset
, size
, DMA_TO_DEVICE
);
594 if (unlikely(dma_mapping_error(dev
, mapped_addr
)))
597 if (st
->i
&& !(st
->i
& 1))
598 fe_tx_dma_write_desc(ring
, st
);
600 tx_buf
= &ring
->tx_buf
[st
->ring_idx
];
602 st
->txd
.txd3
= mapped_addr
;
603 st
->txd
.txd2
|= TX_DMA_PLEN1(size
);
604 dma_unmap_addr_set(tx_buf
, dma_addr1
, mapped_addr
);
605 dma_unmap_len_set(tx_buf
, dma_len1
, size
);
607 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
608 st
->txd
.txd1
= mapped_addr
;
609 st
->txd
.txd2
= TX_DMA_PLEN0(size
);
610 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
611 dma_unmap_len_set(tx_buf
, dma_len0
, size
);
618 static int fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
619 struct page
*page
, size_t offset
, size_t size
)
625 cur_size
= min_t(size_t, size
, TX_DMA_BUF_LEN
);
627 ret
= __fe_tx_dma_map_page(ring
, st
, page
, offset
, cur_size
);
638 static int fe_tx_dma_map_skb(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
641 struct page
*page
= virt_to_page(skb
->data
);
642 size_t offset
= offset_in_page(skb
->data
);
643 size_t size
= skb_headlen(skb
);
645 return fe_tx_dma_map_page(ring
, st
, page
, offset
, size
);
648 static inline struct sk_buff
*
649 fe_next_frag(struct sk_buff
*head
, struct sk_buff
*skb
)
654 if (skb_has_frag_list(skb
))
655 return skb_shinfo(skb
)->frag_list
;
661 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
662 int tx_num
, struct fe_tx_ring
*ring
)
664 struct fe_priv
*priv
= netdev_priv(dev
);
665 struct fe_map_state st
= {
667 .ring_idx
= ring
->tx_next_idx
,
669 struct sk_buff
*head
= skb
;
670 struct fe_tx_buf
*tx_buf
;
671 unsigned int nr_frags
;
674 /* init tx descriptor */
675 if (priv
->soc
->tx_dma
)
676 priv
->soc
->tx_dma(&st
.txd
);
678 st
.txd
.txd4
= TX_DMA_DESP4_DEF
;
679 st
.def_txd4
= st
.txd
.txd4
;
681 /* TX Checksum offload */
682 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
683 st
.txd
.txd4
|= TX_DMA_CHKSUM
;
685 /* VLAN header offload */
686 if (skb_vlan_tag_present(skb
)) {
687 u16 tag
= skb_vlan_tag_get(skb
);
689 if (IS_ENABLED(CONFIG_SOC_MT7621
))
690 st
.txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
692 st
.txd
.txd4
|= TX_DMA_INS_VLAN
|
693 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
697 /* TSO: fill MSS info in tcp checksum field */
698 if (skb_is_gso(skb
)) {
699 if (skb_cow_head(skb
, 0)) {
700 netif_warn(priv
, tx_err
, dev
,
701 "GSO expand head fail.\n");
704 if (skb_shinfo(skb
)->gso_type
&
705 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
706 st
.txd
.txd4
|= TX_DMA_TSO
;
707 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
712 if (skb_headlen(skb
) && fe_tx_dma_map_skb(ring
, &st
, skb
))
716 nr_frags
= skb_shinfo(skb
)->nr_frags
;
717 for (i
= 0; i
< nr_frags
; i
++) {
718 struct skb_frag_struct
*frag
;
720 frag
= &skb_shinfo(skb
)->frags
[i
];
721 if (fe_tx_dma_map_page(ring
, &st
, skb_frag_page(frag
),
722 frag
->page_offset
, skb_frag_size(frag
)))
726 skb
= fe_next_frag(head
, skb
);
730 /* set last segment */
732 st
.txd
.txd2
|= TX_DMA_LS0
;
734 st
.txd
.txd2
|= TX_DMA_LS1
;
736 /* store skb to cleanup */
737 tx_buf
= &ring
->tx_buf
[st
.ring_idx
];
740 netdev_sent_queue(dev
, head
->len
);
741 skb_tx_timestamp(head
);
743 fe_tx_dma_write_desc(ring
, &st
);
744 ring
->tx_next_idx
= st
.ring_idx
;
746 /* make sure that all changes to the dma ring are flushed before we
750 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
751 netif_stop_queue(dev
);
753 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
754 netif_wake_queue(dev
);
757 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !head
->xmit_more
)
758 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
763 j
= ring
->tx_next_idx
;
764 for (i
= 0; i
< tx_num
; i
++) {
766 fe_txd_unmap(priv
->dev
, &ring
->tx_buf
[j
]);
767 ring
->tx_dma
[j
].txd2
= TX_DMA_DESP2_DEF
;
769 j
= NEXT_TX_DESP_IDX(j
);
771 /* make sure that all changes to the dma ring are flushed before we
780 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
786 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
787 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
788 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
791 if (skb_vlan_tag_present(skb
))
793 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
795 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
800 if (skb
->len
< len
) {
801 ret
= skb_pad(skb
, len
- skb
->len
);
805 skb_set_tail_pointer(skb
, len
);
812 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
814 struct sk_buff
*head
= skb
;
816 struct skb_frag_struct
*frag
;
820 if (skb_is_gso(skb
)) {
821 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
822 frag
= &skb_shinfo(skb
)->frags
[i
];
823 nfrags
+= DIV_ROUND_UP(frag
->size
, TX_DMA_BUF_LEN
);
826 nfrags
+= skb_shinfo(skb
)->nr_frags
;
829 skb
= fe_next_frag(head
, skb
);
833 return DIV_ROUND_UP(nfrags
, 2);
836 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
838 struct fe_priv
*priv
= netdev_priv(dev
);
839 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
840 struct net_device_stats
*stats
= &dev
->stats
;
844 if (fe_skb_padto(skb
, priv
)) {
845 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
849 tx_num
= fe_cal_txd_req(skb
);
850 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
851 netif_stop_queue(dev
);
852 netif_err(priv
, tx_queued
, dev
,
853 "Tx Ring full when queue awake!\n");
854 return NETDEV_TX_BUSY
;
857 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
861 stats
->tx_bytes
+= len
;
867 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
868 struct fe_priv
*priv
, u32 rx_intr
)
870 struct net_device
*netdev
= priv
->netdev
;
871 struct net_device_stats
*stats
= &netdev
->stats
;
872 struct fe_soc_data
*soc
= priv
->soc
;
873 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
874 int idx
= ring
->rx_calc_idx
;
878 struct fe_rx_dma
*rxd
, trxd
;
881 if (netdev
->features
& NETIF_F_RXCSUM
)
882 checksum_bit
= soc
->checksum_bit
;
886 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
891 while (done
< budget
) {
895 idx
= NEXT_RX_DESP_IDX(idx
);
896 rxd
= &ring
->rx_dma
[idx
];
897 data
= ring
->rx_data
[idx
];
899 fe_get_rxd(&trxd
, rxd
);
900 if (!(trxd
.rxd2
& RX_DMA_DONE
))
903 /* alloc new buffer */
904 new_data
= page_frag_alloc(&ring
->frag_cache
, ring
->frag_size
,
906 if (unlikely(!new_data
)) {
910 dma_addr
= dma_map_single(priv
->dev
,
911 new_data
+ NET_SKB_PAD
+ pad
,
914 if (unlikely(dma_mapping_error(priv
->dev
, dma_addr
))) {
915 skb_free_frag(new_data
);
920 skb
= build_skb(data
, ring
->frag_size
);
921 if (unlikely(!skb
)) {
922 skb_free_frag(new_data
);
925 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
927 dma_unmap_single(priv
->dev
, trxd
.rxd1
,
928 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
929 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
931 skb_put(skb
, pktlen
);
932 if (trxd
.rxd4
& checksum_bit
)
933 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
935 skb_checksum_none_assert(skb
);
936 skb
->protocol
= eth_type_trans(skb
, netdev
);
938 if (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
939 RX_DMA_VID(trxd
.rxd3
))
940 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
941 RX_DMA_VID(trxd
.rxd3
));
943 #ifdef CONFIG_NET_RALINK_OFFLOAD
944 if (mtk_offload_check_rx(priv
, skb
, trxd
.rxd4
) == 0) {
947 stats
->rx_bytes
+= pktlen
;
949 napi_gro_receive(napi
, skb
);
950 #ifdef CONFIG_NET_RALINK_OFFLOAD
955 ring
->rx_data
[idx
] = new_data
;
956 rxd
->rxd1
= (unsigned int)dma_addr
;
959 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
960 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
962 rxd
->rxd2
= RX_DMA_LSO
;
964 ring
->rx_calc_idx
= idx
;
965 /* make sure that all changes to the dma ring are flushed before
969 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
974 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
979 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
982 struct net_device
*netdev
= priv
->netdev
;
983 unsigned int bytes_compl
= 0;
985 struct fe_tx_buf
*tx_buf
;
988 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
990 idx
= ring
->tx_free_idx
;
991 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
993 while ((idx
!= hwidx
) && budget
) {
994 tx_buf
= &ring
->tx_buf
[idx
];
1000 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
1001 bytes_compl
+= skb
->len
;
1005 fe_txd_unmap(priv
->dev
, tx_buf
);
1006 idx
= NEXT_TX_DESP_IDX(idx
);
1008 ring
->tx_free_idx
= idx
;
1011 /* read hw index again make sure no new tx packet */
1012 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
1014 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
1022 netdev_completed_queue(netdev
, done
, bytes_compl
);
1024 if (unlikely(netif_queue_stopped(netdev
) &&
1025 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
1026 netif_wake_queue(netdev
);
1032 static int fe_poll(struct napi_struct
*napi
, int budget
)
1034 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
1035 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
1036 int tx_done
, rx_done
, tx_again
;
1037 u32 status
, fe_status
, status_reg
, mask
;
1038 u32 tx_intr
, rx_intr
, status_intr
;
1040 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1042 tx_intr
= priv
->soc
->tx_int
;
1043 rx_intr
= priv
->soc
->rx_int
;
1044 status_intr
= priv
->soc
->status_int
;
1049 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
1050 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
1051 status_reg
= FE_REG_FE_INT_STATUS2
;
1053 status_reg
= FE_REG_FE_INT_STATUS
;
1056 if (status
& tx_intr
)
1057 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
1059 if (status
& rx_intr
)
1060 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
1062 if (unlikely(fe_status
& status_intr
)) {
1063 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
1064 fe_stats_update(priv
);
1065 spin_unlock(&hwstat
->stats_lock
);
1067 fe_reg_w32(status_intr
, status_reg
);
1070 if (unlikely(netif_msg_intr(priv
))) {
1071 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
1072 netdev_info(priv
->netdev
,
1073 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1074 tx_done
, rx_done
, status
, mask
);
1077 if (!tx_again
&& (rx_done
< budget
)) {
1078 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1079 if (status
& (tx_intr
| rx_intr
)) {
1080 /* let napi poll again */
1085 napi_complete_done(napi
, rx_done
);
1086 fe_int_enable(tx_intr
| rx_intr
);
1095 static void fe_tx_timeout(struct net_device
*dev
)
1097 struct fe_priv
*priv
= netdev_priv(dev
);
1098 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1100 priv
->netdev
->stats
.tx_errors
++;
1101 netif_err(priv
, tx_err
, dev
,
1102 "transmit timed out\n");
1103 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1104 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1105 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1106 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1107 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1108 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1109 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1110 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1113 netif_info(priv
, drv
, dev
,
1114 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1115 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1116 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1117 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1118 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1120 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1121 schedule_work(&priv
->pending_work
);
1124 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1126 struct fe_priv
*priv
= netdev_priv(dev
);
1127 u32 status
, int_mask
;
1129 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1131 if (unlikely(!status
))
1134 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1135 if (likely(status
& int_mask
)) {
1136 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1137 fe_int_disable(int_mask
);
1138 __napi_schedule(&priv
->rx_napi
);
1141 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1147 #ifdef CONFIG_NET_POLL_CONTROLLER
1148 static void fe_poll_controller(struct net_device
*dev
)
1150 struct fe_priv
*priv
= netdev_priv(dev
);
1151 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1153 fe_int_disable(int_mask
);
1154 fe_handle_irq(dev
->irq
, dev
);
1155 fe_int_enable(int_mask
);
1159 int fe_set_clock_cycle(struct fe_priv
*priv
)
1161 unsigned long sysclk
= priv
->sysclk
;
1163 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1164 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1166 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1167 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1173 void fe_fwd_config(struct fe_priv
*priv
)
1177 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1179 /* disable jumbo frame */
1180 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1181 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1183 /* set unicast/multicast/broadcast frame to cpu */
1186 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1189 static void fe_rxcsum_config(bool enable
)
1192 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1193 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1196 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1197 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1201 static void fe_txcsum_config(bool enable
)
1204 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1205 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1208 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1209 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1213 void fe_csum_config(struct fe_priv
*priv
)
1215 struct net_device
*dev
= priv_netdev(priv
);
1217 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1218 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1221 static int fe_hw_init(struct net_device
*dev
)
1223 struct fe_priv
*priv
= netdev_priv(dev
);
1226 err
= devm_request_irq(priv
->dev
, dev
->irq
, fe_handle_irq
, 0,
1227 dev_name(priv
->dev
), dev
);
1231 if (priv
->soc
->set_mac
)
1232 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1234 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1236 /* disable delay interrupt */
1237 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1239 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1241 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1242 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1243 for (i
= 0; i
< 16; i
+= 2)
1244 fe_w32(((i
+ 1) << 16) + i
,
1245 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1248 if (priv
->soc
->fwd_config(priv
))
1249 netdev_err(dev
, "unable to get clock\n");
1251 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1252 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1253 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1259 static int fe_open(struct net_device
*dev
)
1261 struct fe_priv
*priv
= netdev_priv(dev
);
1262 unsigned long flags
;
1266 err
= fe_init_dma(priv
);
1272 spin_lock_irqsave(&priv
->page_lock
, flags
);
1274 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1275 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1276 val
|= FE_RX_2B_OFFSET
;
1277 val
|= priv
->soc
->pdma_glo_cfg
;
1278 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1280 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1283 priv
->phy
->start(priv
);
1285 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1286 netif_carrier_on(dev
);
1288 napi_enable(&priv
->rx_napi
);
1289 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1290 netif_start_queue(dev
);
1291 #ifdef CONFIG_NET_RALINK_OFFLOAD
1292 mtk_ppe_probe(priv
);
1298 static int fe_stop(struct net_device
*dev
)
1300 struct fe_priv
*priv
= netdev_priv(dev
);
1301 unsigned long flags
;
1304 netif_tx_disable(dev
);
1305 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1306 napi_disable(&priv
->rx_napi
);
1309 priv
->phy
->stop(priv
);
1311 spin_lock_irqsave(&priv
->page_lock
, flags
);
1313 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1314 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1315 FE_REG_PDMA_GLO_CFG
);
1316 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1319 for (i
= 0; i
< 10; i
++) {
1320 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1321 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1330 #ifdef CONFIG_NET_RALINK_OFFLOAD
1331 mtk_ppe_remove(priv
);
1337 static void fe_reset_phy(struct fe_priv
*priv
)
1340 struct gpio_desc
*phy_reset
;
1342 phy_reset
= devm_gpiod_get_optional(priv
->dev
, "phy-reset",
1347 if (IS_ERR(phy_reset
)) {
1348 dev_err(priv
->dev
, "Error acquiring reset gpio pins: %ld\n",
1349 PTR_ERR(phy_reset
));
1353 err
= of_property_read_u32(priv
->dev
->of_node
, "phy-reset-duration",
1355 if (!err
&& msec
> 1000)
1361 usleep_range(msec
* 1000, msec
* 1000 + 1000);
1363 gpiod_set_value(phy_reset
, 0);
1366 static int __init
fe_init(struct net_device
*dev
)
1368 struct fe_priv
*priv
= netdev_priv(dev
);
1369 struct device_node
*port
;
1370 const char *mac_addr
;
1373 priv
->soc
->reset_fe();
1375 if (priv
->soc
->switch_init
)
1376 if (priv
->soc
->switch_init(priv
)) {
1377 netdev_err(dev
, "failed to initialize switch core\n");
1383 mac_addr
= of_get_mac_address(priv
->dev
->of_node
);
1385 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1387 /* If the mac address is invalid, use random mac address */
1388 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1389 eth_hw_addr_random(dev
);
1390 dev_err(priv
->dev
, "generated random MAC address %pM\n",
1394 err
= fe_mdio_init(priv
);
1398 if (priv
->soc
->port_init
)
1399 for_each_child_of_node(priv
->dev
->of_node
, port
)
1400 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1401 of_device_is_available(port
))
1402 priv
->soc
->port_init(priv
, port
);
1405 err
= priv
->phy
->connect(priv
);
1407 goto err_phy_disconnect
;
1410 err
= fe_hw_init(dev
);
1412 goto err_phy_disconnect
;
1414 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1415 priv
->soc
->switch_config(priv
);
1421 priv
->phy
->disconnect(priv
);
1422 fe_mdio_cleanup(priv
);
1427 static void fe_uninit(struct net_device
*dev
)
1429 struct fe_priv
*priv
= netdev_priv(dev
);
1432 priv
->phy
->disconnect(priv
);
1433 fe_mdio_cleanup(priv
);
1435 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1436 free_irq(dev
->irq
, dev
);
1439 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1441 struct fe_priv
*priv
= netdev_priv(dev
);
1447 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1450 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1452 struct fe_priv
*priv
= netdev_priv(dev
);
1453 int frag_size
, old_mtu
;
1459 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1462 /* return early if the buffer sizes will not change */
1463 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1465 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1468 if (new_mtu
<= ETH_DATA_LEN
)
1469 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1471 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1472 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1474 if (!netif_running(dev
))
1478 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1479 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1480 if (new_mtu
<= ETH_DATA_LEN
) {
1481 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1483 frag_size
= fe_max_frag_size(new_mtu
);
1484 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1485 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1486 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1488 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1491 return fe_open(dev
);
1494 #ifdef CONFIG_NET_RALINK_OFFLOAD
1496 fe_flow_offload(enum flow_offload_type type
, struct flow_offload
*flow
,
1497 struct flow_offload_hw_path
*src
,
1498 struct flow_offload_hw_path
*dest
)
1500 struct fe_priv
*priv
;
1502 if (src
->dev
!= dest
->dev
)
1505 priv
= netdev_priv(src
->dev
);
1507 return mtk_flow_offload(priv
, type
, flow
, src
, dest
);
1511 static const struct net_device_ops fe_netdev_ops
= {
1512 .ndo_init
= fe_init
,
1513 .ndo_uninit
= fe_uninit
,
1514 .ndo_open
= fe_open
,
1515 .ndo_stop
= fe_stop
,
1516 .ndo_start_xmit
= fe_start_xmit
,
1517 .ndo_set_mac_address
= fe_set_mac_address
,
1518 .ndo_validate_addr
= eth_validate_addr
,
1519 .ndo_do_ioctl
= fe_do_ioctl
,
1520 .ndo_change_mtu
= fe_change_mtu
,
1521 .ndo_tx_timeout
= fe_tx_timeout
,
1522 .ndo_get_stats64
= fe_get_stats64
,
1523 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1524 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1525 #ifdef CONFIG_NET_POLL_CONTROLLER
1526 .ndo_poll_controller
= fe_poll_controller
,
1528 #ifdef CONFIG_NET_RALINK_OFFLOAD
1529 .ndo_flow_offload
= fe_flow_offload
,
1533 static void fe_reset_pending(struct fe_priv
*priv
)
1535 struct net_device
*dev
= priv
->netdev
;
1543 netif_alert(priv
, ifup
, dev
,
1544 "Driver up/down cycle failed, closing device.\n");
1550 static const struct fe_work_t fe_work
[] = {
1551 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1554 static void fe_pending_work(struct work_struct
*work
)
1556 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1560 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1561 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1562 priv
->pending_flags
);
1564 fe_work
[i
].action(priv
);
1568 static int fe_probe(struct platform_device
*pdev
)
1570 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1571 const struct of_device_id
*match
;
1572 struct fe_soc_data
*soc
;
1573 struct net_device
*netdev
;
1574 struct fe_priv
*priv
;
1576 int err
, napi_weight
;
1578 device_reset(&pdev
->dev
);
1580 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1581 soc
= (struct fe_soc_data
*)match
->data
;
1584 fe_reg_table
= soc
->reg_table
;
1586 soc
->reg_table
= fe_reg_table
;
1588 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1589 if (IS_ERR(fe_base
)) {
1590 err
= -EADDRNOTAVAIL
;
1594 netdev
= alloc_etherdev(sizeof(*priv
));
1596 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1601 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1602 netdev
->netdev_ops
= &fe_netdev_ops
;
1603 netdev
->base_addr
= (unsigned long)fe_base
;
1605 netdev
->irq
= platform_get_irq(pdev
, 0);
1606 if (netdev
->irq
< 0) {
1607 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1613 soc
->init_data(soc
, netdev
);
1614 netdev
->vlan_features
= netdev
->hw_features
&
1615 ~(NETIF_F_HW_VLAN_CTAG_TX
|
1616 NETIF_F_HW_VLAN_CTAG_RX
);
1617 netdev
->features
|= netdev
->hw_features
;
1619 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1620 netdev
->max_mtu
= 2048;
1622 /* fake rx vlan filter func. to support tx vlan offload func */
1623 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1624 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1626 priv
= netdev_priv(netdev
);
1627 spin_lock_init(&priv
->page_lock
);
1628 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1629 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1630 if (!priv
->hw_stats
) {
1634 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1637 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1638 if (!IS_ERR(sysclk
)) {
1639 priv
->sysclk
= clk_get_rate(sysclk
);
1640 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1641 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1646 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1647 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1648 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1653 priv
->netdev
= netdev
;
1654 priv
->dev
= &pdev
->dev
;
1656 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1657 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1658 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1659 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1660 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1661 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1662 u64_stats_init(&priv
->hw_stats
->syncp
);
1665 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1667 priv
->tx_ring
.tx_ring_size
*= 4;
1668 priv
->rx_ring
.rx_ring_size
*= 4;
1670 netif_napi_add(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1671 fe_set_ethtool_ops(netdev
);
1673 err
= register_netdev(netdev
);
1675 dev_err(&pdev
->dev
, "error bringing up device\n");
1679 platform_set_drvdata(pdev
, netdev
);
1681 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1682 netdev
->base_addr
, netdev
->irq
);
1687 free_netdev(netdev
);
1689 devm_iounmap(&pdev
->dev
, fe_base
);
1694 static int fe_remove(struct platform_device
*pdev
)
1696 struct net_device
*dev
= platform_get_drvdata(pdev
);
1697 struct fe_priv
*priv
= netdev_priv(dev
);
1699 netif_napi_del(&priv
->rx_napi
);
1700 kfree(priv
->hw_stats
);
1702 cancel_work_sync(&priv
->pending_work
);
1704 unregister_netdev(dev
);
1706 platform_set_drvdata(pdev
, NULL
);
1711 static struct platform_driver fe_driver
= {
1713 .remove
= fe_remove
,
1715 .name
= "mtk_soc_eth",
1716 .owner
= THIS_MODULE
,
1717 .of_match_table
= of_fe_match
,
1721 module_platform_driver(fe_driver
);
1723 MODULE_LICENSE("GPL");
1724 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1725 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1726 MODULE_VERSION(MTK_FE_DRV_VERSION
);