1 From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Aug 2014 10:53:40 +0200
4 Subject: [PATCH 51/57] SPI: MIPS: ralink: add rt5350 dual SPI support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
9 drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
10 1 file changed, 205 insertions(+), 13 deletions(-)
12 --- a/drivers/spi/spi-rt2880.c
13 +++ b/drivers/spi/spi-rt2880.c
16 #include <linux/reset.h>
17 #include <linux/spi/spi.h>
18 +#include <linux/of_device.h>
19 #include <linux/platform_device.h>
21 +#include <ralink_regs.h>
23 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
25 #define DRIVER_NAME "spi-rt2880"
26 -/* only one slave is supported*/
27 -#define RALINK_NUM_CHIPSELECTS 1
29 #define RALINK_SPI_WAIT_MAX_LOOP 2000
31 -#define RAMIPS_SPI_STAT 0x00
32 -#define RAMIPS_SPI_CFG 0x10
33 -#define RAMIPS_SPI_CTL 0x14
34 -#define RAMIPS_SPI_DATA 0x20
35 -#define RAMIPS_SPI_FIFO_STAT 0x38
36 +#define RAMIPS_SPI_DEV_OFFSET 0x40
38 +#define RAMIPS_SPI_STAT(cs) (0x00 + (cs * RAMIPS_SPI_DEV_OFFSET))
39 +#define RAMIPS_SPI_CFG(cs) (0x10 + (cs * RAMIPS_SPI_DEV_OFFSET))
40 +#define RAMIPS_SPI_CTL(cs) (0x14 + (cs * RAMIPS_SPI_DEV_OFFSET))
41 +#define RAMIPS_SPI_DATA(cs) (0x20 + (cs * RAMIPS_SPI_DEV_OFFSET))
42 +#define RAMIPS_SPI_FIFO_STAT(cs) (0x38 + (cs * RAMIPS_SPI_DEV_OFFSET))
43 +#define RAMIPS_SPI_ARBITER 0xF0
45 /* SPISTAT register bit field */
46 #define SPISTAT_BUSY BIT(0)
48 /* SPIFIFOSTAT register bit field */
49 #define SPIFIFOSTAT_TXFULL BIT(17)
51 +#define SPICTL_ARB_EN BIT(31)
52 +#define SPI1_POR BIT(1)
53 +#define SPI0_POR BIT(0)
55 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
59 +struct rt2880_spi_ops {
60 + void (*init_hw)(struct rt2880_spi *rs);
65 struct spi_master *master;
67 @@ -70,6 +89,8 @@ struct rt2880_spi {
72 + struct rt2880_spi_ops *ops;
75 static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
76 @@ -115,6 +136,7 @@ static inline void rt2880_spi_clrbits(st
78 static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
80 + int cs = spi->chip_select;
81 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
84 @@ -142,9 +164,9 @@ static int rt2880_spi_baudrate_set(struc
85 prescale = ilog2(rate / 2);
86 dev_dbg(&spi->dev, "prescale:%u\n", prescale);
88 - reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
89 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
90 reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
91 - rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
92 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
96 @@ -157,7 +179,8 @@ rt2880_spi_setup_transfer(struct spi_dev
98 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
99 unsigned int speed = spi->max_speed_hz;
101 + int rc, cs = spi->chip_select;
104 if ((t != NULL) && t->speed_hz)
106 @@ -169,25 +192,68 @@ rt2880_spi_setup_transfer(struct spi_dev
110 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
112 + reg = (reg & ~SPICFG_MSBFIRST);
113 + if (!(spi->mode & SPI_LSB_FIRST))
114 + reg |= SPICFG_MSBFIRST;
116 + reg = (reg & ~(SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING |SPICFG_TXCLKEDGE_FALLING));
117 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
119 + reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
122 + reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
125 + reg |= SPICFG_RXCLKEDGE_FALLING;
128 + reg |= SPICFG_TXCLKEDGE_FALLING;
132 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
134 + reg = SPICTL_ARB_EN;
135 + if (spi->mode & SPI_CS_HIGH) {
146 + rt2880_spi_write(rs, RAMIPS_SPI_ARBITER, reg);
151 -static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
152 +static void rt2880_spi_set_cs(struct spi_device *spi, int enable)
154 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
155 + int cs = spi->chip_select;
158 - rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
159 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
161 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
162 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
165 -static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
166 +static inline int rt2880_spi_wait_till_ready(struct spi_device *spi)
168 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
169 + int cs = spi->chip_select;
172 for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
175 - status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
176 + status = rt2880_spi_read(rs, RAMIPS_SPI_STAT(cs));
177 if ((status & SPISTAT_BUSY) == 0)
180 @@ -199,9 +265,10 @@ static inline int rt2880_spi_wait_till_r
184 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
185 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
187 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
188 + int cs = spi->chip_select;
190 u8 *rx = xfer->rx_buf;
191 const u8 *tx = xfer->tx_buf;
192 @@ -213,9 +280,9 @@ rt2880_spi_write_read(struct spi_device
195 for (count = 0; count < xfer->len; count++) {
196 - rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
197 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
198 - err = rt2880_spi_wait_till_ready(rs);
199 + rt2880_spi_write(rs, RAMIPS_SPI_DATA(cs), tx[count]);
200 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTWR);
201 + err = rt2880_spi_wait_till_ready(spi);
203 dev_err(&spi->dev, "TX failed, err=%d\n", err);
205 @@ -225,13 +292,13 @@ rt2880_spi_write_read(struct spi_device
208 for (count = 0; count < xfer->len; count++) {
209 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
210 - err = rt2880_spi_wait_till_ready(rs);
211 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTRD);
212 + err = rt2880_spi_wait_till_ready(spi);
214 dev_err(&spi->dev, "RX failed, err=%d\n", err);
217 - rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
218 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA(cs));
222 @@ -280,25 +347,25 @@ static int rt2880_spi_transfer_one_messa
226 - rt2880_spi_set_cs(rs, 1);
227 + rt2880_spi_set_cs(spi, 1);
232 - m->actual_length += rt2880_spi_write_read(spi, t);
233 + m->actual_length += rt2880_spi_write_read(spi, &m->transfers, t);
236 udelay(t->delay_usecs);
239 - rt2880_spi_set_cs(rs, 0);
240 + rt2880_spi_set_cs(spi, 0);
247 - rt2880_spi_set_cs(rs, 0);
248 + rt2880_spi_set_cs(spi, 0);
251 spi_finalize_current_message(master);
252 @@ -311,7 +378,7 @@ static int rt2880_spi_setup(struct spi_d
253 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
255 if ((spi->max_speed_hz == 0) ||
256 - (spi->max_speed_hz > (rs->sys_freq / 2)))
257 + (spi->max_speed_hz > (rs->sys_freq / 2)))
258 spi->max_speed_hz = (rs->sys_freq / 2);
260 if (spi->max_speed_hz < (rs->sys_freq / 128)) {
261 @@ -328,14 +395,47 @@ static int rt2880_spi_setup(struct spi_d
263 static void rt2880_spi_reset(struct rt2880_spi *rs)
265 - rt2880_spi_write(rs, RAMIPS_SPI_CFG,
266 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(0),
267 SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
268 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
269 - rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
270 + rt2880_spi_write(rs, RAMIPS_SPI_CTL(0), SPICTL_HIZSDO | SPICTL_SPIENA);
273 +static void rt5350_spi_reset(struct rt2880_spi *rs)
277 + rt2880_spi_write(rs, RAMIPS_SPI_ARBITER,
280 + for (cs = 0; cs < rs->ops->num_cs; cs++) {
281 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs),
282 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
283 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
284 + rt2880_spi_write(rs, RAMIPS_SPI_CTL(cs), SPICTL_HIZSDO | SPICTL_SPIENA);
288 +static struct rt2880_spi_ops spi_ops[] = {
290 + .init_hw = rt2880_spi_reset,
293 + .init_hw = rt5350_spi_reset,
298 +static const struct of_device_id rt2880_spi_match[] = {
299 + { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
300 + { .compatible = "ralink,rt5350-spi", .data = &spi_ops[1]},
303 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
305 static int rt2880_spi_probe(struct platform_device *pdev)
307 + const struct of_device_id *match;
308 struct spi_master *master;
309 struct rt2880_spi *rs;
311 @@ -343,6 +443,12 @@ static int rt2880_spi_probe(struct platf
315 + struct rt2880_spi_ops *ops;
317 + match = of_match_device(rt2880_spi_match, &pdev->dev);
320 + ops = (struct rt2880_spi_ops *)match->data;
322 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
323 base = devm_ioremap_resource(&pdev->dev, r);
324 @@ -366,14 +472,13 @@ static int rt2880_spi_probe(struct platf
328 - /* we support only mode 0, and no options */
329 - master->mode_bits = 0;
330 + master->mode_bits = RT2880_SPI_MODE_BITS;
332 master->setup = rt2880_spi_setup;
333 master->transfer_one_message = rt2880_spi_transfer_one_message;
334 - master->num_chipselect = RALINK_NUM_CHIPSELECTS;
335 master->bits_per_word_mask = SPI_BPW_MASK(8);
336 master->dev.of_node = pdev->dev.of_node;
337 + master->num_chipselect = ops->num_cs;
339 dev_set_drvdata(&pdev->dev, master);
341 @@ -382,12 +487,13 @@ static int rt2880_spi_probe(struct platf
344 rs->sys_freq = clk_get_rate(rs->clk);
346 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
347 spin_lock_irqsave(&rs->lock, flags);
349 device_reset(&pdev->dev);
351 - rt2880_spi_reset(rs);
352 + rs->ops->init_hw(rs);
354 return spi_register_master(master);
356 @@ -408,12 +514,6 @@ static int rt2880_spi_remove(struct plat
358 MODULE_ALIAS("platform:" DRIVER_NAME);
360 -static const struct of_device_id rt2880_spi_match[] = {
361 - { .compatible = "ralink,rt2880-spi" },
364 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
366 static struct platform_driver rt2880_spi_driver = {