ar71xx: fold 641-MIPS-ath79-fix-AR934x-OTP-offsets.patch into the patch that it fixes

[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 620-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 777f7b2c8838f2c93f79d5d5212f90b2bd82ced3..64ebf59366e921c3a89bf76ddc2bede9c8c0ebb5 100644 (file)
--- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -274,7 +274,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  static void qca955x_wmac_setup(void)
  {
        u32 t;
-@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -380,6 +400,8 @@ void __init ath79_register_wmac(u8 *cal_
                ar933x_wmac_setup();
        else if (soc_is_ar934x())
                ar934x_wmac_setup();
@@ -446,9 +446,9 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_PCI_MEM_BASE0 0x10000000
  #define QCA955X_PCI_MEM_BASE1 0x12000000
  #define QCA955X_PCI_MEM_SIZE  0x02000000
-@@ -173,6 +188,12 @@
- #define AR934X_DDR_REG_FLUSH_PCIE     0xa8
- #define AR934X_DDR_REG_FLUSH_WMAC     0xac
+@@ -180,6 +195,12 @@
+ #define AR934X_OTP_INTF3_ADDRESS                      0x3100c
+ #define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS      0x31034
  
 +#define QCA953X_DDR_REG_FLUSH_GE0     0x9c
 +#define QCA953X_DDR_REG_FLUSH_GE1     0xa0
@@ -459,7 +459,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  /*
   * PLL block
   */
-@@ -279,6 +300,44 @@
+@@ -286,6 +307,44 @@
  
  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
  
@@ -504,7 +504,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_PLL_CPU_CONFIG_REG            0x00
  #define QCA955X_PLL_DDR_CONFIG_REG            0x04
  #define QCA955X_PLL_CLK_CTRL_REG              0x08
-@@ -355,6 +414,10 @@
+@@ -362,6 +421,10 @@
  #define AR934X_RESET_REG_BOOTSTRAP            0xb0
  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  
@@ -515,7 +515,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_RESET_REG_RESET_MODULE                0x1c
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
-@@ -450,6 +513,27 @@
+@@ -457,6 +520,27 @@
  #define AR934X_RESET_MBOX             BIT(1)
  #define AR934X_RESET_I2S              BIT(0)
  
@@ -543,7 +543,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_RESET_HOST            BIT(31)
  #define QCA955X_RESET_SLIC            BIT(30)
  #define QCA955X_RESET_HDMA            BIT(29)
-@@ -503,6 +587,13 @@
+@@ -510,6 +594,13 @@
  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  #define AR934X_BOOTSTRAP_DDR1         BIT(0)
  
@@ -557,7 +557,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
-@@ -523,6 +614,24 @@
+@@ -530,6 +621,24 @@
         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
         AR934X_PCIE_WMAC_INT_PCIE_RC3)
  
@@ -582,7 +582,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
  #define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
  #define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
-@@ -565,6 +674,8 @@
+@@ -572,6 +681,8 @@
  #define REV_ID_MAJOR_AR9341           0x0120
  #define REV_ID_MAJOR_AR9342           0x1120
  #define REV_ID_MAJOR_AR9344           0x2120
@@ -591,7 +591,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  
-@@ -587,6 +698,8 @@
+@@ -594,6 +705,8 @@
  
  #define AR934X_REV_ID_REVISION_MASK   0xf
  
@@ -600,7 +600,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
-@@ -634,6 +747,25 @@
+@@ -641,6 +754,25 @@
  #define AR934X_GPIO_REG_OUT_FUNC5     0x40
  #define AR934X_GPIO_REG_FUNC          0x6c
  
@@ -626,7 +626,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_GPIO_REG_OUT_FUNC0    0x2c
  #define QCA955X_GPIO_REG_OUT_FUNC1    0x30
  #define QCA955X_GPIO_REG_OUT_FUNC2    0x34
-@@ -648,6 +780,7 @@
+@@ -655,6 +787,7 @@
  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23
@@ -634,7 +634,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_GPIO_COUNT            24
  
  /*
-@@ -671,6 +804,24 @@
+@@ -678,6 +811,24 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
@@ -659,7 +659,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
  #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
  #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
-@@ -877,6 +1028,16 @@
+@@ -884,6 +1035,16 @@
  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
  
  /*