ar71xx: fold 641-MIPS-ath79-fix-AR934x-OTP-offsets.patch into the patch that it fixes
authorFelix Fietkau <nbd@nbd.name>
Tue, 18 Apr 2017 07:59:54 +0000 (09:59 +0200)
committerFelix Fietkau <nbd@nbd.name>
Wed, 26 Apr 2017 08:29:45 +0000 (10:29 +0200)
Signed-off-by: Felix Fietkau <nbd@nbd.name>
15 files changed:
target/linux/ar71xx/patches-4.4/523-MIPS-ath79-OTP-support.patch
target/linux/ar71xx/patches-4.4/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch
target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch
target/linux/ar71xx/patches-4.4/612-MIPS-ath79-set-buffalo-txgain.patch
target/linux/ar71xx/patches-4.4/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch
target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
target/linux/ar71xx/patches-4.4/631-MIPS-ath79-wmac-enable-set-led-pin.patch
target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
target/linux/ar71xx/patches-4.4/641-MIPS-ath79-fix-AR934x-OTP-offsets.patch [deleted file]
target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch

index e030d7c..6778183 100644 (file)
@@ -1,18 +1,30 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -167,6 +167,137 @@ static void qca955x_wmac_setup(void)
+@@ -167,6 +167,149 @@ static void qca955x_wmac_setup(void)
                ath79_wmac_data.is_clk_25mhz = true;
  }
  
++#define AR93XX_WMAC_SIZE \
++      (soc_is_ar934x() ? AR934X_WMAC_SIZE : AR933X_WMAC_SIZE)
++#define AR93XX_WMAC_BASE \
++      (soc_is_ar934x() ? AR934X_WMAC_BASE : AR933X_WMAC_BASE)
++
++#define AR93XX_OTP_BASE \
++      (soc_is_ar934x() ? AR934X_OTP_BASE : AR9300_OTP_BASE)
++#define AR93XX_OTP_STATUS \
++      (soc_is_ar934x() ? AR934X_OTP_STATUS : AR9300_OTP_STATUS)
++#define AR93XX_OTP_READ_DATA \
++      (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
++
 +static bool __init
 +ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
 +{
 +      int timeout = 1000;
 +      u32 val;
 +
-+      __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
++      __raw_readl(base + AR93XX_OTP_BASE + (4 * addr));
 +      while (timeout--) {
-+              val = __raw_readl(base + AR9300_OTP_STATUS);
++              val = __raw_readl(base + AR93XX_OTP_STATUS);
 +              if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
 +                      break;
 +
@@ -22,7 +34,7 @@
 +      if (!timeout)
 +              return false;
 +
-+      *data = __raw_readl(base + AR9300_OTP_READ_DATA);
++      *data = __raw_readl(base + AR93XX_OTP_READ_DATA);
 +      return true;
 +}
 +
 +      int mac_start = 2, mac_end = 8;
 +
 +      BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
-+      base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
++      base = ioremap_nocache(AR93XX_WMAC_BASE, AR93XX_WMAC_SIZE);
 +      while (addr > sizeof(hdr)) {
 +              if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
 +                      break;
  /*
   * DDR_CTRL block
   */
+@@ -149,6 +157,13 @@
+ #define AR934X_DDR_REG_FLUSH_PCIE     0xa8
+ #define AR934X_DDR_REG_FLUSH_WMAC     0xac
++#define AR934X_OTP_BASE                                       0x30000
++#define AR934X_OTP_STATUS                             0x31018
++#define AR934X_OTP_READ_DATA                          0x3101c
++#define AR934X_OTP_INTF2_ADDRESS                      0x31008
++#define AR934X_OTP_INTF3_ADDRESS                      0x3100c
++#define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS      0x31034
++
+ /*
+  * PLL block
+  */
index 31f885f..6f36462 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -298,6 +298,16 @@ bool __init ar93xx_wmac_read_mac_address
+@@ -310,6 +310,16 @@ bool __init ar93xx_wmac_read_mac_address
        return ret;
  }
  
index 0e33674..61b6b4e 100644 (file)
@@ -29,7 +29,9 @@
 -      u32 bootstrap;
 +      void __iomem *phy_reg;
 +      u32 t;
-+
+-      bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+-      if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
 +      phy_reg = ioremap(base, 4);
 +      if (!phy_reg)
 +              return;
@@ -41,9 +43,7 @@
 +
 +      iounmap(phy_reg);
 +}
--      bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
--      if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
++
 +static void ar934x_usb_reset_notifier(struct platform_device *pdev)
 +{
 +      if (pdev->id != -1)
index 0126f6a..03ca106 100644 (file)
@@ -58,7 +58,7 @@
  
  #define AR9300_OTP_BASE               0x14000
  #define AR9300_OTP_STATUS     0x15f18
-@@ -174,6 +190,9 @@
+@@ -181,6 +197,9 @@
  #define AR71XX_AHB_DIV_SHIFT          20
  #define AR71XX_AHB_DIV_MASK           0x7
  
@@ -68,7 +68,7 @@
  #define AR724X_PLL_REG_CPU_CONFIG     0x00
  #define AR724X_PLL_REG_PCIE_CONFIG    0x18
  
-@@ -186,6 +205,8 @@
+@@ -193,6 +212,8 @@
  #define AR724X_DDR_DIV_SHIFT          22
  #define AR724X_DDR_DIV_MASK           0x3
  
@@ -77,7 +77,7 @@
  #define AR913X_PLL_REG_CPU_CONFIG     0x00
  #define AR913X_PLL_REG_ETH_CONFIG     0x04
  #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -198,6 +219,9 @@
+@@ -205,6 +226,9 @@
  #define AR913X_AHB_DIV_SHIFT          19
  #define AR913X_AHB_DIV_MASK           0x1
  
@@ -87,7 +87,7 @@
  #define AR933X_PLL_CPU_CONFIG_REG     0x00
  #define AR933X_PLL_CLOCK_CTRL_REG     0x08
  
-@@ -219,6 +243,8 @@
+@@ -226,6 +250,8 @@
  #define AR934X_PLL_CPU_CONFIG_REG             0x00
  #define AR934X_PLL_DDR_CONFIG_REG             0x04
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG               0x08
@@ -96,7 +96,7 @@
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
-@@ -251,9 +277,13 @@
+@@ -258,9 +284,13 @@
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
  
  
  #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
  #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
-@@ -378,16 +408,83 @@
+@@ -385,16 +415,83 @@
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
 +#define AR934X_RESET_LUT              BIT(2)
 +#define AR934X_RESET_MBOX             BIT(1)
 +#define AR934X_RESET_I2S              BIT(0)
-+
 +#define QCA955X_RESET_HOST            BIT(31)
 +#define QCA955X_RESET_SLIC            BIT(30)
 +#define QCA955X_RESET_HDMA            BIT(29)
 +#define QCA955X_RESET_LUT             BIT(2)
 +#define QCA955X_RESET_MBOX            BIT(1)
 +#define QCA955X_RESET_I2S             BIT(0)
++
 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
 +#define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -529,8 +626,22 @@
+@@ -536,8 +633,22 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
  #define AR71XX_GPIO_COUNT             16
  #define AR7240_GPIO_COUNT             18
  #define AR7241_GPIO_COUNT             20
-@@ -560,4 +671,235 @@
+@@ -567,4 +678,235 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
index 4d7902e..5d9d802 100644 (file)
 +static void __init ap136_common_setup(void)
 +{
 +      u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-+
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 +      ath79_register_m25p80(NULL);
 +
 +      ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
 +      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
 +
 +      ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
--static int ap136_pci_plat_dev_init(struct pci_dev *dev)
++
 +      ath79_register_mdio(0, 0x0);
 +      ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
 +
 +      /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
 +      ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
 +      ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
-+
+-      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+-      ath79_register_pci();
 +      /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
 +      ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
 +      ap136_ar8327_pad6_cfg.txclk_delay_en = true;
 +      ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
 +      ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
 +      ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
--      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
--      ath79_register_pci();
++
 +      ath79_eth0_pll_data.pll_1000 = 0x56000000;
 +      ath79_eth1_pll_data.pll_1000 = 0x03000101;
 +
index 4e3ac70..41775f0 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -308,6 +308,11 @@ void __init ath79_wmac_disable_5ghz(void
+@@ -320,6 +320,11 @@ void __init ath79_wmac_disable_5ghz(void
        ath79_wmac_data.disable_5ghz = true;
  }
  
index e8bbe44..3d422bb 100644 (file)
@@ -12,7 +12,7 @@
  #include "dev-wmac.h"
  
  static u8 ath79_wmac_mac[ETH_ALEN];
-@@ -313,6 +315,51 @@ void __init ath79_wmac_set_tx_gain_buffa
+@@ -325,6 +327,51 @@ void __init ath79_wmac_set_tx_gain_buffa
        ath79_wmac_data.tx_gain_buffalo = true;
  }
  
index 777f7b2..64ebf59 100644 (file)
@@ -274,7 +274,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  static void qca955x_wmac_setup(void)
  {
        u32 t;
-@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -380,6 +400,8 @@ void __init ath79_register_wmac(u8 *cal_
                ar933x_wmac_setup();
        else if (soc_is_ar934x())
                ar934x_wmac_setup();
@@ -446,9 +446,9 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_PCI_MEM_BASE0 0x10000000
  #define QCA955X_PCI_MEM_BASE1 0x12000000
  #define QCA955X_PCI_MEM_SIZE  0x02000000
-@@ -173,6 +188,12 @@
- #define AR934X_DDR_REG_FLUSH_PCIE     0xa8
- #define AR934X_DDR_REG_FLUSH_WMAC     0xac
+@@ -180,6 +195,12 @@
+ #define AR934X_OTP_INTF3_ADDRESS                      0x3100c
+ #define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS      0x31034
  
 +#define QCA953X_DDR_REG_FLUSH_GE0     0x9c
 +#define QCA953X_DDR_REG_FLUSH_GE1     0xa0
@@ -459,7 +459,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  /*
   * PLL block
   */
-@@ -279,6 +300,44 @@
+@@ -286,6 +307,44 @@
  
  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
  
@@ -504,7 +504,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_PLL_CPU_CONFIG_REG            0x00
  #define QCA955X_PLL_DDR_CONFIG_REG            0x04
  #define QCA955X_PLL_CLK_CTRL_REG              0x08
-@@ -355,6 +414,10 @@
+@@ -362,6 +421,10 @@
  #define AR934X_RESET_REG_BOOTSTRAP            0xb0
  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  
@@ -515,7 +515,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_RESET_REG_RESET_MODULE                0x1c
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
-@@ -450,6 +513,27 @@
+@@ -457,6 +520,27 @@
  #define AR934X_RESET_MBOX             BIT(1)
  #define AR934X_RESET_I2S              BIT(0)
  
@@ -543,7 +543,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_RESET_HOST            BIT(31)
  #define QCA955X_RESET_SLIC            BIT(30)
  #define QCA955X_RESET_HDMA            BIT(29)
-@@ -503,6 +587,13 @@
+@@ -510,6 +594,13 @@
  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  #define AR934X_BOOTSTRAP_DDR1         BIT(0)
  
@@ -557,7 +557,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
-@@ -523,6 +614,24 @@
+@@ -530,6 +621,24 @@
         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
         AR934X_PCIE_WMAC_INT_PCIE_RC3)
  
@@ -582,7 +582,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
  #define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
  #define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
-@@ -565,6 +674,8 @@
+@@ -572,6 +681,8 @@
  #define REV_ID_MAJOR_AR9341           0x0120
  #define REV_ID_MAJOR_AR9342           0x1120
  #define REV_ID_MAJOR_AR9344           0x2120
@@ -591,7 +591,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  
-@@ -587,6 +698,8 @@
+@@ -594,6 +705,8 @@
  
  #define AR934X_REV_ID_REVISION_MASK   0xf
  
@@ -600,7 +600,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
-@@ -634,6 +747,25 @@
+@@ -641,6 +754,25 @@
  #define AR934X_GPIO_REG_OUT_FUNC5     0x40
  #define AR934X_GPIO_REG_FUNC          0x6c
  
@@ -626,7 +626,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_GPIO_REG_OUT_FUNC0    0x2c
  #define QCA955X_GPIO_REG_OUT_FUNC1    0x30
  #define QCA955X_GPIO_REG_OUT_FUNC2    0x34
-@@ -648,6 +780,7 @@
+@@ -655,6 +787,7 @@
  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23
@@ -634,7 +634,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_GPIO_COUNT            24
  
  /*
-@@ -671,6 +804,24 @@
+@@ -678,6 +811,24 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
@@ -659,7 +659,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
  #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
  #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
-@@ -877,6 +1028,16 @@
+@@ -884,6 +1035,16 @@
  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
  
  /*
index ed90c40..d8bb248 100644 (file)
  }
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -189,6 +189,26 @@ static void qca955x_wmac_setup(void)
-               ath79_wmac_data.is_clk_25mhz = true;
- }
+@@ -201,6 +201,26 @@ static void qca955x_wmac_setup(void)
+ #define AR93XX_OTP_READ_DATA \
+       (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
  
 +static void qca956x_wmac_setup(void)
 +{
  static bool __init
  ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
  {
-@@ -392,6 +412,8 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -404,6 +424,8 @@ void __init ath79_register_wmac(u8 *cal_
                qca953x_wmac_setup();
        else if (soc_is_qca955x())
                qca955x_wmac_setup();
   * DDR_CTRL block
   */
  #define AR71XX_DDR_REG_PCI_WIN0               0x7c
-@@ -375,6 +399,49 @@
+@@ -382,6 +406,49 @@
  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
  
  /*
   * USB_CONFIG block
   */
-@@ -422,6 +489,11 @@
+@@ -429,6 +496,11 @@
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
  
  #define MISC_INT_ETHSW                        BIT(12)
  #define MISC_INT_TIMER4                       BIT(10)
  #define MISC_INT_TIMER3                       BIT(9)
-@@ -596,6 +668,8 @@
+@@ -603,6 +675,8 @@
  
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
  #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
-@@ -663,6 +737,37 @@
+@@ -670,6 +744,37 @@
         QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
         QCA955X_EXT_INT_PCIE_RC2_INT3)
  
  #define REV_ID_MAJOR_MASK             0xfff0
  #define REV_ID_MAJOR_AR71XX           0x00a0
  #define REV_ID_MAJOR_AR913X           0x00b0
-@@ -678,6 +783,8 @@
+@@ -685,6 +790,8 @@
  #define REV_ID_MAJOR_QCA9533_V2               0x0160
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  
  #define AR71XX_REV_ID_MINOR_MASK      0x3
  #define AR71XX_REV_ID_MINOR_AR7130    0x0
-@@ -702,6 +809,8 @@
+@@ -709,6 +816,8 @@
  
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
   * SPI block
   */
-@@ -774,6 +883,19 @@
+@@ -781,6 +890,19 @@
  #define QCA955X_GPIO_REG_OUT_FUNC5    0x40
  #define QCA955X_GPIO_REG_FUNC         0x6c
  
  #define AR71XX_GPIO_COUNT             16
  #define AR7240_GPIO_COUNT             18
  #define AR7241_GPIO_COUNT             20
-@@ -782,6 +904,7 @@
+@@ -789,6 +911,7 @@
  #define AR934X_GPIO_COUNT             23
  #define QCA953X_GPIO_COUNT            18
  #define QCA955X_GPIO_COUNT            24
index dff3543..6573b29 100644 (file)
@@ -11,7 +11,7 @@
  #define QCA956X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
  #define QCA956X_GMAC_SIZE     0x64
  
-@@ -404,6 +408,7 @@
+@@ -411,6 +415,7 @@
  #define QCA956X_PLL_DDR_CONFIG_REG                    0x08
  #define QCA956X_PLL_DDR_CONFIG1_REG                   0x0c
  #define QCA956X_PLL_CLK_CTRL_REG                      0x10
@@ -19,7 +19,7 @@
  
  #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT           12
  #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK            0x1f
-@@ -1186,4 +1191,16 @@
+@@ -1193,4 +1198,16 @@
  #define QCA955X_ETH_CFG_TXE_DELAY_MASK        0x3
  #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT       20
  
index 16a0b90..0af1488 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -400,6 +400,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
+@@ -412,6 +412,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
                ar934x_set_ext_lna_gpio(chain, gpio);
  }
  
index 8aa5957..8ddb81c 100644 (file)
@@ -20,7 +20,7 @@
  #define AR71XX_UART_BASE      (AR71XX_APB_BASE + 0x00020000)
  #define AR71XX_UART_SIZE      0x100
  #define AR71XX_USB_CTRL_BASE  (AR71XX_APB_BASE + 0x00030000)
-@@ -222,6 +222,9 @@
+@@ -229,6 +229,9 @@
  #define QCA953X_DDR_REG_FLUSH_PCIE    0xa8
  #define QCA953X_DDR_REG_FLUSH_WMAC    0xac
  
@@ -68,7 +68,7 @@
 +      ath79_wmac_data.external_reset = ar955x_wmac_reset;
  }
  
- static void qca956x_wmac_setup(void)
+ #define AR93XX_WMAC_SIZE \
 --- a/arch/mips/ath79/common.h
 +++ b/arch/mips/ath79/common.h
 @@ -19,6 +19,8 @@
diff --git a/target/linux/ar71xx/patches-4.4/641-MIPS-ath79-fix-AR934x-OTP-offsets.patch b/target/linux/ar71xx/patches-4.4/641-MIPS-ath79-fix-AR934x-OTP-offsets.patch
deleted file mode 100644 (file)
index 78ecf89..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
---- a/arch/mips/ath79/dev-wmac.c       2017-02-12 19:49:21.158142253 +0100
-+++ b/arch/mips/ath79/dev-wmac.c       2017-02-12 21:01:51.206198122 +0100
-@@ -232,15 +274,27 @@ static void qca956x_wmac_setup(void)
-       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
- }
-
-+#define AR93XX_WMAC_SIZE \
-+      (soc_is_ar934x() ? AR934X_WMAC_SIZE : AR933X_WMAC_SIZE)
-+#define AR93XX_WMAC_BASE \
-+      (soc_is_ar934x() ? AR934X_WMAC_BASE : AR933X_WMAC_BASE)
-+
-+#define AR93XX_OTP_BASE \
-+      (soc_is_ar934x() ? AR934X_OTP_BASE : AR9300_OTP_BASE)
-+#define AR93XX_OTP_STATUS \
-+      (soc_is_ar934x() ? AR934X_OTP_STATUS : AR9300_OTP_STATUS)
-+#define AR93XX_OTP_READ_DATA \
-+      (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
-+
- static bool __init
- ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
- {
-       int timeout = 1000;
-       u32 val;
-
--      __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
-+      __raw_readl(base + AR93XX_OTP_BASE + (4 * addr));
-       while (timeout--) {
--              val = __raw_readl(base + AR9300_OTP_STATUS);
-+              val = __raw_readl(base + AR93XX_OTP_STATUS);
-               if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
-                       break;
-
-@@ -250,7 +304,7 @@ ar93xx_wmac_otp_read_word(void __iomem *
-       if (!timeout)
-               return false;
-
--      *data = __raw_readl(base + AR9300_OTP_READ_DATA);
-+      *data = __raw_readl(base + AR93XX_OTP_READ_DATA);
-       return true;
- }
-
-@@ -326,7 +380,7 @@ bool __init ar93xx_wmac_read_mac_address
-       int mac_start = 2, mac_end = 8;
-
-       BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
--      base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
-+      base = ioremap_nocache(AR93XX_WMAC_BASE, AR93XX_WMAC_SIZE);
-       while (addr > sizeof(hdr)) {
-               if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
-                       break;
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2017-02-12 20:22:32.185209249 +0100
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2017-02-12 20:42:21.037382287 +0100
-@@ -172,6 +172,13 @@
- #define AR9300_OTP_STATUS_SM_BUSY     0x1
- #define AR9300_OTP_READ_DATA  0x15f1c
-
-+#define AR934X_OTP_BASE                                       0x30000
-+#define AR934X_OTP_STATUS                             0x31018
-+#define AR934X_OTP_READ_DATA                          0x3101c
-+#define AR934X_OTP_INTF2_ADDRESS                      0x31008
-+#define AR934X_OTP_INTF3_ADDRESS                      0x3100c
-+#define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS      0x31034
-+
- /*
-  * Hidden Registers
-  */
index 6b33158..4d72a6c 100644 (file)
@@ -48,7 +48,7 @@ functions on the Arduino Yun.
        void __iomem *reg = ath79_gpio_get_function_reg();
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -855,6 +855,7 @@
+@@ -862,6 +862,7 @@
  #define AR71XX_GPIO_REG_INT_PENDING   0x20
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
@@ -56,7 +56,7 @@ functions on the Arduino Yun.
  
  #define AR934X_GPIO_REG_OUT_FUNC0     0x2c
  #define AR934X_GPIO_REG_OUT_FUNC1     0x30
-@@ -979,6 +980,8 @@
+@@ -986,6 +987,8 @@
  #define AR724X_GPIO_FUNC_UART_EN              BIT(1)
  #define AR724X_GPIO_FUNC_JTAG_DISABLE         BIT(0)
  
index 26aab8e..1aa4120 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -649,6 +649,7 @@
+@@ -656,6 +656,7 @@
  
  #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
  #define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
@@ -8,7 +8,7 @@
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -678,6 +679,8 @@
+@@ -685,6 +686,8 @@
  
  #define QCA956X_BOOTSTRAP_REF_CLK_40  BIT(2)