uboot-rockchip: bump to 2026.01 main master
authorStijn Tintel <stijn@linux-ipv6.be>
Mon, 12 Jan 2026 15:26:05 +0000 (17:26 +0200)
committerStijn Tintel <stijn@linux-ipv6.be>
Thu, 15 Jan 2026 14:33:26 +0000 (16:33 +0200)
Drop upstreamed patches, refresh others.

Tested on Radxa ROCK 5B+.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
12 files changed:
package/boot/uboot-rockchip/Makefile
package/boot/uboot-rockchip/patches/001-spi-rockchip_sfc-Support-sclk_x2-version.patch [deleted file]
package/boot/uboot-rockchip/patches/002-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch [deleted file]
package/boot/uboot-rockchip/patches/003-rockchip-rk3528-Implement-read_brom_bootsource_id.patch [deleted file]
package/boot/uboot-rockchip/patches/004-rockchip-rk3576-Add-SPI-Flash-boot-support.patch [deleted file]
package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-4D.patch [deleted file]
package/boot/uboot-rockchip/patches/006-arm64-dts-rockchip-Add-Radxa-ROCK-2A-2F.patch [deleted file]
package/boot/uboot-rockchip/patches/007-board-rockchip-Add-Radxa-ROCK-2A-2F.patch [deleted file]
package/boot/uboot-rockchip/patches/008-board-rockchip-add-Lunzn-FastRhino-R66S.patch [deleted file]
package/boot/uboot-rockchip/patches/009-mmc-rockchip_sdhci-Set-xx_TAP_VALUE-for-RK3528.patch [deleted file]
package/boot/uboot-rockchip/patches/102-rockchip-Add-initial-RK3582-support.patch
package/boot/uboot-rockchip/patches/103-rockchip-rk3588-generic-Enable-support-for-RK3582.patch

index b2886703fc61774f36e532c6078ac5cb08b4dc75..9d098125246af3a179cbbd37436256f7a5cef895 100644 (file)
@@ -5,9 +5,9 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2025.10
+PKG_VERSION:=2026.01
 PKG_RELEASE:=1
 PKG_RELEASE:=1
-PKG_HASH:=b4f032848e56cc8f213ad59f9132c084dbbb632bc29176d024e58220e0efdf4a
+PKG_HASH:=b60d5865cefdbc75da8da4156c56c458e00de75a49b80c1a2e58a96e30ad0d54
 
 PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de>
 
 
 PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de>
 
diff --git a/package/boot/uboot-rockchip/patches/001-spi-rockchip_sfc-Support-sclk_x2-version.patch b/package/boot/uboot-rockchip/patches/001-spi-rockchip_sfc-Support-sclk_x2-version.patch
deleted file mode 100644 (file)
index 26ac1ff..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-From 193563a005edc4e54426458ee6e097c8e4b38874 Mon Sep 17 00:00:00 2001
-From: Jon Lin <jon.lin@rock-chips.com>
-Date: Sun, 19 Oct 2025 15:47:15 +0000
-Subject: [PATCH] spi: rockchip_sfc: Support sclk_x2 version
-
-SFC after version 8 supports dtr mode, so the IO is the binary output of
-the controller clock.
-
-Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
---- a/drivers/spi/rockchip_sfc.c
-+++ b/drivers/spi/rockchip_sfc.c
-@@ -108,6 +108,7 @@
- #define  SFC_VER_3                    0x3
- #define  SFC_VER_4                    0x4
- #define  SFC_VER_5                    0x5
-+#define  SFC_VER_8                    0x8
- /* Delay line controller resiter */
- #define SFC_DLL_CTRL0                 0x3C
-@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(s
-       return 0;
- }
-+#if CONFIG_IS_ENABLED(CLK)
-+static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
-+{
-+      if (sfc->version >= SFC_VER_8)
-+              return clk_set_rate(&sfc->clk, speed * 2);
-+      else
-+              return clk_set_rate(&sfc->clk, speed);
-+}
-+#endif
-+
- static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
- {
-       struct rockchip_sfc *sfc = dev_get_plat(bus);
-@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct
-               return 0;
- #if CONFIG_IS_ENABLED(CLK)
--      int ret = clk_set_rate(&sfc->clk, speed);
-+      int ret = rockchip_sfc_clk_set_rate(sfc, speed);
-       if (ret < 0) {
-               dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
diff --git a/package/boot/uboot-rockchip/patches/002-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch b/package/boot/uboot-rockchip/patches/002-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch
deleted file mode 100644 (file)
index 2081105..0000000
+++ /dev/null
@@ -1,56 +0,0 @@
-From 20c950de5e0431464b7068fdb2c6ec4ead3940ad Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 19 Oct 2025 15:47:16 +0000
-Subject: [PATCH] rockchip: spl: Add a read_brom_bootsource_id() helper
-
-The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
-SPI NOR and USB differs slightly compared to prior SoCs:
-
-- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
-- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
-- Booting from sfc1 M0 has not been tested (no board using this config).
-- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
-
-Add a helper function to read the bootsource id. This helper function
-will be used to translate the new values to the common BROM_BOOTSOURCE
-enum values on RK3528 and RK3576.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
- arch/arm/mach-rockchip/spl.c                 | 7 ++++++-
- 2 files changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/include/asm/arch-rockchip/bootrom.h
-+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
-@@ -64,4 +64,6 @@ extern const char * const boot_devices[B
-  */
- #define BROM_BOOTSOURCE_ID_ADDR   (CFG_IRAM_BASE + 0x10)
-+u32 read_brom_bootsource_id(void);
-+
- #endif
---- a/arch/arm/mach-rockchip/spl.c
-+++ b/arch/arm/mach-rockchip/spl.c
-@@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_i
- __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- };
-+__weak u32 read_brom_bootsource_id(void)
-+{
-+      return readl(BROM_BOOTSOURCE_ID_ADDR);
-+}
-+
- const char *board_spl_was_booted_from(void)
- {
-       static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN;
-@@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(vo
-       if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN)
-               bootdevice_brom_id = brom_bootsource_id_cache;
-       else
--              bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
-+              bootdevice_brom_id = read_brom_bootsource_id();
-       if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
-               bootdevice_ofpath = boot_devices[bootdevice_brom_id];
diff --git a/package/boot/uboot-rockchip/patches/003-rockchip-rk3528-Implement-read_brom_bootsource_id.patch b/package/boot/uboot-rockchip/patches/003-rockchip-rk3528-Implement-read_brom_bootsource_id.patch
deleted file mode 100644 (file)
index ab2775d..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-From deee6a1cf623a81cb6de9ebe84cc6d1a393881f8 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 19 Oct 2025 15:47:17 +0000
-Subject: [PATCH] rockchip: rk3528: Implement read_brom_bootsource_id()
-
-The bootsource ids reported by BootROM of RK3528 for e.g. USB differs
-compared to prior SoCs:
-
-- Booting from USB report a new bootsource id 0x81.
-
-Add a RK3528 specific read_brom_bootsource_id() function to help decode
-this new bootsource id value to help support booting from USB on RK3528.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/mach-rockchip/rk3528/rk3528.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm/mach-rockchip/rk3528/rk3528.c
-+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
-@@ -49,6 +49,21 @@ void board_debug_uart_init(void)
- {
- }
-+u32 read_brom_bootsource_id(void)
-+{
-+      u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
-+
-+      /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE
-+       * enum value to avoid having to create a larger boot_devices table.
-+       */
-+      if (bootsource_id == 0x81)
-+              return BROM_BOOTSOURCE_USB;
-+      else if (bootsource_id > BROM_LAST_BOOTSOURCE)
-+              log_debug("Unknown bootsource %x\n", bootsource_id);
-+
-+      return bootsource_id;
-+}
-+
- int arch_cpu_init(void)
- {
-       u32 val;
diff --git a/package/boot/uboot-rockchip/patches/004-rockchip-rk3576-Add-SPI-Flash-boot-support.patch b/package/boot/uboot-rockchip/patches/004-rockchip-rk3576-Add-SPI-Flash-boot-support.patch
deleted file mode 100644 (file)
index 2dee70e..0000000
+++ /dev/null
@@ -1,143 +0,0 @@
-From 06d52d81cbd4275c86a7a150a23ab4d1dee8f435 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 19 Oct 2025 15:47:18 +0000
-Subject: [PATCH] rockchip: rk3576: Add SPI Flash boot support
-
-The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
-differs slightly compared to prior SoCs:
-
-- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
-- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
-- Booting from sfc1 M0 has not been tested (no board using this config).
-- Booting from USB report a new bootsource id 0x81.
-
-Add a RK3576 specific read_brom_bootsource_id() function to help decode
-the new bootsource id values and the required boot_devices mapping of
-sfc0 and sfc1 to help support booting from SPI flash on RK3576.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/rk3576-u-boot.dtsi        | 46 ++++++++++++++++++++++++++
- arch/arm/mach-rockchip/rk3576/rk3576.c | 25 ++++++++++++++
- 2 files changed, 71 insertions(+)
-
---- a/arch/arm/dts/rk3576-u-boot.dtsi
-+++ b/arch/arm/dts/rk3576-u-boot.dtsi
-@@ -6,6 +6,11 @@
- #include "rockchip-u-boot.dtsi"
- / {
-+      aliases {
-+              spi5 = &sfc0;
-+              spi6 = &sfc1;
-+      };
-+
-       chosen {
-               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
-       };
-@@ -16,6 +21,17 @@
-       };
- };
-+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
-+&binman {
-+      simple-bin-spi {
-+              mkimage {
-+                      args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
-+                      offset = <0x8000>;
-+              };
-+      };
-+};
-+#endif
-+
- &cru {
-       bootph-all;
- };
-@@ -45,6 +61,26 @@
-       bootph-some-ram;
- };
-+&fspi0_csn0 {
-+      bootph-pre-ram;
-+      bootph-some-ram;
-+};
-+
-+&fspi0_pins {
-+      bootph-pre-ram;
-+      bootph-some-ram;
-+};
-+
-+&fspi1m1_csn0 {
-+      bootph-pre-ram;
-+      bootph-some-ram;
-+};
-+
-+&fspi1m1_pins {
-+      bootph-pre-ram;
-+      bootph-some-ram;
-+};
-+
- &ioc_grf {
-       bootph-all;
- };
-@@ -116,6 +152,16 @@
-       bootph-some-ram;
- };
-+&sfc0 {
-+      bootph-some-ram;
-+      u-boot,spl-sfc-no-dma;
-+};
-+
-+&sfc1 {
-+      bootph-some-ram;
-+      u-boot,spl-sfc-no-dma;
-+};
-+
- &sys_grf {
-       bootph-all;
- };
---- a/arch/arm/mach-rockchip/rk3576/rk3576.c
-+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
-@@ -36,8 +36,15 @@
- #define USB_GRF_BASE          0x2601E000
- #define USB3OTG0_CON1         0x0030
-+enum {
-+      BROM_BOOTSOURCE_FSPI0 = 3,
-+      BROM_BOOTSOURCE_FSPI1_M1 = 6,
-+};
-+
- const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
-       [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
-+      [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0",
-+      [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0",
-       [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
- };
-@@ -85,6 +92,24 @@ void board_debug_uart_init(void)
- {
- }
-+u32 read_brom_bootsource_id(void)
-+{
-+      u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
-+
-+      /* Re-map the raw value read from reg to a redefined or existing
-+       * BROM_BOOTSOURCE enum value to avoid having to create a larger
-+       * boot_devices table.
-+       */
-+      if (bootsource_id == 0x23)
-+              return BROM_BOOTSOURCE_FSPI1_M1;
-+      else if (bootsource_id == 0x81)
-+              return BROM_BOOTSOURCE_USB;
-+      else if (bootsource_id > BROM_LAST_BOOTSOURCE)
-+              log_debug("Unknown bootsource %x\n", bootsource_id);
-+
-+      return bootsource_id;
-+}
-+
- #define HP_TIMER_BASE                 CONFIG_ROCKCHIP_STIMER_BASE
- #define HP_CTRL_REG                   0x04
- #define TIMER_EN                      BIT(0)
diff --git a/package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-4D.patch b/package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-4D.patch
deleted file mode 100644 (file)
index 2e234c0..0000000
+++ /dev/null
@@ -1,299 +0,0 @@
-From 06cc02fe00d5a6d9ef51aa8852b891c0a5e3cf3e Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 19 Oct 2025 15:47:19 +0000
-Subject: [PATCH] board: rockchip: Add Radxa ROCK 4D
-
-The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
-numerous top-tier functions, features, and expansion options.
-
-Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
-octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
-powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
-
-Features tested on a Radxa ROCK 4D v1.112:
-- SPI Flash boot
-- Ethernet
-- PCIe/NVMe
-- USB host
-
-ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
-or directly from USB when the MASKROM button is pressed, booting
-directly from SD-card is not possible on these boards.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/rk3576-rock-4d-u-boot.dtsi   | 10 ++++
- arch/arm/mach-rockchip/rk3576/MAINTAINERS |  6 ++
- configs/rock-4d-rk3576_defconfig          | 68 +++++++++++++++++++++++
- doc/board/rockchip/rockchip.rst           |  1 +
- 4 files changed, 85 insertions(+)
- create mode 100644 arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
- create mode 100644 configs/rock-4d-rk3576_defconfig
-
---- a/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts
-+++ b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts
-@@ -57,13 +57,13 @@
-               };
-       };
--      vcc_12v0_dcin: regulator-vcc-12v0-dcin {
-+      vcc_5v0_dcin: regulator-vcc-5v0-dcin {
-               compatible = "regulator-fixed";
-               regulator-always-on;
-               regulator-boot-on;
--              regulator-min-microvolt = <12000000>;
--              regulator-max-microvolt = <12000000>;
--              regulator-name = "vcc_12v0_dcin";
-+              regulator-min-microvolt = <5000000>;
-+              regulator-max-microvolt = <5000000>;
-+              regulator-name = "vcc_5v0_dcin";
-       };
-       vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
-@@ -166,7 +166,7 @@
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               regulator-name = "vcc_5v0_device";
--              vin-supply = <&vcc_12v0_dcin>;
-+              vin-supply = <&vcc_5v0_sys>;
-       };
-       vcc_5v0_host: regulator-vcc-5v0-host {
-@@ -180,7 +180,21 @@
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               regulator-name = "vcc5v0_host";
--              vin-supply = <&vcc_5v0_device>;
-+              vin-supply = <&vcc_5v0_sys>;
-+      };
-+
-+      vcc_5v0_otg: regulator-vcc-5v0-otg {
-+              compatible = "regulator-fixed";
-+              enable-active-high;
-+              gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&usb_otg_pwren>;
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <5000000>;
-+              regulator-max-microvolt = <5000000>;
-+              regulator-name = "vcc5v0_otg";
-+              vin-supply = <&vcc_5v0_sys>;
-       };
-       vcc_5v0_sys: regulator-vcc-5v0-sys {
-@@ -190,10 +204,14 @@
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               regulator-name = "vcc_5v0_sys";
--              vin-supply = <&vcc_12v0_dcin>;
-+              vin-supply = <&vcc_5v0_dcin>;
-       };
- };
-+&combphy0_ps {
-+      status = "okay";
-+};
-+
- &combphy1_psu {
-       status = "okay";
- };
-@@ -641,17 +659,27 @@
- &mdio0 {
-       rgmii_phy0: ethernet-phy@1 {
--              compatible = "ethernet-phy-ieee802.3-c22";
-+              compatible = "ethernet-phy-id001c.c916";
-               reg = <0x1>;
-               clocks = <&cru REFCLKO25M_GMAC0_OUT>;
-+              assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>;
-+              assigned-clock-rates = <25000000>;
-               pinctrl-names = "default";
-               pinctrl-0 = <&rtl8211f_rst>;
-               reset-assert-us = <20000>;
-               reset-deassert-us = <100000>;
--              reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
-+              reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
-       };
- };
-+&pcie0 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&pcie_reset>;
-+      reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
-+      vpcie3v3-supply = <&vcc_3v3_pcie>;
-+      status = "okay";
-+};
-+
- &pinctrl {
-       hym8563 {
-               hym8563_int: hym8563-int {
-@@ -678,11 +706,18 @@
-               pcie_pwren: pcie-pwren {
-                       rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-               };
-+              pcie_reset: pcie-reset {
-+                      rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-       };
-       usb {
-               usb_host_pwren: usb-host-pwren {
--                      rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-+                      rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
-+              };
-+              usb_otg_pwren: usb-otg-pwren {
-+                      rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
-+
-               };
-       };
- };
-@@ -721,15 +756,38 @@
-       status = "okay";
- };
-+&u2phy0_otg {
-+      phy-supply = <&vcc_5v0_otg>;
-+      status = "okay";
-+};
-+
- &u2phy1 {
-       status = "okay";
- };
-+&u2phy1_otg {
-+      phy-supply = <&vcc_5v0_host>;
-+      status = "okay";
-+};
-+
- &uart0 {
-       pinctrl-0 = <&uart0m0_xfer>;
-       status = "okay";
- };
-+&ufshc {
-+      status = "okay";
-+};
-+
-+&usbdp_phy {
-+      status = "okay";
-+};
-+
-+&usb_drd0_dwc3 {
-+      dr_mode = "host";
-+      status = "okay";
-+};
-+
- &usb_drd1_dwc3 {
-       dr_mode = "host";
-       status = "okay";
---- /dev/null
-+++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3576-u-boot.dtsi"
-+
-+&sfc0 {
-+      flash@0 {
-+              bootph-pre-ram;
-+              bootph-some-ram;
-+      };
-+};
---- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-@@ -4,6 +4,12 @@ S:    Maintained
- F:    arch/arm/dts/rk3576-generic*
- F:    configs/generic-rk3576_defconfig
-+ROCK-4D-RK3576
-+M:    Jonas Karlman <jonas@kwiboo.se>
-+S:    Maintained
-+F:    arch/arm/dts/rk3576-rock-4d*
-+F:    configs/rock-4d-rk3576_defconfig
-+
- SIGE5-RK3576
- M:    Jonas Karlman <jonas@kwiboo.se>
- S:    Maintained
---- /dev/null
-+++ b/configs/rock-4d-rk3576_defconfig
-@@ -0,0 +1,68 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=50000000
-+CONFIG_SF_DEFAULT_MODE=0x2000
-+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d"
-+CONFIG_ROCKCHIP_RK3576=y
-+CONFIG_ROCKCHIP_SPI_IMAGE=y
-+CONFIG_SYS_LOAD_ADDR=0x40c00800
-+CONFIG_SF_DEFAULT_BUS=5
-+CONFIG_DEBUG_UART_BASE=0x2AD40000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-+CONFIG_SPL_SPI=y
-+CONFIG_PCI=y
-+CONFIG_DEBUG_UART=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_SPI_LOAD=y
-+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
-+CONFIG_CMD_MEMINFO=y
-+CONFIG_CMD_MEMINFO_MAP=y
-+CONFIG_CMD_ADC=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_I2C=y
-+CONFIG_CMD_MISC=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_RNG=y
-+CONFIG_CMD_REGULATOR=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_LED=y
-+CONFIG_LED_GPIO=y
-+CONFIG_SUPPORT_EMMC_RPMB=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-+CONFIG_SPI_FLASH_MACRONIX=y
-+CONFIG_PHY_REALTEK=y
-+CONFIG_DWC_ETH_QOS=y
-+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
-+CONFIG_NVME_PCI=y
-+CONFIG_PCIE_DW_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-+CONFIG_PHY_ROCKCHIP_USBDP=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_ROCKCHIP_SFC=y
-+CONFIG_SYSRESET_PSCI=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_ERRNO_STR=y
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -137,6 +137,7 @@ List of mainline supported Rockchip boar
-      - ArmSoM Sige5 (sige5-rk3576)
-      - Firefly ROC-RK3576-PC (roc-pc-rk3576)
-      - Generic RK3576 (generic-rk3576)
-+     - Radxa ROCK 4D (rock-4d-rk3576)
- * rk3588
-      - ArmSoM Sige7 (sige7-rk3588)
diff --git a/package/boot/uboot-rockchip/patches/006-arm64-dts-rockchip-Add-Radxa-ROCK-2A-2F.patch b/package/boot/uboot-rockchip/patches/006-arm64-dts-rockchip-Add-Radxa-ROCK-2A-2F.patch
deleted file mode 100644 (file)
index e1265d6..0000000
+++ /dev/null
@@ -1,421 +0,0 @@
-From 02b18f9cf43dcc9bea066a2390b8c8a59313aad0 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 19 Oct 2025 20:58:36 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 2A/2F
-
-The ROCK 2A and ROCK 2F is a high-performance single board computer
-developed by Radxa, based on the Rockchip RK3528A SoC.
-
-Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Tested-by: Yao Zi <ziyao@disroot.org>
-Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
-Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
-Link: https://lore.kernel.org/r/20250717103720.2853031-3-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
-[ upstream commit: 5b71b3d9aa61626d6a93ed2f761a748aa2ecfa95 ]
-
-(cherry picked from commit d272bc0c747a5af49cf98140ebd25a702f84ab52)
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- .../src/arm64/rockchip/rk3528-rock-2.dtsi     | 293 ++++++++++++++++++
- .../src/arm64/rockchip/rk3528-rock-2a.dts     |  82 +++++
- .../src/arm64/rockchip/rk3528-rock-2f.dts     |  10 +
- 3 files changed, 385 insertions(+)
- create mode 100644 dts/upstream/src/arm64/rockchip/rk3528-rock-2.dtsi
- create mode 100644 dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts
- create mode 100644 dts/upstream/src/arm64/rockchip/rk3528-rock-2f.dts
-
---- /dev/null
-+++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2.dtsi
-@@ -0,0 +1,288 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pwm/pwm.h>
-+#include "rk3528.dtsi"
-+
-+/ {
-+      aliases {
-+              i2c1 = &i2c1;
-+              mmc0 = &sdhci;
-+              mmc1 = &sdmmc;
-+              serial0 = &uart0;
-+      };
-+
-+      chosen {
-+              stdout-path = "serial0:1500000n8";
-+      };
-+
-+      adc-keys {
-+              compatible = "adc-keys";
-+              io-channels = <&saradc 0>;
-+              io-channel-names = "buttons";
-+              keyup-threshold-microvolt = <1800000>;
-+              poll-interval = <100>;
-+
-+              button-maskrom {
-+                      label = "MASKROM";
-+                      linux,code = <KEY_SETUP>;
-+                      press-threshold-microvolt = <0>;
-+              };
-+      };
-+
-+      leds: leds {
-+              compatible = "gpio-leds";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&state_led_b>;
-+
-+              led-0 {
-+                      color = <LED_COLOR_ID_BLUE>;
-+                      default-state = "on";
-+                      function = LED_FUNCTION_HEARTBEAT;
-+                      gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
-+                      linux,default-trigger = "heartbeat";
-+              };
-+      };
-+
-+      vdd_0v9: regulator-0v9-vdd {
-+              compatible = "regulator-fixed";
-+              regulator-name = "vdd_0v9";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <900000>;
-+              regulator-max-microvolt = <900000>;
-+              vin-supply = <&vcc5v0_sys>;
-+      };
-+
-+      vcc_ddr: regulator-1v1-vcc-ddr {
-+              compatible = "regulator-fixed";
-+              regulator-name = "vcc_ddr";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <1100000>;
-+              regulator-max-microvolt = <1100000>;
-+              vin-supply = <&vcc5v0_sys>;
-+      };
-+
-+      vcc_1v8: regulator-1v8-vcc {
-+              compatible = "regulator-fixed";
-+              regulator-name = "vcc_1v8";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <1800000>;
-+              regulator-max-microvolt = <1800000>;
-+              vin-supply = <&vcc_3v3>;
-+      };
-+
-+      vcc_3v3: regulator-3v3-vcc {
-+              compatible = "regulator-fixed";
-+              regulator-name = "vcc_3v3";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <3300000>;
-+              regulator-max-microvolt = <3300000>;
-+              vin-supply = <&vcc5v0_sys>;
-+      };
-+
-+      vcc_wifi: regulator-3v3-vcc-wifi {
-+              compatible = "regulator-fixed";
-+              enable-active-high;
-+              gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&usb_wifi_pwr>;
-+              regulator-name = "vcc_wifi";
-+              regulator-min-microvolt = <3300000>;
-+              regulator-max-microvolt = <3300000>;
-+              vin-supply = <&vcc_3v3>;
-+      };
-+
-+      vcc5v0_sys: regulator-5v0-vcc-sys {
-+              compatible = "regulator-fixed";
-+              regulator-name = "vcc5v0_sys";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <5000000>;
-+              regulator-max-microvolt = <5000000>;
-+      };
-+
-+      vcc5v0_usb20: regulator-5v0-vcc-usb20 {
-+              compatible = "regulator-fixed";
-+              enable-active-high;
-+              gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&usb_host_en>;
-+              regulator-name = "vcc5v0_usb20";
-+              regulator-min-microvolt = <5000000>;
-+              regulator-max-microvolt = <5000000>;
-+              vin-supply = <&vcc5v0_sys>;
-+      };
-+
-+      vccio_sd: regulator-vccio-sd {
-+              compatible = "regulator-gpio";
-+              gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&sdmmc_vol_ctrl_h>;
-+              regulator-name = "vccio_sd";
-+              regulator-min-microvolt = <1800000>;
-+              regulator-max-microvolt = <3300000>;
-+              states = <1800000 0x0>, <3300000 0x1>;
-+              vin-supply = <&vcc5v0_sys>;
-+      };
-+
-+      vdd_arm: regulator-vdd-arm {
-+              compatible = "pwm-regulator";
-+              pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
-+              pwm-supply = <&vcc5v0_sys>;
-+              regulator-name = "vdd_arm";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <746000>;
-+              regulator-max-microvolt = <1201000>;
-+              regulator-settling-time-up-us = <250>;
-+      };
-+
-+      vdd_logic: regulator-vdd-logic {
-+              compatible = "pwm-regulator";
-+              pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
-+              pwm-supply = <&vcc5v0_sys>;
-+              regulator-name = "vdd_logic";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              regulator-min-microvolt = <705000>;
-+              regulator-max-microvolt = <1006000>;
-+              regulator-settling-time-up-us = <250>;
-+      };
-+
-+      rfkill {
-+              compatible = "rfkill-gpio";
-+              label = "rfkill-wlan";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&wifi_reg_on_h>;
-+              radio-type = "wlan";
-+              shutdown-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
-+      };
-+};
-+
-+&cpu0 {
-+      cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+      cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+      cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+      cpu-supply = <&vdd_arm>;
-+};
-+
-+&i2c1 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c1m0_xfer>;
-+      status = "okay";
-+
-+      eeprom@50 {
-+              compatible = "belling,bl24c16a", "atmel,24c16";
-+              reg = <0x50>;
-+              pagesize = <16>;
-+              read-only;
-+              vcc-supply = <&vcc_3v3>;
-+      };
-+};
-+
-+&pinctrl {
-+      bluetooth {
-+              bt_wake_host_h: bt-wake-host-h {
-+                      rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+              };
-+
-+              host_wake_bt_h: host-wake-bt-h {
-+                      rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      leds {
-+              state_led_b: state-led-b {
-+                      rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      sdmmc {
-+              sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
-+                      rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      usb {
-+              usb_host_en: usb-host-en {
-+                      rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      wifi {
-+              usb_wifi_pwr: usb-wifi-pwr {
-+                      rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+
-+              wifi_reg_on_h: wifi-reg-on-h {
-+                      rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+
-+              wifi_wake_host_h: wifi-wake-host-h {
-+                      rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
-+              };
-+      };
-+};
-+
-+&pwm1 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&pwm1m0_pins>;
-+      status = "okay";
-+};
-+
-+&pwm2 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&pwm2m0_pins>;
-+      status = "okay";
-+};
-+
-+&saradc {
-+      vref-supply = <&vcc_1v8>;
-+      status = "okay";
-+};
-+
-+&sdhci {
-+      bus-width = <8>;
-+      cap-mmc-highspeed;
-+      mmc-hs200-1_8v;
-+      no-sd;
-+      no-sdio;
-+      non-removable;
-+      vmmc-supply = <&vcc_3v3>;
-+      vqmmc-supply = <&vcc_1v8>;
-+      status = "okay";
-+};
-+
-+&sdmmc {
-+      bus-width = <4>;
-+      cap-mmc-highspeed;
-+      cap-sd-highspeed;
-+      disable-wp;
-+      max-frequency = <100000000>;
-+      sd-uhs-sdr104;
-+      vmmc-supply = <&vcc_3v3>;
-+      vqmmc-supply = <&vccio_sd>;
-+      status = "okay";
-+};
-+
-+&uart0 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&uart0m0_xfer>;
-+      status = "okay";
-+};
---- /dev/null
-+++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts
-@@ -0,0 +1,82 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include "rk3528-rock-2.dtsi"
-+
-+/ {
-+      model = "Radxa ROCK 2A";
-+      compatible = "radxa,rock-2a", "rockchip,rk3528";
-+
-+      aliases {
-+              ethernet0 = &gmac1;
-+      };
-+
-+      vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg {
-+              compatible = "regulator-fixed";
-+              enable-active-high;
-+              gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&usb_otg_en>;
-+              regulator-name = "vcc5v0_usb30_otg";
-+              regulator-min-microvolt = <5000000>;
-+              regulator-max-microvolt = <5000000>;
-+              vin-supply = <&vcc5v0_sys>;
-+      };
-+};
-+
-+&gmac1 {
-+      clock_in_out = "output";
-+      phy-handle = <&rgmii_phy>;
-+      phy-mode = "rgmii-id";
-+      phy-supply = <&vcc_3v3>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
-+                  <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
-+      status = "okay";
-+};
-+
-+&leds {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&state_led_b>, <&sys_led_g>;
-+
-+      led-1 {
-+              color = <LED_COLOR_ID_GREEN>;
-+              default-state = "on";
-+              function = LED_FUNCTION_STATUS;
-+              gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
-+              linux,default-trigger = "default-on";
-+      };
-+};
-+
-+&mdio1 {
-+      rgmii_phy: ethernet-phy@1 {
-+              compatible = "ethernet-phy-ieee802.3-c22";
-+              reg = <0x1>;
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&gmac1_rstn_l>;
-+              reset-assert-us = <20000>;
-+              reset-deassert-us = <100000>;
-+              reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
-+      };
-+};
-+
-+&pinctrl {
-+      ethernet {
-+              gmac1_rstn_l: gmac1-rstn-l {
-+                      rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      leds {
-+              sys_led_g: sys-led-g {
-+                      rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      usb {
-+              usb_otg_en: usb-otg-en {
-+                      rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+};
---- /dev/null
-+++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2f.dts
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include "rk3528-rock-2.dtsi"
-+
-+/ {
-+      model = "Radxa ROCK 2F";
-+      compatible = "radxa,rock-2f", "rockchip,rk3528";
-+};
diff --git a/package/boot/uboot-rockchip/patches/007-board-rockchip-Add-Radxa-ROCK-2A-2F.patch b/package/boot/uboot-rockchip/patches/007-board-rockchip-Add-Radxa-ROCK-2A-2F.patch
deleted file mode 100644 (file)
index 85587ff..0000000
+++ /dev/null
@@ -1,317 +0,0 @@
-From 15b368fb5fde5663dd29176ee548053770dd74d4 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 19 Oct 2025 20:58:37 +0000
-Subject: [PATCH] board: rockchip: Add Radxa ROCK 2A/2F
-
-The ROCK 2 Family is a high-performance SBC (Single Board Computer)
-developed by Radxa, based on the Rockchip RK3528A.
-
-The Radxa E20C shares some board characteristics with the ROCK 2 family
-boards.
-
-Add support for the ROCK 2A and 2F boards. The radxa-e20c-rk3528 target
-is also extended to support booting ROCK 2 boards.
-
-Features tested on a ROCK 2A v1.202:
-- SD-card boot
-- Ethernet
-- USB host (with pending DT changes)
-
-Features tested on a ROCK 2F v1.016:
-- SD-card boot
-- eMMC boot
-- USB host (with pending DT changes)
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi |  5 ++
- arch/arm/dts/rk3528-rock-2-u-boot.dtsi     | 16 +++++
- arch/arm/dts/rk3528-rock-2a-u-boot.dtsi    |  3 +
- arch/arm/dts/rk3528-rock-2f-u-boot.dtsi    |  3 +
- arch/arm/mach-rockchip/rk3528/Kconfig      |  7 +++
- board/radxa/rock-2-rk3528/Kconfig          | 14 +++++
- board/radxa/rock-2-rk3528/MAINTAINERS      |  6 ++
- board/radxa/rock-2-rk3528/Makefile         |  3 +
- board/radxa/rock-2-rk3528/rock-2-rk3528.c  | 60 +++++++++++++++++++
- configs/radxa-e20c-rk3528_defconfig        |  3 +
- configs/rock-2-rk3528_defconfig            | 68 ++++++++++++++++++++++
- doc/board/rockchip/rockchip.rst            |  1 +
- 12 files changed, 189 insertions(+)
- create mode 100644 arch/arm/dts/rk3528-rock-2-u-boot.dtsi
- create mode 100644 arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
- create mode 100644 arch/arm/dts/rk3528-rock-2f-u-boot.dtsi
- create mode 100644 board/radxa/rock-2-rk3528/Kconfig
- create mode 100644 board/radxa/rock-2-rk3528/MAINTAINERS
- create mode 100644 board/radxa/rock-2-rk3528/Makefile
- create mode 100644 board/radxa/rock-2-rk3528/rock-2-rk3528.c
- create mode 100644 configs/rock-2-rk3528_defconfig
-
---- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-@@ -6,6 +6,11 @@
-       mmc-hs200-1_8v;
- };
-+&saradc {
-+      bootph-pre-ram;
-+      vdd-microvolts = <1800000>;
-+};
-+
- &vdd_arm {
-       regulator-init-microvolt = <953000>;
- };
---- /dev/null
-+++ b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi
-@@ -0,0 +1,16 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3528-u-boot.dtsi"
-+
-+&saradc {
-+      bootph-pre-ram;
-+      vdd-microvolts = <1800000>;
-+};
-+
-+&vdd_arm {
-+      regulator-init-microvolt = <953000>;
-+};
-+
-+&vdd_logic {
-+      regulator-init-microvolt = <900000>;
-+};
---- /dev/null
-+++ b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
-@@ -0,0 +1,3 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3528-rock-2-u-boot.dtsi"
---- /dev/null
-+++ b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi
-@@ -0,0 +1,3 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3528-rock-2-u-boot.dtsi"
---- a/arch/arm/mach-rockchip/rk3528/Kconfig
-+++ b/arch/arm/mach-rockchip/rk3528/Kconfig
-@@ -1,5 +1,10 @@
- if ROCKCHIP_RK3528
-+config TARGET_RADXA_ROCK_2_RK3528
-+      bool "Radxa ROCK 2A/2F"
-+      help
-+        Radxa ROCK 2A/2F single board computers with a RK3528A SoC.
-+
- config ROCKCHIP_BOOT_MODE_REG
-       default 0xff370200
-@@ -9,6 +14,8 @@ config ROCKCHIP_STIMER_BASE
- config SYS_SOC
-       default "rk3528"
-+source "board/radxa/rock-2-rk3528/Kconfig"
-+
- config SYS_CONFIG_NAME
-       default "rk3528_common"
---- /dev/null
-+++ b/board/radxa/rock-2-rk3528/Kconfig
-@@ -0,0 +1,14 @@
-+if TARGET_RADXA_ROCK_2_RK3528
-+
-+config SYS_BOARD
-+      default "rock-2-rk3528"
-+
-+config SYS_VENDOR
-+      default "radxa"
-+
-+config BOARD_SPECIFIC_OPTIONS # dummy
-+      def_bool y
-+      select ADC
-+      select SPL_ADC
-+
-+endif
---- /dev/null
-+++ b/board/radxa/rock-2-rk3528/MAINTAINERS
-@@ -0,0 +1,6 @@
-+RADXA-ROCK-2-RK3528
-+M:    Jonas Karlman <jonas@kwiboo.se>
-+S:    Maintained
-+F:    board/radxa/rock-2-rk3528
-+F:    configs/rock-2-rk3528_defconfig
-+F:    arch/arm/dts/rk3528-rock-2*
---- /dev/null
-+++ b/board/radxa/rock-2-rk3528/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0+
-+
-+obj-y += rock-2-rk3528.o
---- /dev/null
-+++ b/board/radxa/rock-2-rk3528/rock-2-rk3528.c
-@@ -0,0 +1,60 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <adc.h>
-+#include <env.h>
-+
-+#define HW_ID_CHANNEL 2
-+
-+struct board_model {
-+      unsigned int low;
-+      unsigned int high;
-+      const char *fdtfile;
-+};
-+
-+static const struct board_model board_models[] = {
-+      { 63, 278, "rockchip/rk3528-rock-2a.dtb" },
-+      { 291, 392, "rockchip/rk3528-radxa-e20c.dtb" },
-+      { 519, 733, "rockchip/rk3528-rock-2f.dtb" },
-+};
-+
-+static const struct board_model *get_board_model(void)
-+{
-+      unsigned int val;
-+      int i, ret;
-+
-+      ret = adc_channel_single_shot("adc@ffae0000", HW_ID_CHANNEL, &val);
-+      if (ret)
-+              return NULL;
-+
-+      for (i = 0; i < ARRAY_SIZE(board_models); i++) {
-+              unsigned int min = board_models[i].low;
-+              unsigned int max = board_models[i].high;
-+
-+              if (min <= val && val <= max)
-+                      return &board_models[i];
-+      }
-+
-+      return NULL;
-+}
-+
-+int rk_board_late_init(void)
-+{
-+      const struct board_model *model = get_board_model();
-+
-+      if (model)
-+              env_set("fdtfile", model->fdtfile);
-+
-+      return 0;
-+}
-+
-+int board_fit_config_name_match(const char *name)
-+{
-+      const struct board_model *model = get_board_model();
-+
-+      if (model && !strcmp(name, model->fdtfile))
-+              return 0;
-+
-+      return -EINVAL;
-+}
---- a/configs/radxa-e20c-rk3528_defconfig
-+++ b/configs/radxa-e20c-rk3528_defconfig
-@@ -4,12 +4,14 @@ CONFIG_COUNTER_FREQUENCY=24000000
- CONFIG_ARCH_ROCKCHIP=y
- CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
- CONFIG_ROCKCHIP_RK3528=y
-+CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
- CONFIG_SYS_LOAD_ADDR=0xc00800
- CONFIG_DEBUG_UART_BASE=0xFF9F0000
- CONFIG_DEBUG_UART_CLOCK=24000000
- CONFIG_DEBUG_UART=y
- CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
- # CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_BOARD_RNG_SEED=y
- CONFIG_SPL_MAX_SIZE=0x40000
- # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
- CONFIG_CMD_MEMINFO=y
-@@ -26,6 +28,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
- CONFIG_CMD_RNG=y
- CONFIG_CMD_REGULATOR=y
- # CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_OF_LIST="rockchip/rk3528-radxa-e20c rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f"
- CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
- CONFIG_BUTTON=y
- CONFIG_BUTTON_ADC=y
---- /dev/null
-+++ b/configs/rock-2-rk3528_defconfig
-@@ -0,0 +1,68 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-rock-2a"
-+CONFIG_ROCKCHIP_RK3528=y
-+CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
-+CONFIG_SYS_LOAD_ADDR=0xc00800
-+CONFIG_DEBUG_UART_BASE=0xFF9F0000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_DEBUG_UART=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-rock-2a.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_BOARD_RNG_SEED=y
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_CMD_MEMINFO=y
-+CONFIG_CMD_MEMINFO_MAP=y
-+CONFIG_CMD_ADC=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MISC=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_ROCKUSB=y
-+CONFIG_CMD_USB_MASS_STORAGE=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_RNG=y
-+CONFIG_CMD_REGULATOR=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_OF_LIST="rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f rockchip/rk3528-radxa-e20c"
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_BUTTON=y
-+CONFIG_BUTTON_ADC=y
-+CONFIG_BUTTON_GPIO=y
-+# CONFIG_USB_FUNCTION_FASTBOOT is not set
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_LED=y
-+CONFIG_LED_GPIO=y
-+CONFIG_SUPPORT_EMMC_RPMB=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_SDMA=y
-+CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_PHY_MOTORCOMM=y
-+CONFIG_PHY_REALTEK=y
-+CONFIG_DM_MDIO=y
-+CONFIG_DWC_ETH_QOS=y
-+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_GPIO=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_USB_FUNCTION_ROCKUSB=y
-+CONFIG_ERRNO_STR=y
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -102,6 +102,7 @@ List of mainline supported Rockchip boar
- * rk3528
-      - Generic RK3528 (generic-rk3528)
-      - Radxa E20C (radxa-e20c-rk3528)
-+     - Radxa ROCK 2A/2F (rock-2-rk3528)
- * rk3566
-      - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
diff --git a/package/boot/uboot-rockchip/patches/008-board-rockchip-add-Lunzn-FastRhino-R66S.patch b/package/boot/uboot-rockchip/patches/008-board-rockchip-add-Lunzn-FastRhino-R66S.patch
deleted file mode 100644 (file)
index b354758..0000000
+++ /dev/null
@@ -1,125 +0,0 @@
-From 37a5383059d0c3d8a72394cbffef775042a40acd Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Mon, 8 Sep 2025 19:32:18 +0800
-Subject: [PATCH] board: rockchip: add Lunzn FastRhino R66S
-
-Lunzn Fastrhino R66S is a high-performance mini router.
-
-Specification:
-- Rockchip RK3568
-- 1/2GB LPDDR4 RAM
-- SD card slot
-- 2x USB 3.0 Port
-- 2x 2500 Base-T (PCIe, r8125b)
-- 12v DC Jack
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- .../arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi |  3 +
- board/rockchip/evb_rk3568/MAINTAINERS         |  7 ++
- configs/fastrhino-r66s-rk3568_defconfig       | 64 +++++++++++++++++++
- doc/board/rockchip/rockchip.rst               |  1 +
- 4 files changed, 75 insertions(+)
- create mode 100644 arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
- create mode 100644 configs/fastrhino-r66s-rk3568_defconfig
-
---- /dev/null
-+++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
-@@ -0,0 +1,3 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+
-+#include "rk356x-u-boot.dtsi"
---- a/board/rockchip/evb_rk3568/MAINTAINERS
-+++ b/board/rockchip/evb_rk3568/MAINTAINERS
-@@ -14,6 +14,13 @@ F:  configs/evb-rk3568_defconfig
- F:    arch/arm/dts/rk3568-evb-u-boot.dtsi
- F:    arch/arm/dts/rk3568-evb.dts
-+FASTRHINO-R66S-RK3568
-+M:    Tianling Shen <cnsztl@gmail.com>
-+R:    Jonas Karlman <jonas@kwiboo.se>
-+S:    Maintained
-+F:    configs/fastrhino-r66s-rk3568_defconfig
-+F:    arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
-+
- GENERIC-RK3568
- M:    Jonas Karlman <jonas@kwiboo.se>
- S:    Maintained
---- /dev/null
-+++ b/configs/fastrhino-r66s-rk3568_defconfig
-@@ -0,0 +1,64 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s"
-+CONFIG_ROCKCHIP_RK3568=y
-+CONFIG_SPL_SERIAL=y
-+CONFIG_SYS_LOAD_ADDR=0xc00800
-+CONFIG_DEBUG_UART_BASE=0xFE660000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_PCI=y
-+CONFIG_DEBUG_UART=y
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_FIT_SIGNATURE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_LEGACY_IMAGE_FORMAT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_ATF=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_I2C=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_PMIC=y
-+CONFIG_CMD_REGULATOR=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_OF_LIVE=y
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_SPL_DM_SEQ_ALIAS=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_SPL_CLK=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MISC=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_RTL8169=y
-+CONFIG_PCIE_DW_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_SPL_RAM=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_SYSRESET=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_ERRNO_STR=y
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -129,6 +129,7 @@ List of mainline supported Rockchip boar
-      - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
-      - Generic RK3566/RK3568 (generic-rk3568)
-      - Hardkernel ODROID-M1 (odroid-m1-rk3568)
-+     - Lunzn FastRhino R66S (fastrhino-r66s-rk3568)
-      - QNAP TS-433 (qnap-ts433-rk3568)
-      - Radxa E25 Carrier Board (radxa-e25-rk3568)
-      - Radxa ROCK 3A (rock-3a-rk3568)
diff --git a/package/boot/uboot-rockchip/patches/009-mmc-rockchip_sdhci-Set-xx_TAP_VALUE-for-RK3528.patch b/package/boot/uboot-rockchip/patches/009-mmc-rockchip_sdhci-Set-xx_TAP_VALUE-for-RK3528.patch
deleted file mode 100644 (file)
index 88a9055..0000000
+++ /dev/null
@@ -1,109 +0,0 @@
-From 498a9756adf57e94af64e31b144a6698c656c50a Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 14 Jul 2025 20:34:07 +0000
-Subject: [PATCH] mmc: rockchip_sdhci: Set xx_TAP_VALUE for RK3528
-
-eMMC erase and write support on RK3528 is somewhat unreliable, sometime
-e.g. mmc erase and write commands will fail with an error.
-
-Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
-to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
-
-This is only enabled for RK3528, remaining SoCs still use the automatic
-tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
-for RK3528.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- drivers/mmc/rockchip_sdhci.c | 27 ++++++++++++++++++++++-----
- 1 file changed, 22 insertions(+), 5 deletions(-)
-
---- a/drivers/mmc/rockchip_sdhci.c
-+++ b/drivers/mmc/rockchip_sdhci.c
-@@ -9,6 +9,7 @@
- #include <dm.h>
- #include <dm/ofnode.h>
- #include <dt-structs.h>
-+#include <linux/bitfield.h>
- #include <linux/delay.h>
- #include <linux/err.h>
- #include <linux/libfdt.h>
-@@ -86,6 +87,9 @@
- #define DLL_CMDOUT_SRC_CLK_NEG                BIT(28)
- #define DLL_CMDOUT_EN_SRC_CLK_NEG     BIT(29)
- #define DLL_CMDOUT_BOTH_CLK_EDGE      BIT(30)
-+#define DLL_TAPVALUE_FROM_SW          BIT(25)
-+#define DLL_TAP_VALUE_PREP(x)         FIELD_PREP(GENMASK(15, 8), (x))
-+#define DLL_LOCK_VALUE_GET(x)         FIELD_GET(GENMASK(7, 0), (x))
- #define DLL_LOCK_WO_TMOUT(x) \
-       ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
-@@ -93,6 +97,7 @@
- #define ROCKCHIP_MAX_CLKS             3
- #define FLAG_INVERTER_FLAG_IN_RXCLK   BIT(0)
-+#define FLAG_TAPVALUE_FROM_SW         BIT(1)
- struct rockchip_sdhc_plat {
-       struct mmc_config cfg;
-@@ -317,7 +322,7 @@ static int rk3568_sdhci_config_dll(struc
-       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
-       struct mmc *mmc = host->mmc;
-       int val, ret;
--      u32 extra, txclk_tapnum;
-+      u32 extra, txclk_tapnum, dll_tap_value;
-       if (!enable) {
-               sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
-@@ -347,7 +352,15 @@ static int rk3568_sdhci_config_dll(struc
-               if (ret)
-                       return ret;
--              extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
-+              if (data->flags & FLAG_TAPVALUE_FROM_SW)
-+                      dll_tap_value = DLL_TAPVALUE_FROM_SW |
-+                                      DLL_TAP_VALUE_PREP(DLL_LOCK_VALUE_GET(val) * 2);
-+              else
-+                      dll_tap_value = 0;
-+
-+              extra = DWCMSHC_EMMC_DLL_DLYENA |
-+                      DLL_RXCLK_ORI_GATE |
-+                      dll_tap_value;
-               if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK)
-                       extra |= DLL_RXCLK_NO_INVERTER;
-               sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
-@@ -361,19 +374,22 @@ static int rk3568_sdhci_config_dll(struc
-                               DLL_CMDOUT_BOTH_CLK_EDGE |
-                               DWCMSHC_EMMC_DLL_DLYENA |
-                               data->hs400_cmdout_tapnum |
--                              DLL_CMDOUT_TAPNUM_FROM_SW;
-+                              DLL_CMDOUT_TAPNUM_FROM_SW |
-+                              dll_tap_value;
-                       sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
-               }
-               extra = DWCMSHC_EMMC_DLL_DLYENA |
-                       DLL_TXCLK_TAPNUM_FROM_SW |
-                       DLL_TXCLK_NO_INVERTER |
--                      txclk_tapnum;
-+                      txclk_tapnum |
-+                      dll_tap_value;
-               sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
-               extra = DWCMSHC_EMMC_DLL_DLYENA |
-                       data->hs400_strbin_tapnum |
--                      DLL_STRBIN_TAPNUM_FROM_SW;
-+                      DLL_STRBIN_TAPNUM_FROM_SW |
-+                      dll_tap_value;
-               sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
-       } else {
-               /*
-@@ -663,6 +679,7 @@ static const struct sdhci_data rk3528_da
-       .set_ios_post = rk3568_sdhci_set_ios_post,
-       .set_clock = rk3568_sdhci_set_clock,
-       .config_dll = rk3568_sdhci_config_dll,
-+      .flags = FLAG_TAPVALUE_FROM_SW,
-       .hs200_txclk_tapnum = 0xc,
-       .hs400_txclk_tapnum = 0x6,
-       .hs400_cmdout_tapnum = 0x6,
index 9eef599337491eb1d6a543a166a2e90741d5b772..813d753533feb644e82498a673fdecc5c0306ee6 100644 (file)
@@ -27,7 +27,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  #include <misc.h>
  #include <spl.h>
  #include <asm/armv8/mmu.h>
  #include <misc.h>
  #include <spl.h>
  #include <asm/armv8/mmu.h>
-@@ -200,6 +201,15 @@ int arch_cpu_init(void)
+@@ -213,6 +214,15 @@ int arch_cpu_init(void)
  
  #define RK3588_OTP_CPU_CODE_OFFSET            0x02
  #define RK3588_OTP_SPECIFICATION_OFFSET               0x06
  
  #define RK3588_OTP_CPU_CODE_OFFSET            0x02
  #define RK3588_OTP_SPECIFICATION_OFFSET               0x06
@@ -43,7 +43,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  
  int checkboard(void)
  {
  
  int checkboard(void)
  {
-@@ -245,3 +255,199 @@ int checkboard(void)
+@@ -258,3 +268,199 @@ int checkboard(void)
  
        return 0;
  }
  
        return 0;
  }
index 8a8ca8e293fd750ca000d9b7d4d85f717305f0ff..2a720277e0004278d043ba7e890d8f21910ab21e 100644 (file)
@@ -61,7 +61,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  CONFIG_SPL_MAX_SIZE=0x40000
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
  CONFIG_SPL_MAX_SIZE=0x40000
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
-@@ -151,7 +151,7 @@ List of mainline supported Rockchip boar
+@@ -154,7 +154,7 @@ List of mainline supported Rockchip boar
       - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
       - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
       - GameForce Ace (gameforce-ace-rk3588s)
       - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
       - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
       - GameForce Ace (gameforce-ace-rk3588s)