fix the Aruba ethernet drivers for 2.6.17
[openwrt/openwrt.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
786 @@ -0,0 +1,134 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + switch (mips_machtype) {
909 + case MACH_ARUBA_AP70:
910 + return "Aruba AP70";
911 + case MACH_ARUBA_AP65:
912 + return "Aruba AP65";
913 + case MACH_ARUBA_AP60:
914 + return "Aruba AP60/AP61";
915 + default:
916 + return "Aruba UNKNOWN";
917 + }
918 +}
919 +
920 +EXPORT_SYMBOL(get_system_type);
921 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
922 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
923 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
924 @@ -0,0 +1,108 @@
925 +/**************************************************************************
926 + *
927 + * BRIEF MODULE DESCRIPTION
928 + * timer routines for IDT EB434 boards
929 + *
930 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
931 + *
932 + * This program is free software; you can redistribute it and/or modify it
933 + * under the terms of the GNU General Public License as published by the
934 + * Free Software Foundation; either version 2 of the License, or (at your
935 + * option) any later version.
936 + *
937 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
938 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
939 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
940 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
941 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
942 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
943 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
944 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
945 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
946 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
947 + *
948 + * You should have received a copy of the GNU General Public License along
949 + * with this program; if not, write to the Free Software Foundation, Inc.,
950 + * 675 Mass Ave, Cambridge, MA 02139, USA.
951 + *
952 + *
953 + **************************************************************************
954 + * May 2004 rkt, neb
955 + *
956 + * Initial Release
957 + *
958 + *
959 + *
960 + **************************************************************************
961 + */
962 +
963 +#include <linux/config.h>
964 +#include <linux/init.h>
965 +#include <linux/kernel_stat.h>
966 +#include <linux/sched.h>
967 +#include <linux/spinlock.h>
968 +#include <linux/mc146818rtc.h>
969 +#include <linux/irq.h>
970 +#include <linux/timex.h>
971 +
972 +#include <linux/param.h>
973 +#include <asm/mipsregs.h>
974 +#include <asm/ptrace.h>
975 +#include <asm/time.h>
976 +#include <asm/hardirq.h>
977 +
978 +#include <asm/mipsregs.h>
979 +#include <asm/ptrace.h>
980 +#include <asm/debug.h>
981 +#include <asm/time.h>
982 +
983 +#include <asm/idt-boards/rc32434/rc32434.h>
984 +
985 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
986 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
987 +
988 +extern unsigned int idt_cpu_freq;
989 +
990 +static unsigned long __init cal_r4koff(void)
991 +{
992 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
993 + return (mips_hpt_frequency / HZ);
994 +}
995 +
996 +void __init aruba_time_init(void)
997 +{
998 + unsigned int est_freq, flags;
999 + local_irq_save(flags);
1000 +
1001 + printk("calculating r4koff... ");
1002 + r4k_offset = cal_r4koff();
1003 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1004 +
1005 + est_freq = 2 * r4k_offset * HZ;
1006 + est_freq += 5000; /* round */
1007 + est_freq -= est_freq % 10000;
1008 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1009 + (est_freq % 1000000) * 100 / 1000000);
1010 + local_irq_restore(flags);
1011 +
1012 +}
1013 +
1014 +void __init aruba_timer_setup(struct irqaction *irq)
1015 +{
1016 + /* we are using the cpu counter for timer interrupts */
1017 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1018 +
1019 + /* to generate the first timer interrupt */
1020 + r4k_cur = (read_c0_count() + r4k_offset);
1021 + write_c0_compare(r4k_cur);
1022 +
1023 +}
1024 +
1025 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1026 +{
1027 + irq_enter();
1028 + kstat_this_cpu.irqs[irq]++;
1029 +
1030 + timer_interrupt(irq, NULL, regs);
1031 + irq_exit();
1032 +}
1033 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1034 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
1035 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1036 @@ -227,6 +227,17 @@
1037 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1038 a kernel for this platform.
1039
1040 +config MACH_ARUBA
1041 + bool "Support for the ARUBA product line"
1042 + select DMA_NONCOHERENT
1043 + select CPU_HAS_PREFETCH
1044 + select HW_HAS_PCI
1045 + select SWAP_IO_SPACE
1046 + select SYS_SUPPORTS_32BIT_KERNEL
1047 + select SYS_HAS_CPU_MIPS32_R1
1048 + select SYS_SUPPORTS_BIG_ENDIAN
1049 +
1050 +
1051 config MACH_JAZZ
1052 bool "Jazz family of machines"
1053 select ARC
1054 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1055 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
1056 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
1057 @@ -145,6 +145,14 @@
1058 #
1059
1060 #
1061 +# Aruba
1062 +#
1063 +
1064 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1065 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1066 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1067 +
1068 +#
1069 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1070 #
1071 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1072 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1073 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
1074 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
1075 @@ -876,7 +876,6 @@
1076 case CPU_R10000:
1077 case CPU_R12000:
1078 case CPU_R14000:
1079 - case CPU_4KC:
1080 case CPU_SB1:
1081 case CPU_SB1A:
1082 case CPU_4KSC:
1083 @@ -904,6 +903,7 @@
1084 tlbw(p);
1085 break;
1086
1087 + case CPU_4KC:
1088 case CPU_4KEC:
1089 case CPU_24K:
1090 case CPU_34K:
1091 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1092 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
1093 +++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
1094 @@ -187,6 +187,13 @@
1095
1096 source "drivers/net/arm/Kconfig"
1097
1098 +config IDT_RC32434_ETH
1099 + tristate "IDT RC32434 Local Ethernet support"
1100 + depends on NET_ETHERNET
1101 + help
1102 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1103 + To compile this driver as a module, choose M here.
1104 +
1105 config MACE
1106 tristate "MACE (Power Mac ethernet) support"
1107 depends on NET_ETHERNET && PPC_PMAC && PPC32
1108 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1109 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
1110 +++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
1111 @@ -38,6 +38,7 @@
1112
1113 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1114
1115 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1116 obj-$(CONFIG_DGRS) += dgrs.o
1117 obj-$(CONFIG_VORTEX) += 3c59x.o
1118 obj-$(CONFIG_TYPHOON) += typhoon.o
1119 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1120 --- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
1121 +++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
1122 @@ -771,6 +771,49 @@
1123 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1124 static struct ethtool_ops ethtool_ops;
1125
1126 +#ifdef CONFIG_MACH_ARUBA
1127 +
1128 +#include <linux/ctype.h>
1129 +
1130 +#ifndef ERR
1131 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1132 +#endif
1133 +
1134 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1135 +{
1136 + int i, j;
1137 + unsigned char result, value;
1138 +
1139 + for (i=0; i<6; i++) {
1140 + result = 0;
1141 + if (i != 5 && *(macstr+2) != ':') {
1142 + ERR("invalid mac address format: %d %c\n",
1143 + i, *(macstr+2));
1144 + return -EINVAL;
1145 + }
1146 + for (j=0; j<2; j++) {
1147 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1148 + toupper(*macstr)-'A'+10) < 16) {
1149 + result = result*16 + value;
1150 + macstr++;
1151 + }
1152 + else {
1153 + ERR("invalid mac address "
1154 + "character: %c\n", *macstr);
1155 + return -EINVAL;
1156 + }
1157 + }
1158 +
1159 + macstr++;
1160 + dev->dev_addr[i] = result;
1161 + }
1162 +
1163 + dev->dev_addr[5]++;
1164 + return 0;
1165 +}
1166 +
1167 +#endif
1168 +
1169 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1170 {
1171 return (void __iomem *) dev->base_addr;
1172 @@ -871,6 +914,7 @@
1173 goto err_ioremap;
1174 }
1175
1176 +#ifndef CONFIG_MACH_ARUBA
1177 /* Work around the dropped serial bit. */
1178 prev_eedata = eeprom_read(ioaddr, 6);
1179 for (i = 0; i < 3; i++) {
1180 @@ -879,6 +923,19 @@
1181 dev->dev_addr[i*2+1] = eedata >> 7;
1182 prev_eedata = eedata;
1183 }
1184 +#else
1185 + {
1186 + char mac[32];
1187 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1188 + extern char *getenv(char *e);
1189 + memset(mac, 0, 32);
1190 + memcpy(mac, getenv("ethaddr"), 17);
1191 + if (parse_mac_addr(dev, mac)){
1192 + printk("%s: MAC address not found\n", __func__);
1193 + memcpy(dev->dev_addr, def_mac, 6);
1194 + }
1195 + }
1196 +#endif
1197
1198 dev->base_addr = (unsigned long __force) ioaddr;
1199 dev->irq = irq;
1200 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1201 --- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1203 @@ -0,0 +1,1273 @@
1204 +/**************************************************************************
1205 + *
1206 + * BRIEF MODULE DESCRIPTION
1207 + * Driver for the IDT RC32434 on-chip ethernet controller.
1208 + *
1209 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1210 + *
1211 + * This program is free software; you can redistribute it and/or modify it
1212 + * under the terms of the GNU General Public License as published by the
1213 + * Free Software Foundation; either version 2 of the License, or (at your
1214 + * option) any later version.
1215 + *
1216 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1217 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1218 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1219 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1220 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1221 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1222 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1223 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1224 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1225 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1226 + *
1227 + * You should have received a copy of the GNU General Public License along
1228 + * with this program; if not, write to the Free Software Foundation, Inc.,
1229 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1230 + *
1231 + *
1232 + **************************************************************************
1233 + * May 2004 rkt, neb
1234 + *
1235 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1236 + *
1237 + * Aug 2004 Sadik
1238 + *
1239 + * Added NAPI
1240 + *
1241 + **************************************************************************
1242 + */
1243 +
1244 +#include <linux/config.h>
1245 +#include <linux/version.h>
1246 +#include <linux/module.h>
1247 +#include <linux/kernel.h>
1248 +#include <linux/moduleparam.h>
1249 +#include <linux/sched.h>
1250 +#include <linux/ctype.h>
1251 +#include <linux/types.h>
1252 +#include <linux/fcntl.h>
1253 +#include <linux/interrupt.h>
1254 +#include <linux/ptrace.h>
1255 +#include <linux/init.h>
1256 +#include <linux/ioport.h>
1257 +#include <linux/proc_fs.h>
1258 +#include <linux/in.h>
1259 +#include <linux/slab.h>
1260 +#include <linux/string.h>
1261 +#include <linux/delay.h>
1262 +#include <linux/netdevice.h>
1263 +#include <linux/etherdevice.h>
1264 +#include <linux/skbuff.h>
1265 +#include <linux/errno.h>
1266 +#include <asm/bootinfo.h>
1267 +#include <asm/system.h>
1268 +#include <asm/bitops.h>
1269 +#include <asm/pgtable.h>
1270 +#include <asm/segment.h>
1271 +#include <asm/io.h>
1272 +#include <asm/dma.h>
1273 +
1274 +#include "rc32434_eth.h"
1275 +
1276 +#define DRIVER_VERSION "(mar2904)"
1277 +
1278 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1279 +
1280 +
1281 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1282 + ((dev)->dev_addr[1]))
1283 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1284 + ((dev)->dev_addr[3] << 16) | \
1285 + ((dev)->dev_addr[4] << 8) | \
1286 + ((dev)->dev_addr[5]))
1287 +
1288 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1289 +static char mac0[18] = "08:00:06:05:40:01";
1290 +
1291 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,17)
1292 +module_param_string(mac0, mac0, 18, 0);
1293 +#else
1294 +MODULE_PARM(mac0, "c18");
1295 +#endif
1296 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1297 +
1298 +static struct rc32434_if_t {
1299 + char *name;
1300 + struct net_device *dev;
1301 + char* mac_str;
1302 + int weight;
1303 + u32 iobase;
1304 + u32 rxdmabase;
1305 + u32 txdmabase;
1306 + int rx_dma_irq;
1307 + int tx_dma_irq;
1308 + int rx_ovr_irq;
1309 + int tx_und_irq;
1310 +} rc32434_iflist[] =
1311 +{
1312 + {
1313 + "rc32434_eth0", NULL, mac0,
1314 + 64,
1315 + ETH0_PhysicalAddress,
1316 + ETH0_RX_DMA_ADDR,
1317 + ETH0_TX_DMA_ADDR,
1318 + ETH0_DMA_RX_IRQ,
1319 + ETH0_DMA_TX_IRQ,
1320 + ETH0_RX_OVR_IRQ,
1321 + ETH0_TX_UND_IRQ
1322 + }
1323 +};
1324 +
1325 +
1326 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1327 +{
1328 + int i, j;
1329 + unsigned char result, value;
1330 +
1331 + for (i=0; i<6; i++) {
1332 + result = 0;
1333 + if (i != 5 && *(macstr+2) != ':') {
1334 + ERR("invalid mac address format: %d %c\n",
1335 + i, *(macstr+2));
1336 + return -EINVAL;
1337 + }
1338 + for (j=0; j<2; j++) {
1339 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1340 + toupper(*macstr)-'A'+10) < 16) {
1341 + result = result*16 + value;
1342 + macstr++;
1343 + }
1344 + else {
1345 + ERR("invalid mac address "
1346 + "character: %c\n", *macstr);
1347 + return -EINVAL;
1348 + }
1349 + }
1350 +
1351 + macstr++;
1352 + dev->dev_addr[i] = result;
1353 + }
1354 +
1355 + return 0;
1356 +}
1357 +
1358 +
1359 +
1360 +static inline void rc32434_abort_tx(struct net_device *dev)
1361 +{
1362 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1363 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1364 +
1365 +}
1366 +
1367 +static inline void rc32434_abort_rx(struct net_device *dev)
1368 +{
1369 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1370 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1371 +
1372 +}
1373 +
1374 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1375 +{
1376 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1377 +}
1378 +
1379 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1380 +{
1381 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1382 +}
1383 +
1384 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1385 +{
1386 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1387 +}
1388 +
1389 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1390 +{
1391 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1392 +}
1393 +
1394 +#ifdef RC32434_PROC_DEBUG
1395 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1396 + int length, int *eof, void *data)
1397 +{
1398 + struct net_device *dev = (struct net_device *)data;
1399 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1400 + int len = 0;
1401 +
1402 + /* print out header */
1403 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1404 + len += sprintf (buf + len,
1405 + "DMA halt count = %10d, DMA run count = %10d\n",
1406 + lp->dma_halt_cnt, lp->dma_run_cnt);
1407 +
1408 + if (fpos >= len) {
1409 + *start = buf;
1410 + *eof = 1;
1411 + return 0;
1412 + }
1413 + *start = buf + fpos;
1414 +
1415 + if ((len -= fpos) > length)
1416 + return length;
1417 + *eof = 1;
1418 +
1419 + return len;
1420 +
1421 +}
1422 +#endif
1423 +
1424 +
1425 +/*
1426 + * Restart the RC32434 ethernet controller.
1427 + */
1428 +static int rc32434_restart(struct net_device *dev)
1429 +{
1430 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1431 +
1432 + /*
1433 + * Disable interrupts
1434 + */
1435 + disable_irq(lp->rx_irq);
1436 + disable_irq(lp->tx_irq);
1437 +#ifdef RC32434_REVISION
1438 + disable_irq(lp->ovr_irq);
1439 +#endif
1440 + disable_irq(lp->und_irq);
1441 +
1442 + /* Mask F E bit in Tx DMA */
1443 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1444 + /* Mask D H E bit in Rx DMA */
1445 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1446 +
1447 + rc32434_init(dev);
1448 + rc32434_multicast_list(dev);
1449 +
1450 + enable_irq(lp->und_irq);
1451 +#ifdef RC32434_REVISION
1452 + enable_irq(lp->ovr_irq);
1453 +#endif
1454 + enable_irq(lp->tx_irq);
1455 + enable_irq(lp->rx_irq);
1456 +
1457 + return 0;
1458 +}
1459 +
1460 +int rc32434_init_module(void)
1461 +{
1462 +#ifdef CONFIG_MACH_ARUBA
1463 + if (mips_machtype != MACH_ARUBA_AP70)
1464 + return 1;
1465 +#endif
1466 +
1467 + printk(KERN_INFO DRIVER_NAME " \n");
1468 + return rc32434_probe(0);
1469 +}
1470 +
1471 +static int rc32434_probe(int port_num)
1472 +{
1473 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1474 + struct rc32434_local *lp = NULL;
1475 + struct net_device *dev = NULL;
1476 + int i, retval,err;
1477 +
1478 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1479 + if(!dev) {
1480 + ERR("rc32434_eth: alloc_etherdev failed\n");
1481 + return -1;
1482 + }
1483 +
1484 + SET_MODULE_OWNER(dev);
1485 + bif->dev = dev;
1486 +
1487 +#ifdef CONFIG_MACH_ARUBA
1488 + {
1489 + extern char * getenv(char *e);
1490 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1491 + }
1492 +#endif
1493 +
1494 + printk("mac: %s\n", bif->mac_str);
1495 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1496 + ERR("MAC address parse failed\n");
1497 + free_netdev(dev);
1498 + return -1;
1499 + }
1500 +
1501 +
1502 + /* Initialize the device structure. */
1503 + if (dev->priv == NULL) {
1504 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1505 + memset(lp, 0, sizeof(struct rc32434_local));
1506 + }
1507 + else {
1508 + lp = (struct rc32434_local *)dev->priv;
1509 + }
1510 +
1511 + lp->rx_irq = bif->rx_dma_irq;
1512 + lp->tx_irq = bif->tx_dma_irq;
1513 + lp->ovr_irq = bif->rx_ovr_irq;
1514 + lp->und_irq = bif->tx_und_irq;
1515 +
1516 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1517 +
1518 + if (!lp->eth_regs) {
1519 + ERR("Can't remap eth registers\n");
1520 + retval = -ENXIO;
1521 + goto probe_err_out;
1522 + }
1523 +
1524 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1525 +
1526 + if (!lp->rx_dma_regs) {
1527 + ERR("Can't remap Rx DMA registers\n");
1528 + retval = -ENXIO;
1529 + goto probe_err_out;
1530 + }
1531 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1532 +
1533 + if (!lp->tx_dma_regs) {
1534 + ERR("Can't remap Tx DMA registers\n");
1535 + retval = -ENXIO;
1536 + goto probe_err_out;
1537 + }
1538 +
1539 +#ifdef RC32434_PROC_DEBUG
1540 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1541 + rc32434_read_proc, dev);
1542 +#endif
1543 +
1544 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1545 + if (!lp->td_ring) {
1546 + ERR("Can't allocate descriptors\n");
1547 + retval = -ENOMEM;
1548 + goto probe_err_out;
1549 + }
1550 +
1551 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1552 +
1553 + /* now convert TD_RING pointer to KSEG1 */
1554 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1555 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1556 +
1557 +
1558 + spin_lock_init(&lp->lock);
1559 +
1560 + dev->base_addr = bif->iobase;
1561 + /* just use the rx dma irq */
1562 + dev->irq = bif->rx_dma_irq;
1563 +
1564 + dev->priv = lp;
1565 +
1566 + dev->open = rc32434_open;
1567 + dev->stop = rc32434_close;
1568 + dev->hard_start_xmit = rc32434_send_packet;
1569 + dev->get_stats = rc32434_get_stats;
1570 + dev->set_multicast_list = &rc32434_multicast_list;
1571 + dev->tx_timeout = rc32434_tx_timeout;
1572 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1573 +
1574 +#ifdef CONFIG_IDT_USE_NAPI
1575 + dev->poll = rc32434_poll;
1576 + dev->weight = bif->weight;
1577 + printk("Using NAPI with weight %d\n",dev->weight);
1578 +#else
1579 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1580 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1581 +#endif
1582 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1583 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1584 +
1585 + if ((err = register_netdev(dev))) {
1586 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1587 + free_netdev(dev);
1588 + retval = -EINVAL;
1589 + goto probe_err_out;
1590 + }
1591 +
1592 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1593 + for (i = 0; i < 6; i++) {
1594 + printk("%2.2x", dev->dev_addr[i]);
1595 + if (i<5)
1596 + printk(":");
1597 + }
1598 + printk("\n");
1599 +
1600 + return 0;
1601 +
1602 + probe_err_out:
1603 + rc32434_cleanup_module();
1604 + ERR(" failed. Returns %d\n", retval);
1605 + return retval;
1606 +
1607 +}
1608 +
1609 +
1610 +static void rc32434_cleanup_module(void)
1611 +{
1612 + int i;
1613 +
1614 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1615 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1616 + if (bif->dev != NULL) {
1617 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1618 + if (lp != NULL) {
1619 + if (lp->eth_regs)
1620 + iounmap((void*)lp->eth_regs);
1621 + if (lp->rx_dma_regs)
1622 + iounmap((void*)lp->rx_dma_regs);
1623 + if (lp->tx_dma_regs)
1624 + iounmap((void*)lp->tx_dma_regs);
1625 + if (lp->td_ring)
1626 + kfree((void*)KSEG0ADDR(lp->td_ring));
1627 +
1628 +#ifdef RC32434_PROC_DEBUG
1629 + if (lp->ps) {
1630 + remove_proc_entry(bif->name, proc_net);
1631 + }
1632 +#endif
1633 + kfree(lp);
1634 + }
1635 +
1636 + unregister_netdev(bif->dev);
1637 + free_netdev(bif->dev);
1638 + kfree(bif->dev);
1639 + }
1640 + }
1641 +}
1642 +
1643 +
1644 +
1645 +static int rc32434_open(struct net_device *dev)
1646 +{
1647 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1648 +
1649 + /* Initialize */
1650 + if (rc32434_init(dev)) {
1651 + ERR("Error: cannot open the Ethernet device\n");
1652 + return -EAGAIN;
1653 + }
1654 +
1655 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1656 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1657 + SA_SHIRQ | SA_INTERRUPT,
1658 + "rc32434 ethernet Rx", dev)) {
1659 + ERR(": unable to get Rx DMA IRQ %d\n",
1660 + lp->rx_irq);
1661 + return -EAGAIN;
1662 + }
1663 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1664 + SA_SHIRQ | SA_INTERRUPT,
1665 + "rc32434 ethernet Tx", dev)) {
1666 + ERR(": unable to get Tx DMA IRQ %d\n",
1667 + lp->tx_irq);
1668 + free_irq(lp->rx_irq, dev);
1669 + return -EAGAIN;
1670 + }
1671 +
1672 +#ifdef RC32434_REVISION
1673 + /* Install handler for overrun error. */
1674 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1675 + SA_SHIRQ | SA_INTERRUPT,
1676 + "Ethernet Overflow", dev)) {
1677 + ERR(": unable to get OVR IRQ %d\n",
1678 + lp->ovr_irq);
1679 + free_irq(lp->rx_irq, dev);
1680 + free_irq(lp->tx_irq, dev);
1681 + return -EAGAIN;
1682 + }
1683 +#endif
1684 +
1685 + /* Install handler for underflow error. */
1686 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1687 + SA_SHIRQ | SA_INTERRUPT,
1688 + "Ethernet Underflow", dev)) {
1689 + ERR(": unable to get UND IRQ %d\n",
1690 + lp->und_irq);
1691 + free_irq(lp->rx_irq, dev);
1692 + free_irq(lp->tx_irq, dev);
1693 +#ifdef RC32434_REVISION
1694 + free_irq(lp->ovr_irq, dev);
1695 +#endif
1696 + return -EAGAIN;
1697 + }
1698 +
1699 +
1700 + return 0;
1701 +}
1702 +
1703 +
1704 +
1705 +
1706 +static int rc32434_close(struct net_device *dev)
1707 +{
1708 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1709 + u32 tmp;
1710 +
1711 + /* Disable interrupts */
1712 + disable_irq(lp->rx_irq);
1713 + disable_irq(lp->tx_irq);
1714 +#ifdef RC32434_REVISION
1715 + disable_irq(lp->ovr_irq);
1716 +#endif
1717 + disable_irq(lp->und_irq);
1718 +
1719 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1720 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1721 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1722 +
1723 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1724 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1725 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1726 +
1727 + free_irq(lp->rx_irq, dev);
1728 + free_irq(lp->tx_irq, dev);
1729 +#ifdef RC32434_REVISION
1730 + free_irq(lp->ovr_irq, dev);
1731 +#endif
1732 + free_irq(lp->und_irq, dev);
1733 + return 0;
1734 +}
1735 +
1736 +
1737 +/* transmit packet */
1738 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1739 +{
1740 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1741 + unsigned long flags;
1742 + u32 length;
1743 + DMAD_t td;
1744 +
1745 +
1746 + spin_lock_irqsave(&lp->lock, flags);
1747 +
1748 + td = &lp->td_ring[lp->tx_chain_tail];
1749 +
1750 + /* stop queue when full, drop pkts if queue already full */
1751 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1752 + lp->tx_full = 1;
1753 +
1754 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1755 + netif_stop_queue(dev);
1756 + }
1757 + else {
1758 + lp->stats.tx_dropped++;
1759 + dev_kfree_skb_any(skb);
1760 + spin_unlock_irqrestore(&lp->lock, flags);
1761 + return 1;
1762 + }
1763 + }
1764 +
1765 + lp->tx_count ++;
1766 +
1767 + lp->tx_skb[lp->tx_chain_tail] = skb;
1768 +
1769 + length = skb->len;
1770 +
1771 + /* Setup the transmit descriptor. */
1772 + td->ca = CPHYSADDR(skb->data);
1773 +
1774 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1775 + if( lp->tx_chain_status == empty ) {
1776 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1777 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1778 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1779 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1780 + }
1781 + else {
1782 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1783 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1784 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1785 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1786 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1787 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1788 + lp->tx_chain_status = empty;
1789 + }
1790 + }
1791 + else {
1792 + if( lp->tx_chain_status == empty ) {
1793 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1794 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1795 + lp->tx_chain_status = filled;
1796 + }
1797 + else {
1798 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1799 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1800 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1801 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1802 + }
1803 + }
1804 +
1805 + dev->trans_start = jiffies;
1806 +
1807 + spin_unlock_irqrestore(&lp->lock, flags);
1808 +
1809 + return 0;
1810 +}
1811 +
1812 +
1813 +/* Ethernet MII-PHY Handler */
1814 +static void rc32434_mii_handler(unsigned long data)
1815 +{
1816 + struct net_device *dev = (struct net_device *)data;
1817 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1818 + unsigned long flags;
1819 + unsigned long duplex_status;
1820 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1821 +
1822 + spin_lock_irqsave(&lp->lock, flags);
1823 +
1824 + /* Two ports are using the same MII, the difference is the PHY address */
1825 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1826 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1827 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1828 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1829 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1830 +
1831 + ERR("irq:%x port_addr:%x RDD:%x\n",
1832 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1833 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1834 + if(duplex_status != lp->duplex_mode) {
1835 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1836 + lp->duplex_mode = duplex_status;
1837 + rc32434_restart(dev);
1838 + }
1839 +
1840 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1841 + add_timer(&lp->mii_phy_timer);
1842 +
1843 + spin_unlock_irqrestore(&lp->lock, flags);
1844 +
1845 +}
1846 +
1847 +#ifdef RC32434_REVISION
1848 +/* Ethernet Rx Overflow interrupt */
1849 +static irqreturn_t
1850 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1851 +{
1852 + struct net_device *dev = (struct net_device *)dev_id;
1853 + struct rc32434_local *lp;
1854 + unsigned int ovr;
1855 + irqreturn_t retval = IRQ_NONE;
1856 +
1857 + ASSERT(dev != NULL);
1858 +
1859 + lp = (struct rc32434_local *)dev->priv;
1860 + spin_lock(&lp->lock);
1861 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1862 +
1863 + if(ovr & ETHINTFC_ovr_m) {
1864 + netif_stop_queue(dev);
1865 +
1866 + /* clear OVR bit */
1867 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1868 +
1869 + /* Restart interface */
1870 + rc32434_restart(dev);
1871 + retval = IRQ_HANDLED;
1872 + }
1873 + spin_unlock(&lp->lock);
1874 +
1875 + return retval;
1876 +}
1877 +
1878 +#endif
1879 +
1880 +
1881 +/* Ethernet Tx Underflow interrupt */
1882 +static irqreturn_t
1883 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1884 +{
1885 + struct net_device *dev = (struct net_device *)dev_id;
1886 + struct rc32434_local *lp;
1887 + unsigned int und;
1888 + irqreturn_t retval = IRQ_NONE;
1889 +
1890 + ASSERT(dev != NULL);
1891 +
1892 + lp = (struct rc32434_local *)dev->priv;
1893 +
1894 + spin_lock(&lp->lock);
1895 +
1896 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1897 +
1898 + if(und & ETHINTFC_und_m) {
1899 + netif_stop_queue(dev);
1900 +
1901 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1902 +
1903 + /* Restart interface */
1904 + rc32434_restart(dev);
1905 + retval = IRQ_HANDLED;
1906 + }
1907 +
1908 + spin_unlock(&lp->lock);
1909 +
1910 + return retval;
1911 +}
1912 +
1913 +
1914 +/* Ethernet Rx DMA interrupt */
1915 +static irqreturn_t
1916 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1917 +{
1918 + struct net_device *dev = (struct net_device *)dev_id;
1919 + struct rc32434_local* lp;
1920 + volatile u32 dmas,dmasm;
1921 + irqreturn_t retval;
1922 +
1923 + ASSERT(dev != NULL);
1924 +
1925 + lp = (struct rc32434_local *)dev->priv;
1926 +
1927 + spin_lock(&lp->lock);
1928 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1929 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1930 + /* Mask D H E bit in Rx DMA */
1931 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1932 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1933 +#ifdef CONFIG_IDT_USE_NAPI
1934 + if(netif_rx_schedule_prep(dev))
1935 + __netif_rx_schedule(dev);
1936 +#else
1937 + tasklet_hi_schedule(lp->rx_tasklet);
1938 +#endif
1939 +
1940 + if (dmas & DMAS_e_m)
1941 + ERR(": DMA error\n");
1942 +
1943 + retval = IRQ_HANDLED;
1944 + }
1945 + else
1946 + retval = IRQ_NONE;
1947 +
1948 + spin_unlock(&lp->lock);
1949 + return retval;
1950 +}
1951 +
1952 +#ifdef CONFIG_IDT_USE_NAPI
1953 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1954 +#else
1955 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1956 +#endif
1957 +{
1958 + struct net_device *dev = (struct net_device *)rx_data_dev;
1959 + struct rc32434_local* lp = netdev_priv(dev);
1960 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1961 + struct sk_buff *skb, *skb_new;
1962 + u8* pkt_buf;
1963 + u32 devcs, count, pkt_len, pktuncrc_len;
1964 + volatile u32 dmas;
1965 +#ifdef CONFIG_IDT_USE_NAPI
1966 + u32 received = 0;
1967 + int rx_work_limit = min(*budget,dev->quota);
1968 +#else
1969 + unsigned long flags;
1970 + spin_lock_irqsave(&lp->lock, flags);
1971 +#endif
1972 +
1973 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1974 +#ifdef CONFIG_IDT_USE_NAPI
1975 + if(--rx_work_limit <0)
1976 + {
1977 + break;
1978 + }
1979 +#endif
1980 + /* init the var. used for the later operations within the while loop */
1981 + skb_new = NULL;
1982 + devcs = rd->devcs;
1983 + pkt_len = RCVPKT_LENGTH(devcs);
1984 + skb = lp->rx_skb[lp->rx_next_done];
1985 +
1986 + if (count < 64) {
1987 + lp->stats.rx_errors++;
1988 + lp->stats.rx_dropped++;
1989 + }
1990 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1991 + /* check that this is a whole packet */
1992 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1993 + lp->stats.rx_errors++;
1994 + lp->stats.rx_dropped++;
1995 + }
1996 + else if ( (devcs & ETHRX_rok_m) ) {
1997 +
1998 + {
1999 + /* must be the (first and) last descriptor then */
2000 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2001 +
2002 + pktuncrc_len = pkt_len - 4;
2003 + /* invalidate the cache */
2004 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2005 +
2006 + /* Malloc up new buffer. */
2007 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2008 +
2009 + if (skb_new != NULL){
2010 + /* Make room */
2011 + skb_put(skb, pktuncrc_len);
2012 +
2013 + skb->protocol = eth_type_trans(skb, dev);
2014 +
2015 + /* pass the packet to upper layers */
2016 +#ifdef CONFIG_IDT_USE_NAPI
2017 + netif_receive_skb(skb);
2018 +#else
2019 + netif_rx(skb);
2020 +#endif
2021 +
2022 + dev->last_rx = jiffies;
2023 + lp->stats.rx_packets++;
2024 + lp->stats.rx_bytes += pktuncrc_len;
2025 +
2026 + if (IS_RCV_MP(devcs))
2027 + lp->stats.multicast++;
2028 +
2029 + /* 16 bit align */
2030 + skb_reserve(skb_new, 2);
2031 +
2032 + skb_new->dev = dev;
2033 + lp->rx_skb[lp->rx_next_done] = skb_new;
2034 + }
2035 + else {
2036 + ERR("no memory, dropping rx packet.\n");
2037 + lp->stats.rx_errors++;
2038 + lp->stats.rx_dropped++;
2039 + }
2040 + }
2041 +
2042 + }
2043 + else {
2044 + /* This should only happen if we enable accepting broken packets */
2045 + lp->stats.rx_errors++;
2046 + lp->stats.rx_dropped++;
2047 +
2048 + /* add statistics counters */
2049 + if (IS_RCV_CRC_ERR(devcs)) {
2050 + DBG(2, "RX CRC error\n");
2051 + lp->stats.rx_crc_errors++;
2052 + }
2053 + else if (IS_RCV_LOR_ERR(devcs)) {
2054 + DBG(2, "RX LOR error\n");
2055 + lp->stats.rx_length_errors++;
2056 + }
2057 + else if (IS_RCV_LE_ERR(devcs)) {
2058 + DBG(2, "RX LE error\n");
2059 + lp->stats.rx_length_errors++;
2060 + }
2061 + else if (IS_RCV_OVR_ERR(devcs)) {
2062 + lp->stats.rx_over_errors++;
2063 + }
2064 + else if (IS_RCV_CV_ERR(devcs)) {
2065 + /* code violation */
2066 + DBG(2, "RX CV error\n");
2067 + lp->stats.rx_frame_errors++;
2068 + }
2069 + else if (IS_RCV_CES_ERR(devcs)) {
2070 + DBG(2, "RX Preamble error\n");
2071 + }
2072 + }
2073 +
2074 + rd->devcs = 0;
2075 +
2076 + /* restore descriptor's curr_addr */
2077 + if(skb_new)
2078 + rd->ca = CPHYSADDR(skb_new->data);
2079 + else
2080 + rd->ca = CPHYSADDR(skb->data);
2081 +
2082 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2083 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2084 +
2085 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2086 + rd = &lp->rd_ring[lp->rx_next_done];
2087 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2088 + }
2089 +#ifdef CONFIG_IDT_USE_NAPI
2090 + dev->quota -= received;
2091 + *budget =- received;
2092 + if(rx_work_limit < 0)
2093 + goto not_done;
2094 +#endif
2095 +
2096 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2097 +
2098 + if(dmas & DMAS_h_m) {
2099 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2100 +#ifdef RC32434_PROC_DEBUG
2101 + lp->dma_halt_cnt++;
2102 +#endif
2103 + rd->devcs = 0;
2104 + skb = lp->rx_skb[lp->rx_next_done];
2105 + rd->ca = CPHYSADDR(skb->data);
2106 + rc32434_chain_rx(lp,rd);
2107 + }
2108 +
2109 +#ifdef CONFIG_IDT_USE_NAPI
2110 + netif_rx_complete(dev);
2111 +#endif
2112 + /* Enable D H E bit in Rx DMA */
2113 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2114 +#ifdef CONFIG_IDT_USE_NAPI
2115 + return 0;
2116 + not_done:
2117 + return 1;
2118 +#else
2119 + spin_unlock_irqrestore(&lp->lock, flags);
2120 + return;
2121 +#endif
2122 +
2123 +
2124 +}
2125 +
2126 +
2127 +
2128 +/* Ethernet Tx DMA interrupt */
2129 +static irqreturn_t
2130 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2131 +{
2132 + struct net_device *dev = (struct net_device *)dev_id;
2133 + struct rc32434_local *lp;
2134 + volatile u32 dmas,dmasm;
2135 + irqreturn_t retval;
2136 +
2137 + ASSERT(dev != NULL);
2138 +
2139 + lp = (struct rc32434_local *)dev->priv;
2140 +
2141 + spin_lock(&lp->lock);
2142 +
2143 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2144 +
2145 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2146 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2147 + /* Mask F E bit in Tx DMA */
2148 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2149 +
2150 + tasklet_hi_schedule(lp->tx_tasklet);
2151 +
2152 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2153 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2154 + lp->tx_chain_status = empty;
2155 + lp->tx_chain_head = lp->tx_chain_tail;
2156 + dev->trans_start = jiffies;
2157 + }
2158 +
2159 + if (dmas & DMAS_e_m)
2160 + ERR(": DMA error\n");
2161 +
2162 + retval = IRQ_HANDLED;
2163 + }
2164 + else
2165 + retval = IRQ_NONE;
2166 +
2167 + spin_unlock(&lp->lock);
2168 +
2169 + return retval;
2170 +}
2171 +
2172 +
2173 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2174 +{
2175 + struct net_device *dev = (struct net_device *)tx_data_dev;
2176 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2177 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2178 + u32 devcs;
2179 + unsigned long flags;
2180 + volatile u32 dmas;
2181 +
2182 + spin_lock_irqsave(&lp->lock, flags);
2183 +
2184 + /* process all desc that are done */
2185 + while(IS_DMA_FINISHED(td->control)) {
2186 + if(lp->tx_full == 1) {
2187 + netif_wake_queue(dev);
2188 + lp->tx_full = 0;
2189 + }
2190 +
2191 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2192 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2193 + lp->stats.tx_errors++;
2194 + lp->stats.tx_dropped++;
2195 +
2196 + /* should never happen */
2197 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2198 + }
2199 + else if (IS_TX_TOK(devcs)) {
2200 + lp->stats.tx_packets++;
2201 + }
2202 + else {
2203 + lp->stats.tx_errors++;
2204 + lp->stats.tx_dropped++;
2205 +
2206 + /* underflow */
2207 + if (IS_TX_UND_ERR(devcs))
2208 + lp->stats.tx_fifo_errors++;
2209 +
2210 + /* oversized frame */
2211 + if (IS_TX_OF_ERR(devcs))
2212 + lp->stats.tx_aborted_errors++;
2213 +
2214 + /* excessive deferrals */
2215 + if (IS_TX_ED_ERR(devcs))
2216 + lp->stats.tx_carrier_errors++;
2217 +
2218 + /* collisions: medium busy */
2219 + if (IS_TX_EC_ERR(devcs))
2220 + lp->stats.collisions++;
2221 +
2222 + /* late collision */
2223 + if (IS_TX_LC_ERR(devcs))
2224 + lp->stats.tx_window_errors++;
2225 +
2226 + }
2227 +
2228 + /* We must always free the original skb */
2229 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2230 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2231 + lp->tx_skb[lp->tx_next_done] = NULL;
2232 + }
2233 +
2234 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2235 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2236 + lp->td_ring[lp->tx_next_done].link = 0;
2237 + lp->td_ring[lp->tx_next_done].ca = 0;
2238 + lp->tx_count --;
2239 +
2240 + /* go on to next transmission */
2241 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2242 + td = &lp->td_ring[lp->tx_next_done];
2243 +
2244 + }
2245 +
2246 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2247 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2248 +
2249 + /* Enable F E bit in Tx DMA */
2250 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2251 + spin_unlock_irqrestore(&lp->lock, flags);
2252 +
2253 +}
2254 +
2255 +
2256 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2257 +{
2258 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2259 + return &lp->stats;
2260 +}
2261 +
2262 +
2263 +/*
2264 + * Set or clear the multicast filter for this adaptor.
2265 + */
2266 +static void rc32434_multicast_list(struct net_device *dev)
2267 +{
2268 + /* listen to broadcasts always and to treat */
2269 + /* IFF bits independantly */
2270 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2271 + unsigned long flags;
2272 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2273 +
2274 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2275 + recognise |= ETHARC_pro_m;
2276 +
2277 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2278 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2279 + else if (dev->mc_count > 0) {
2280 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2281 + recognise |= ETHARC_am_m; /* for the time being */
2282 + }
2283 +
2284 + spin_lock_irqsave(&lp->lock, flags);
2285 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2286 + spin_unlock_irqrestore(&lp->lock, flags);
2287 +}
2288 +
2289 +
2290 +static void rc32434_tx_timeout(struct net_device *dev)
2291 +{
2292 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2293 + unsigned long flags;
2294 +
2295 + spin_lock_irqsave(&lp->lock, flags);
2296 + rc32434_restart(dev);
2297 + spin_unlock_irqrestore(&lp->lock, flags);
2298 +
2299 +}
2300 +
2301 +
2302 +/*
2303 + * Initialize the RC32434 ethernet controller.
2304 + */
2305 +static int rc32434_init(struct net_device *dev)
2306 +{
2307 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2308 + int i, j;
2309 +
2310 + /* Disable DMA */
2311 + rc32434_abort_tx(dev);
2312 + rc32434_abort_rx(dev);
2313 +
2314 + /* reset ethernet logic */
2315 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2316 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2317 + dev->trans_start = jiffies;
2318 +
2319 + /* Enable Ethernet Interface */
2320 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2321 +
2322 +#ifndef CONFIG_IDT_USE_NAPI
2323 + tasklet_disable(lp->rx_tasklet);
2324 +#endif
2325 + tasklet_disable(lp->tx_tasklet);
2326 +
2327 + /* Initialize the transmit Descriptors */
2328 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2329 + lp->td_ring[i].control = DMAD_iof_m;
2330 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2331 + lp->td_ring[i].ca = 0;
2332 + lp->td_ring[i].link = 0;
2333 + if (lp->tx_skb[i] != NULL) {
2334 + dev_kfree_skb_any(lp->tx_skb[i]);
2335 + lp->tx_skb[i] = NULL;
2336 + }
2337 + }
2338 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2339 + lp-> tx_chain_status = empty;
2340 +
2341 + /*
2342 + * Initialize the receive descriptors so that they
2343 + * become a circular linked list, ie. let the last
2344 + * descriptor point to the first again.
2345 + */
2346 + for (i=0; i<RC32434_NUM_RDS; i++) {
2347 + struct sk_buff *skb = lp->rx_skb[i];
2348 +
2349 + if (lp->rx_skb[i] == NULL) {
2350 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2351 + if (skb == NULL) {
2352 + ERR("No memory in the system\n");
2353 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2354 + if (lp->rx_skb[j] != NULL)
2355 + dev_kfree_skb_any(lp->rx_skb[j]);
2356 +
2357 + return 1;
2358 + }
2359 + else {
2360 + skb->dev = dev;
2361 + skb_reserve(skb, 2);
2362 + lp->rx_skb[i] = skb;
2363 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2364 +
2365 + }
2366 + }
2367 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2368 + lp->rd_ring[i].devcs = 0;
2369 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2370 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2371 +
2372 + }
2373 + /* loop back */
2374 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2375 + lp->rx_next_done = 0;
2376 +
2377 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2378 + lp->rx_chain_head = 0;
2379 + lp->rx_chain_tail = 0;
2380 + lp->rx_chain_status = empty;
2381 +
2382 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2383 + /* Start Rx DMA */
2384 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2385 +
2386 + /* Enable F E bit in Tx DMA */
2387 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2388 + /* Enable D H E bit in Rx DMA */
2389 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2390 +
2391 + /* Accept only packets destined for this Ethernet device address */
2392 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2393 +
2394 + /* Set all Ether station address registers to their initial values */
2395 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2396 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2397 +
2398 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2399 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2400 +
2401 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2402 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2403 +
2404 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2405 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2406 +
2407 +
2408 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2409 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2410 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2411 +
2412 + /* Back to back inter-packet-gap */
2413 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2414 + /* Non - Back to back inter-packet-gap */
2415 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2416 +
2417 + /* Management Clock Prescaler Divisor */
2418 + /* Clock independent setting */
2419 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2420 + &lp->eth_regs->ethmcp);
2421 +
2422 + /* don't transmit until fifo contains 48b */
2423 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2424 +
2425 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2426 +
2427 +#ifndef CONFIG_IDT_USE_NAPI
2428 + tasklet_enable(lp->rx_tasklet);
2429 +#endif
2430 + tasklet_enable(lp->tx_tasklet);
2431 +
2432 + netif_start_queue(dev);
2433 +
2434 +
2435 + return 0;
2436 +
2437 +}
2438 +
2439 +
2440 +#ifndef MODULE
2441 +
2442 +static int __init rc32434_setup(char *options)
2443 +{
2444 + /* no options yet */
2445 + return 1;
2446 +}
2447 +
2448 +static int __init rc32434_setup_ethaddr0(char *options)
2449 +{
2450 + memcpy(mac0, options, 17);
2451 + mac0[17]= '\0';
2452 + return 1;
2453 +}
2454 +
2455 +__setup("rc32434eth=", rc32434_setup);
2456 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2457 +
2458 +
2459 +#endif /* MODULE */
2460 +
2461 +module_init(rc32434_init_module);
2462 +module_exit(rc32434_cleanup_module);
2463 +
2464 +
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 +
2473 +
2474 +
2475 +
2476 +
2477 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2478 --- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2479 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2480 @@ -0,0 +1,187 @@
2481 +/**************************************************************************
2482 + *
2483 + * BRIEF MODULE DESCRIPTION
2484 + * Definitions for IDT RC32434 on-chip ethernet controller.
2485 + *
2486 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2487 + *
2488 + * This program is free software; you can redistribute it and/or modify it
2489 + * under the terms of the GNU General Public License as published by the
2490 + * Free Software Foundation; either version 2 of the License, or (at your
2491 + * option) any later version.
2492 + *
2493 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2494 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2495 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2496 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2497 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2498 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2499 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2500 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2501 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2502 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2503 + *
2504 + * You should have received a copy of the GNU General Public License along
2505 + * with this program; if not, write to the Free Software Foundation, Inc.,
2506 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2507 + *
2508 + *
2509 + **************************************************************************
2510 + * May 2004 rkt, neb
2511 + *
2512 + * Initial Release
2513 + *
2514 + * Aug 2004
2515 + *
2516 + * Added NAPI
2517 + *
2518 + **************************************************************************
2519 + */
2520 +
2521 +
2522 +#include <asm/idt-boards/rc32434/rc32434.h>
2523 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2524 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2525 +
2526 +#define RC32434_DEBUG 2
2527 +//#define RC32434_PROC_DEBUG
2528 +#undef RC32434_DEBUG
2529 +
2530 +#ifdef RC32434_DEBUG
2531 +
2532 +/* use 0 for production, 1 for verification, >2 for debug */
2533 +static int rc32434_debug = RC32434_DEBUG;
2534 +#define ASSERT(expr) \
2535 + if(!(expr)) { \
2536 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2537 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2538 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2539 +#else
2540 +#define ASSERT(expr) do {} while (0)
2541 +#define DBG(lvl, format, arg...) do {} while (0)
2542 +#endif
2543 +
2544 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2545 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2546 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2547 +
2548 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2549 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2550 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2551 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2552 +
2553 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2554 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2555 +
2556 +/* the following must be powers of two */
2557 +#ifdef CONFIG_IDT_USE_NAPI
2558 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2559 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2560 +#else
2561 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2562 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2563 +#endif
2564 +
2565 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2566 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2567 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2568 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2569 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2570 +
2571 +#define RC32434_TX_TIMEOUT HZ * 100
2572 +
2573 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2574 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2575 +
2576 +enum status { filled, empty};
2577 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2578 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2579 +
2580 +
2581 +/* Information that need to be kept for each board. */
2582 +struct rc32434_local {
2583 + ETH_t eth_regs;
2584 + DMA_Chan_t rx_dma_regs;
2585 + DMA_Chan_t tx_dma_regs;
2586 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2587 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2588 +
2589 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2590 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2591 +
2592 +#ifndef CONFIG_IDT_USE_NAPI
2593 + struct tasklet_struct * rx_tasklet;
2594 +#endif
2595 + struct tasklet_struct * tx_tasklet;
2596 +
2597 + int rx_next_done;
2598 + int rx_chain_head;
2599 + int rx_chain_tail;
2600 + enum status rx_chain_status;
2601 +
2602 + int tx_next_done;
2603 + int tx_chain_head;
2604 + int tx_chain_tail;
2605 + enum status tx_chain_status;
2606 + int tx_count;
2607 + int tx_full;
2608 +
2609 + struct timer_list mii_phy_timer;
2610 + unsigned long duplex_mode;
2611 +
2612 + int rx_irq;
2613 + int tx_irq;
2614 + int ovr_irq;
2615 + int und_irq;
2616 +
2617 + struct net_device_stats stats;
2618 + spinlock_t lock;
2619 +
2620 + /* debug /proc entry */
2621 + struct proc_dir_entry *ps;
2622 + int dma_halt_cnt; int dma_run_cnt;
2623 +};
2624 +
2625 +extern unsigned int idt_cpu_freq;
2626 +
2627 +/* Index to functions, as function prototypes. */
2628 +static int rc32434_open(struct net_device *dev);
2629 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2630 +static void rc32434_mii_handler(unsigned long data);
2631 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2632 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2633 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2634 +#ifdef RC32434_REVISION
2635 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2636 +#endif
2637 +static int rc32434_close(struct net_device *dev);
2638 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2639 +static void rc32434_multicast_list(struct net_device *dev);
2640 +static int rc32434_init(struct net_device *dev);
2641 +static void rc32434_tx_timeout(struct net_device *dev);
2642 +
2643 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2644 +#ifdef CONFIG_IDT_USE_NAPI
2645 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2646 +#else
2647 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2648 +#endif
2649 +static void rc32434_cleanup_module(void);
2650 +static int rc32434_probe(int port_num);
2651 +int rc32434_init_module(void);
2652 +
2653 +
2654 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2655 +{
2656 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2657 + rc32434_writel(0x10, &ch->dmac);
2658 +
2659 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2660 + dev->trans_start = jiffies;
2661 +
2662 + rc32434_writel(0, &ch->dmas);
2663 + }
2664 +
2665 + rc32434_writel(0, &ch->dmadptr);
2666 + rc32434_writel(0, &ch->dmandptr);
2667 +}
2668 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2669 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
2670 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
2671 @@ -218,6 +218,17 @@
2672 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2673 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2674
2675 +
2676 +/*
2677 + * Valid machtype for group ARUBA
2678 + */
2679 +#define MACH_GROUP_ARUBA 23
2680 +#define MACH_ARUBA_UNKNOWN 0
2681 +#define MACH_ARUBA_AP60 1
2682 +#define MACH_ARUBA_AP65 2
2683 +#define MACH_ARUBA_AP70 3
2684 +#define MACH_ARUBA_AP40 4
2685 +
2686 #define CL_SIZE COMMAND_LINE_SIZE
2687
2688 const char *get_system_type(void);
2689 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2690 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2691 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
2692 @@ -54,6 +54,9 @@
2693 #define PRID_IMP_R14000 0x0f00
2694 #define PRID_IMP_R8000 0x1000
2695 #define PRID_IMP_PR4450 0x1200
2696 +#define PRID_IMP_RC32334 0x1800
2697 +#define PRID_IMP_RC32355 0x1900
2698 +#define PRID_IMP_RC32365 0x1900
2699 #define PRID_IMP_R4600 0x2000
2700 #define PRID_IMP_R4700 0x2100
2701 #define PRID_IMP_TX39 0x2200
2702 @@ -200,7 +203,8 @@
2703 #define CPU_SB1A 62
2704 #define CPU_74K 63
2705 #define CPU_R14000 64
2706 -#define CPU_LAST 64
2707 +#define CPU_RC32300 65
2708 +#define CPU_LAST 65
2709
2710 /*
2711 * ISA Level encodings
2712 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2713 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2714 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
2715 @@ -0,0 +1,142 @@
2716 +/**************************************************************************
2717 + *
2718 + * BRIEF MODULE DESCRIPTION
2719 + * RC32300 helper routines
2720 + *
2721 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2722 + *
2723 + * This program is free software; you can redistribute it and/or modify it
2724 + * under the terms of the GNU General Public License as published by the
2725 + * Free Software Foundation; either version 2 of the License, or (at your
2726 + * option) any later version.
2727 + *
2728 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2729 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2730 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2731 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2732 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2733 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2734 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2735 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2736 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2737 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2738 + *
2739 + * You should have received a copy of the GNU General Public License along
2740 + * with this program; if not, write to the Free Software Foundation, Inc.,
2741 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2742 + *
2743 + *
2744 + **************************************************************************
2745 + * May 2004 P. Sadik.
2746 + *
2747 + * Initial Release
2748 + *
2749 + *
2750 + *
2751 + **************************************************************************
2752 + */
2753 +
2754 +#ifndef __IDT_RC32300_H__
2755 +#define __IDT_RC32300_H__
2756 +
2757 +#include <linux/delay.h>
2758 +#include <asm/io.h>
2759 +
2760 +
2761 +/* cpu pipeline flush */
2762 +static inline void rc32300_sync(void)
2763 +{
2764 + __asm__ volatile ("sync");
2765 +}
2766 +
2767 +static inline void rc32300_sync_udelay(int us)
2768 +{
2769 + __asm__ volatile ("sync");
2770 + udelay(us);
2771 +}
2772 +
2773 +static inline void rc32300_sync_delay(int ms)
2774 +{
2775 + __asm__ volatile ("sync");
2776 + mdelay(ms);
2777 +}
2778 +
2779 +/*
2780 + * Macros to access internal RC32300 registers. No byte
2781 + * swapping should be done when accessing the internal
2782 + * registers.
2783 + */
2784 +
2785 +static inline u8 rc32300_readb(unsigned long pa)
2786 +{
2787 + return *((volatile u8 *)KSEG1ADDR(pa));
2788 +}
2789 +static inline u16 rc32300_readw(unsigned long pa)
2790 +{
2791 + return *((volatile u16 *)KSEG1ADDR(pa));
2792 +}
2793 +static inline u32 rc32300_readl(unsigned long pa)
2794 +{
2795 + return *((volatile u32 *)KSEG1ADDR(pa));
2796 +}
2797 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2798 +{
2799 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2800 +}
2801 +static inline void rc32300_writew(u16 val, unsigned long pa)
2802 +{
2803 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2804 +}
2805 +static inline void rc32300_writel(u32 val, unsigned long pa)
2806 +{
2807 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2808 +}
2809 +
2810 +
2811 +#define local_readb __raw_readb
2812 +#define local_readw __raw_readw
2813 +#define local_readl __raw_readl
2814 +
2815 +#define local_writeb __raw_writeb
2816 +#define local_writew __raw_writew
2817 +#define local_writel __raw_writel
2818 +
2819 +
2820 +/*
2821 + * C access to CLZ and CLO instructions
2822 + * (count leading zeroes/ones).
2823 + */
2824 +static inline int rc32300_clz(unsigned long val)
2825 +{
2826 + int ret;
2827 + __asm__ volatile (
2828 + ".set\tnoreorder\n\t"
2829 + ".set\tnoat\n\t"
2830 + ".set\tmips32\n\t"
2831 + "clz\t%0,%1\n\t"
2832 + ".set\tmips0\n\t"
2833 + ".set\tat\n\t"
2834 + ".set\treorder"
2835 + : "=r" (ret)
2836 + : "r" (val));
2837 +
2838 + return ret;
2839 +}
2840 +static inline int rc32300_clo(unsigned long val)
2841 +{
2842 + int ret;
2843 + __asm__ volatile (
2844 + ".set\tnoreorder\n\t"
2845 + ".set\tnoat\n\t"
2846 + ".set\tmips32\n\t"
2847 + "clo\t%0,%1\n\t"
2848 + ".set\tmips0\n\t"
2849 + ".set\tat\n\t"
2850 + ".set\treorder"
2851 + : "=r" (ret)
2852 + : "r" (val));
2853 +
2854 + return ret;
2855 +}
2856 +
2857 +#endif // __IDT_RC32300_H__
2858 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2859 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2860 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
2861 @@ -0,0 +1,207 @@
2862 +/**************************************************************************
2863 + *
2864 + * BRIEF MODULE DESCRIPTION
2865 + * Definitions for IDT RC32334 CPU.
2866 + *
2867 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2868 + *
2869 + * This program is free software; you can redistribute it and/or modify it
2870 + * under the terms of the GNU General Public License as published by the
2871 + * Free Software Foundation; either version 2 of the License, or (at your
2872 + * option) any later version.
2873 + *
2874 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2875 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2876 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2877 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2878 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2879 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2880 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2881 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2882 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2883 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2884 + *
2885 + * You should have received a copy of the GNU General Public License along
2886 + * with this program; if not, write to the Free Software Foundation, Inc.,
2887 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2888 + *
2889 + *
2890 + **************************************************************************
2891 + * May 2004 P. Sadik.
2892 + *
2893 + * Initial Release
2894 + *
2895 + *
2896 + *
2897 + **************************************************************************
2898 + */
2899 +
2900 +
2901 +#ifndef __IDT_RC32334_H__
2902 +#define __IDT_RC32334_H__
2903 +
2904 +#include <linux/delay.h>
2905 +#include <asm/io.h>
2906 +
2907 +/* Base address of internal registers */
2908 +#define RC32334_REG_BASE 0x18000000
2909 +
2910 +/* CPU and IP Bus Control */
2911 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2912 +#define CPU_BTA 0xffffe204 // virtual!
2913 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2914 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2915 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2916 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2917 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2918 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2919 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2920 +
2921 +/* Memory Controller */
2922 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2923 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2924 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2925 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2926 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2927 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2928 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2929 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2930 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2931 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2932 +
2933 +/* PCI Controller */
2934 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2935 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2936 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2937 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2938 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2939 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2940 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2941 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2942 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2943 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2944 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2945 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2946 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2947 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2948 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2949 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2950 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2951 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2952 +
2953 +/* Timers */
2954 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2955 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2956 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2957 +#define TIMER_REG_OFFSET 0x10
2958 +
2959 +/* Programmable I/O */
2960 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2961 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2962 +
2963 +/*
2964 + * DMA
2965 + *
2966 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2967 + *
2968 + * DMA0: 18001400
2969 + * DMA1: 18001440
2970 + * DMA2: 18001900
2971 + * DMA3: 18001940
2972 + * NB: dma number must be immediate value or variable.
2973 + * It MUST NOT be a function since it would get called twice!
2974 + */
2975 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2976 +
2977 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2978 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2979 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2980 +
2981 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2982 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2983 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2984 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2985 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2986 +
2987 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2988 +
2989 +/* Expansion Interrupt Controller */
2990 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2991 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2992 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2993 +#define IC_GROUP_OFFSET 0x10
2994 +
2995 +#define NUM_INTR_GROUPS 15
2996 +/*
2997 + * The IRQ mapping is as follows:
2998 + *
2999 + * IRQ Mapped To
3000 + * --- -------------------
3001 + * 0 SW0 (IP0) SW0 intr
3002 + * 1 SW1 (IP1) SW1 intr
3003 + * 2 Int0 (IP2) board-specific
3004 + * 3 Int1 (IP3) board-specific
3005 + * 4 Int2 (IP4) board-specific
3006 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3007 + * 6 Int4 (IP6) board-specific
3008 + * 7 Int5 (IP7) CP0 Timer
3009 + *
3010 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3011 + * internally on the RC32334 is routed to the Expansion
3012 + * Interrupt Controller.
3013 + */
3014 +#define MIPS_CPU_TIMER_IRQ 7
3015 +
3016 +#define GROUP1_IRQ_BASE 8 // bus error
3017 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3018 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3019 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3020 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3021 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3022 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3023 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3024 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3025 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3026 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3027 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3028 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3029 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3030 +
3031 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3032 +
3033 +/* 16550 UARTs */
3034 +#ifdef __MIPSEB__
3035 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3036 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3037 +#else
3038 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3039 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3040 +#endif
3041 +
3042 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3043 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3044 +
3045 +#define IDT_CLOCK_MULT 2
3046 +
3047 +/* NVRAM */
3048 +#define NVRAM_BASE 0x12000000
3049 +#define NVRAM_ENVSIZE_OFF 4
3050 +#define NVRAM_ENVSTART_OFF 0x40
3051 +
3052 +/* LCD 4-digit display */
3053 +#define LCD_CLEAR 0x14000400
3054 +#define LCD_DIGIT0 0x1400000f
3055 +#define LCD_DIGIT1 0x14000008
3056 +#define LCD_DIGIT2 0x14000007
3057 +#define LCD_DIGIT3 0x14000003
3058 +
3059 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3060 +#define RC32334_SCC8530_IRQ 2
3061 +#define RC32334_PCI_INTA_IRQ 3
3062 +#define RC32334_PCI_INTB_IRQ 4
3063 +#define RC32334_PCI_INTC_IRQ 6
3064 +#define RC32334_PCI_INTD_IRQ 7
3065 +
3066 +#define RAM_SIZE (32*1024*1024)
3067 +
3068 +#endif // __IDT_RC32334_H__
3069 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3070 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3071 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3072 @@ -0,0 +1,206 @@
3073 +/**************************************************************************
3074 + *
3075 + * BRIEF MODULE DESCRIPTION
3076 + * DMA controller defines on IDT RC32355
3077 + *
3078 + * Copyright 2004 IDT Inc.
3079 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3080 + *
3081 + *
3082 + * This program is free software; you can redistribute it and/or modify it
3083 + * under the terms of the GNU General Public License as published by the
3084 + * Free Software Foundation; either version 2 of the License, or (at your
3085 + * option) any later version.
3086 + *
3087 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3088 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3089 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3090 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3091 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3092 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3093 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3094 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3095 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3096 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3097 + *
3098 + * You should have received a copy of the GNU General Public License along
3099 + * with this program; if not, write to the Free Software Foundation, Inc.,
3100 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3101 + *
3102 + *
3103 + * May 2004 rkt
3104 + * Initial Release
3105 + *
3106 + **************************************************************************
3107 + */
3108 +
3109 +#ifndef BANYAN_DMA_H
3110 +#define BANYAN_DMA_H
3111 +#include <asm/idt-boards/rc32300/rc32300.h>
3112 +
3113 +/*
3114 + * An image of one RC32355 dma channel registers
3115 + */
3116 +typedef struct {
3117 + u32 dmac;
3118 + u32 dmas;
3119 + u32 dmasm;
3120 + u32 dmadptr;
3121 + u32 dmandptr;
3122 +} rc32355_dma_ch_t;
3123 +
3124 +/*
3125 + * An image of all RC32355 dma channel registers
3126 + */
3127 +typedef struct {
3128 + rc32355_dma_ch_t ch[16];
3129 +} rc32355_dma_regs_t;
3130 +
3131 +
3132 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3133 +
3134 +
3135 +/* DMAC register layout */
3136 +
3137 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3138 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3139 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3140 +
3141 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3142 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3143 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3144 +
3145 +/* DMAS and DMASM register layout */
3146 +
3147 +#define DMAS_F 0x01 /* Finished */
3148 +#define DMAS_D 0x02 /* Done */
3149 +#define DMAS_C 0x04 /* Chain */
3150 +#define DMAS_E 0x08 /* Error */
3151 +#define DMAS_H 0x10 /* Halt */
3152 +
3153 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3154 +#define DMA_HALT_TIMEOUT 500
3155 +
3156 +
3157 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3158 +{
3159 + int timeout=1;
3160 +
3161 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3162 + local_writel(0, &ch->dmac);
3163 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3164 + if (local_readl(&ch->dmas) & DMAS_H) {
3165 + local_writel(0, &ch->dmas);
3166 + break;
3167 + }
3168 + }
3169 + }
3170 +
3171 + return timeout ? 0 : 1;
3172 +}
3173 +
3174 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3175 +{
3176 + local_writel(0, &ch->dmandptr);
3177 + local_writel(dma_addr, &ch->dmadptr);
3178 +}
3179 +
3180 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3181 +{
3182 + local_writel(dma_addr, &ch->dmandptr);
3183 +}
3184 +
3185 +
3186 +/* The following can be used to describe DMA channels 0 to 15, and the */
3187 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3188 +
3189 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3190 +
3191 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3192 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3193 +
3194 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3195 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3196 +
3197 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3198 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3199 +
3200 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3201 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3202 +
3203 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3204 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3205 +#define DMA_DEV_ATMVCC(entry) 0
3206 +
3207 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3208 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3209 +
3210 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3211 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3212 +
3213 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3214 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3215 +
3216 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3217 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3218 +
3219 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3220 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3221 +
3222 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3223 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3224 +
3225 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3226 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3227 +
3228 +#define DMA_CHAN_USBIN 13 /* USB input */
3229 +#define DMA_DEV_USBIN 0 /* USB input */
3230 +
3231 +#define DMA_CHAN_USBOUT 14 /* USB output */
3232 +#define DMA_DEV_USBOUT 0 /* USB output */
3233 +
3234 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3235 +#define DMA_DEV_EXTERN 0 /* External DMA */
3236 +
3237 +/*
3238 + * An RC32355 dma descriptor in system memory
3239 + */
3240 +typedef struct {
3241 + u32 cmdstat; /* control and status */
3242 + u32 curr_addr; /* current address of data */
3243 + u32 devcs; /* peripheral-specific control and status */
3244 + u32 link; /* link to next descriptor */
3245 +} rc32355_dma_desc_t;
3246 +
3247 +/* Values for the descriptor cmdstat word */
3248 +
3249 +#define DMADESC_F 0x80000000u /* Finished bit */
3250 +#define DMADESC_D 0x40000000u /* Done bit */
3251 +#define DMADESC_T 0x20000000u /* Terminated bit */
3252 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3253 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3254 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3255 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3256 +
3257 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3258 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3259 +
3260 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3261 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3262 +
3263 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3264 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3265 +
3266 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3267 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3268 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3269 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3270 +
3271 +#define DMA_DEVCMD(devcmd) \
3272 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3273 +#define DMA_DS(ds) \
3274 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3275 +#define DMA_COUNT(count) \
3276 + ((count) & DMADESC_COUNT_MASK)
3277 +
3278 +#endif /* RC32355_DMA_H */
3279 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3280 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3281 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3282 @@ -0,0 +1,442 @@
3283 +/**************************************************************************
3284 + *
3285 + * BRIEF MODULE DESCRIPTION
3286 + * Ethernet registers on IDT RC32355
3287 + *
3288 + * Copyright 2004 IDT Inc.
3289 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3290 + *
3291 + *
3292 + * This program is free software; you can redistribute it and/or modify it
3293 + * under the terms of the GNU General Public License as published by the
3294 + * Free Software Foundation; either version 2 of the License, or (at your
3295 + * option) any later version.
3296 + *
3297 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3298 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3299 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3300 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3301 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3302 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3303 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3304 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3305 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3306 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3307 + *
3308 + * You should have received a copy of the GNU General Public License along
3309 + * with this program; if not, write to the Free Software Foundation, Inc.,
3310 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3311 + *
3312 + *
3313 + * May 2004 rkt
3314 + * Initial Release
3315 + *
3316 + **************************************************************************
3317 + */
3318 +
3319 +
3320 +#ifndef RC32355_ETHER_H
3321 +#define RC32355_ETHER_H
3322 +
3323 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3324 +
3325 +/*
3326 + * A partial image of the RC32355 ethernet registers
3327 + */
3328 +typedef struct {
3329 + u32 ethintfc;
3330 + u32 ethfifott;
3331 + u32 etharc;
3332 + u32 ethhash0;
3333 + u32 ethhash1;
3334 + u32 ethfifost;
3335 + u32 ethfifos;
3336 + u32 ethodeops;
3337 + u32 ethis;
3338 + u32 ethos;
3339 + u32 ethmcp;
3340 + u32 _u1;
3341 + u32 ethid;
3342 + u32 _u2;
3343 + u32 _u3;
3344 + u32 _u4;
3345 + u32 ethod;
3346 + u32 _u5;
3347 + u32 _u6;
3348 + u32 _u7;
3349 + u32 ethodeop;
3350 + u32 _u8[43];
3351 + u32 ethsal0;
3352 + u32 ethsah0;
3353 + u32 ethsal1;
3354 + u32 ethsah1;
3355 + u32 ethsal2;
3356 + u32 ethsah2;
3357 + u32 ethsal3;
3358 + u32 ethsah3;
3359 + u32 ethrbc;
3360 + u32 ethrpc;
3361 + u32 ethrupc;
3362 + u32 ethrfc;
3363 + u32 ethtbc;
3364 + u32 ethgpf;
3365 + u32 _u9[50];
3366 + u32 ethmac1;
3367 + u32 ethmac2;
3368 + u32 ethipgt;
3369 + u32 ethipgr;
3370 + u32 ethclrt;
3371 + u32 ethmaxf;
3372 + u32 _u10;
3373 + u32 ethmtest;
3374 + u32 miimcfg;
3375 + u32 miimcmd;
3376 + u32 miimaddr;
3377 + u32 miimwtd;
3378 + u32 miimrdd;
3379 + u32 miimind;
3380 + u32 _u11;
3381 + u32 _u12;
3382 + u32 ethcfsa0;
3383 + u32 ethcfsa1;
3384 + u32 ethcfsa2;
3385 +} rc32355_eth_regs_t;
3386 +
3387 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3388 +
3389 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3390 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3391 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3392 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3393 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3394 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3395 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3396 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3397 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3398 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3399 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3400 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3401 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3402 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3403 +
3404 +/* for n in { 0, 1, 2, 3 } */
3405 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3406 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3407 +
3408 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3409 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3410 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3411 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3412 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3413 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3414 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3415 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3416 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3417 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3418 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3419 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3420 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3421 +
3422 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3423 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3424 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3425 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3426 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3427 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3428 +
3429 +/* for n in { 0, 1, 2 } */
3430 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3431 +
3432 +
3433 +/*
3434 + * Register Interpretations follow
3435 + */
3436 +
3437 +/******************************************************************************
3438 + * ETHINTFC register
3439 + *****************************************************************************/
3440 +
3441 +#define ETHERINTFC_EN (1<<0)
3442 +#define ETHERINTFC_ITS (1<<1)
3443 +#define ETHERINTFC_RES (1<<2)
3444 +#define ETHERINTFC_RIP (1<<2)
3445 +#define ETHERINTFC_JAM (1<<3)
3446 +
3447 +/******************************************************************************
3448 + * ETHFIFOTT register
3449 + *****************************************************************************/
3450 +
3451 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3452 +
3453 +/******************************************************************************
3454 + * ETHARC register
3455 + *****************************************************************************/
3456 +
3457 +#define ETHERARC_PRO (1<<0)
3458 +#define ETHERARC_AM (1<<1)
3459 +#define ETHERARC_AFM (1<<2)
3460 +#define ETHERARC_AB (1<<3)
3461 +
3462 +/******************************************************************************
3463 + * ETHHASH registers
3464 + *****************************************************************************/
3465 +
3466 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3467 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3468 +
3469 +/******************************************************************************
3470 + * ETHSA registers
3471 + *****************************************************************************/
3472 +
3473 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3474 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3475 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3476 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3477 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3478 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3479 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3480 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3481 +
3482 +/******************************************************************************
3483 + * ETHFIFOST register
3484 + *****************************************************************************/
3485 +
3486 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3487 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3488 +
3489 +/******************************************************************************
3490 + * ETHFIFOS register
3491 + *****************************************************************************/
3492 +
3493 +#define ETHERFIFOS_IR (1<<0)
3494 +#define ETHERFIFOS_OR (1<<1)
3495 +#define ETHERFIFOS_OVR (1<<2)
3496 +#define ETHERFIFOS_UND (1<<3)
3497 +
3498 +/******************************************************************************
3499 + * DATA registers
3500 + *****************************************************************************/
3501 +
3502 +#define ETHERID(v) (((v)&0xffff)<<0)
3503 +#define ETHEROD(v) (((v)&0xffff)<<0)
3504 +
3505 +/******************************************************************************
3506 + * ETHODEOPS register
3507 + *****************************************************************************/
3508 +
3509 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3510 +
3511 +/******************************************************************************
3512 + * ETHODEOP register
3513 + *****************************************************************************/
3514 +
3515 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3516 +
3517 +/******************************************************************************
3518 + * ETHIS register
3519 + *****************************************************************************/
3520 +
3521 +#define ETHERIS_EOP (1<<0)
3522 +#define ETHERIS_ROK (1<<2)
3523 +#define ETHERIS_FM (1<<3)
3524 +#define ETHERIS_MP (1<<4)
3525 +#define ETHERIS_BP (1<<5)
3526 +#define ETHERIS_VLT (1<<6)
3527 +#define ETHERIS_CF (1<<7)
3528 +#define ETHERIS_OVR (1<<8)
3529 +#define ETHERIS_CRC (1<<9)
3530 +#define ETHERIS_CV (1<<10)
3531 +#define ETHERIS_DB (1<<11)
3532 +#define ETHERIS_LE (1<<12)
3533 +#define ETHERIS_LOR (1<<13)
3534 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3535 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3536 +
3537 +/******************************************************************************
3538 + * ETHOS register
3539 + *****************************************************************************/
3540 +
3541 +#define ETHEROS_T (1<<0)
3542 +#define ETHEROS_TOK (1<<6)
3543 +#define ETHEROS_MP (1<<7)
3544 +#define ETHEROS_BP (1<<8)
3545 +#define ETHEROS_UND (1<<9)
3546 +#define ETHEROS_OF (1<<10)
3547 +#define ETHEROS_ED (1<<11)
3548 +#define ETHEROS_EC (1<<12)
3549 +#define ETHEROS_LC (1<<13)
3550 +#define ETHEROS_TD (1<<14)
3551 +#define ETHEROS_CRC (1<<15)
3552 +#define ETHEROS_LE (1<<16)
3553 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3554 +#define ETHEROS_PFD (1<<21)
3555 +
3556 +/******************************************************************************
3557 + * Statistics registers
3558 + *****************************************************************************/
3559 +
3560 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3561 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3562 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3563 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3564 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3565 +
3566 +/******************************************************************************
3567 + * ETHGPF register
3568 + *****************************************************************************/
3569 +
3570 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3571 +
3572 +/******************************************************************************
3573 + * MAC registers
3574 + *****************************************************************************/
3575 +//ETHMAC1
3576 +#define ETHERMAC1_RE (1<<0)
3577 +#define ETHERMAC1_PAF (1<<1)
3578 +#define ETHERMAC1_RFC (1<<2)
3579 +#define ETHERMAC1_TFC (1<<3)
3580 +#define ETHERMAC1_LB (1<<4)
3581 +#define ETHERMAC1_MR (1<<15)
3582 +
3583 +//ETHMAC2
3584 +#define ETHERMAC2_FD (1<<0)
3585 +#define ETHERMAC2_FLC (1<<1)
3586 +#define ETHERMAC2_HFE (1<<2)
3587 +#define ETHERMAC2_DC (1<<3)
3588 +#define ETHERMAC2_CEN (1<<4)
3589 +#define ETHERMAC2_PE (1<<5)
3590 +#define ETHERMAC2_VPE (1<<6)
3591 +#define ETHERMAC2_APE (1<<7)
3592 +#define ETHERMAC2_PPE (1<<8)
3593 +#define ETHERMAC2_LPE (1<<9)
3594 +#define ETHERMAC2_NB (1<<12)
3595 +#define ETHERMAC2_BP (1<<13)
3596 +#define ETHERMAC2_ED (1<<14)
3597 +
3598 +//ETHIPGT
3599 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3600 +
3601 +//ETHIPGR
3602 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3603 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3604 +
3605 +//ETHCLRT
3606 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3607 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3608 +
3609 +//ETHMAXF
3610 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3611 +
3612 +//ETHMTEST
3613 +#define ETHERMTEST_TB (1<<2)
3614 +
3615 +//ETHMCP
3616 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3617 +
3618 +//MIIMCFG
3619 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3620 +#define ETHERMIIMCFG_R (1<<15)
3621 +
3622 +//MIIMCMD
3623 +#define ETHERMIIMCMD_RD (1<<0)
3624 +#define ETHERMIIMCMD_SCN (1<<1)
3625 +
3626 +//MIIMADDR
3627 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3628 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3629 +
3630 +//MIIMWTD
3631 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3632 +
3633 +//MIIMRDD
3634 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3635 +
3636 +//MIIMIND
3637 +#define ETHERMIIMIND_BSY (1<<0)
3638 +#define ETHERMIIMIND_SCN (1<<1)
3639 +#define ETHERMIIMIND_NV (1<<2)
3640 +
3641 +//DMA DEVCS IN
3642 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3643 +#define ETHERDMA_IN_CES (1<<14)
3644 +#define ETHERDMA_IN_LOR (1<<13)
3645 +#define ETHERDMA_IN_LE (1<<12)
3646 +#define ETHERDMA_IN_DB (1<<11)
3647 +#define ETHERDMA_IN_CV (1<<10)
3648 +#define ETHERDMA_IN_CRC (1<<9)
3649 +#define ETHERDMA_IN_OVR (1<<8)
3650 +#define ETHERDMA_IN_CF (1<<7)
3651 +#define ETHERDMA_IN_VLT (1<<6)
3652 +#define ETHERDMA_IN_BP (1<<5)
3653 +#define ETHERDMA_IN_MP (1<<4)
3654 +#define ETHERDMA_IN_FM (1<<3)
3655 +#define ETHERDMA_IN_ROK (1<<2)
3656 +#define ETHERDMA_IN_LD (1<<1)
3657 +#define ETHERDMA_IN_FD (1<<0)
3658 +
3659 +//DMA DEVCS OUT
3660 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3661 +#define ETHERDMA_OUT_CNT 0x001e0000
3662 +#define ETHERDMA_OUT_SHFT 17
3663 +#define ETHERDMA_OUT_LE (1<<16)
3664 +