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[openwrt/openwrt.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
786 @@ -0,0 +1,134 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + switch (mips_machtype) {
909 + case MACH_ARUBA_AP70:
910 + return "Aruba AP70";
911 + case MACH_ARUBA_AP65:
912 + return "Aruba AP65";
913 + case MACH_ARUBA_AP60:
914 + return "Aruba AP60/AP61";
915 + default:
916 + return "Aruba UNKNOWN";
917 + }
918 +}
919 +
920 +EXPORT_SYMBOL(get_system_type);
921 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
922 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
923 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
924 @@ -0,0 +1,108 @@
925 +/**************************************************************************
926 + *
927 + * BRIEF MODULE DESCRIPTION
928 + * timer routines for IDT EB434 boards
929 + *
930 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
931 + *
932 + * This program is free software; you can redistribute it and/or modify it
933 + * under the terms of the GNU General Public License as published by the
934 + * Free Software Foundation; either version 2 of the License, or (at your
935 + * option) any later version.
936 + *
937 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
938 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
939 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
940 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
941 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
942 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
943 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
944 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
945 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
946 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
947 + *
948 + * You should have received a copy of the GNU General Public License along
949 + * with this program; if not, write to the Free Software Foundation, Inc.,
950 + * 675 Mass Ave, Cambridge, MA 02139, USA.
951 + *
952 + *
953 + **************************************************************************
954 + * May 2004 rkt, neb
955 + *
956 + * Initial Release
957 + *
958 + *
959 + *
960 + **************************************************************************
961 + */
962 +
963 +#include <linux/config.h>
964 +#include <linux/init.h>
965 +#include <linux/kernel_stat.h>
966 +#include <linux/sched.h>
967 +#include <linux/spinlock.h>
968 +#include <linux/mc146818rtc.h>
969 +#include <linux/irq.h>
970 +#include <linux/timex.h>
971 +
972 +#include <linux/param.h>
973 +#include <asm/mipsregs.h>
974 +#include <asm/ptrace.h>
975 +#include <asm/time.h>
976 +#include <asm/hardirq.h>
977 +
978 +#include <asm/mipsregs.h>
979 +#include <asm/ptrace.h>
980 +#include <asm/debug.h>
981 +#include <asm/time.h>
982 +
983 +#include <asm/idt-boards/rc32434/rc32434.h>
984 +
985 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
986 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
987 +
988 +extern unsigned int idt_cpu_freq;
989 +
990 +static unsigned long __init cal_r4koff(void)
991 +{
992 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
993 + return (mips_hpt_frequency / HZ);
994 +}
995 +
996 +void __init aruba_time_init(void)
997 +{
998 + unsigned int est_freq, flags;
999 + local_irq_save(flags);
1000 +
1001 + printk("calculating r4koff... ");
1002 + r4k_offset = cal_r4koff();
1003 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1004 +
1005 + est_freq = 2 * r4k_offset * HZ;
1006 + est_freq += 5000; /* round */
1007 + est_freq -= est_freq % 10000;
1008 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1009 + (est_freq % 1000000) * 100 / 1000000);
1010 + local_irq_restore(flags);
1011 +
1012 +}
1013 +
1014 +void __init aruba_timer_setup(struct irqaction *irq)
1015 +{
1016 + /* we are using the cpu counter for timer interrupts */
1017 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1018 +
1019 + /* to generate the first timer interrupt */
1020 + r4k_cur = (read_c0_count() + r4k_offset);
1021 + write_c0_compare(r4k_cur);
1022 +
1023 +}
1024 +
1025 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1026 +{
1027 + irq_enter();
1028 + kstat_this_cpu.irqs[irq]++;
1029 +
1030 + timer_interrupt(irq, NULL, regs);
1031 + irq_exit();
1032 +}
1033 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1034 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
1035 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1036 @@ -227,6 +227,17 @@
1037 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1038 a kernel for this platform.
1039
1040 +config MACH_ARUBA
1041 + bool "Support for the ARUBA product line"
1042 + select DMA_NONCOHERENT
1043 + select CPU_HAS_PREFETCH
1044 + select HW_HAS_PCI
1045 + select SWAP_IO_SPACE
1046 + select SYS_SUPPORTS_32BIT_KERNEL
1047 + select SYS_HAS_CPU_MIPS32_R1
1048 + select SYS_SUPPORTS_BIG_ENDIAN
1049 +
1050 +
1051 config MACH_JAZZ
1052 bool "Jazz family of machines"
1053 select ARC
1054 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1055 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
1056 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
1057 @@ -145,6 +145,14 @@
1058 #
1059
1060 #
1061 +# Aruba
1062 +#
1063 +
1064 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1065 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1066 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1067 +
1068 +#
1069 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1070 #
1071 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1072 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1073 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
1074 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
1075 @@ -876,7 +876,6 @@
1076 case CPU_R10000:
1077 case CPU_R12000:
1078 case CPU_R14000:
1079 - case CPU_4KC:
1080 case CPU_SB1:
1081 case CPU_SB1A:
1082 case CPU_4KSC:
1083 @@ -904,6 +903,7 @@
1084 tlbw(p);
1085 break;
1086
1087 + case CPU_4KC:
1088 case CPU_4KEC:
1089 case CPU_24K:
1090 case CPU_34K:
1091 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1092 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
1093 +++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
1094 @@ -187,6 +187,13 @@
1095
1096 source "drivers/net/arm/Kconfig"
1097
1098 +config IDT_RC32434_ETH
1099 + tristate "IDT RC32434 Local Ethernet support"
1100 + depends on NET_ETHERNET
1101 + help
1102 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1103 + To compile this driver as a module, choose M here.
1104 +
1105 config MACE
1106 tristate "MACE (Power Mac ethernet) support"
1107 depends on NET_ETHERNET && PPC_PMAC && PPC32
1108 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1109 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
1110 +++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
1111 @@ -38,6 +38,7 @@
1112
1113 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1114
1115 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1116 obj-$(CONFIG_DGRS) += dgrs.o
1117 obj-$(CONFIG_VORTEX) += 3c59x.o
1118 obj-$(CONFIG_TYPHOON) += typhoon.o
1119 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1120 --- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
1121 +++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
1122 @@ -771,6 +771,49 @@
1123 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1124 static struct ethtool_ops ethtool_ops;
1125
1126 +#ifdef CONFIG_MACH_ARUBA
1127 +
1128 +#include <linux/ctype.h>
1129 +
1130 +#ifndef ERR
1131 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1132 +#endif
1133 +
1134 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1135 +{
1136 + int i, j;
1137 + unsigned char result, value;
1138 +
1139 + for (i=0; i<6; i++) {
1140 + result = 0;
1141 + if (i != 5 && *(macstr+2) != ':') {
1142 + ERR("invalid mac address format: %d %c\n",
1143 + i, *(macstr+2));
1144 + return -EINVAL;
1145 + }
1146 + for (j=0; j<2; j++) {
1147 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1148 + toupper(*macstr)-'A'+10) < 16) {
1149 + result = result*16 + value;
1150 + macstr++;
1151 + }
1152 + else {
1153 + ERR("invalid mac address "
1154 + "character: %c\n", *macstr);
1155 + return -EINVAL;
1156 + }
1157 + }
1158 +
1159 + macstr++;
1160 + dev->dev_addr[i] = result;
1161 + }
1162 +
1163 + dev->dev_addr[5]++;
1164 + return 0;
1165 +}
1166 +
1167 +#endif
1168 +
1169 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1170 {
1171 return (void __iomem *) dev->base_addr;
1172 @@ -871,6 +914,7 @@
1173 goto err_ioremap;
1174 }
1175
1176 +#ifndef CONFIG_MACH_ARUBA
1177 /* Work around the dropped serial bit. */
1178 prev_eedata = eeprom_read(ioaddr, 6);
1179 for (i = 0; i < 3; i++) {
1180 @@ -879,6 +923,19 @@
1181 dev->dev_addr[i*2+1] = eedata >> 7;
1182 prev_eedata = eedata;
1183 }
1184 +#else
1185 + {
1186 + char mac[32];
1187 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1188 + extern char *getenv(char *e);
1189 + memset(mac, 0, 32);
1190 + memcpy(mac, getenv("ethaddr"), 17);
1191 + if (parse_mac_addr(dev, mac)){
1192 + printk("%s: MAC address not found\n", __func__);
1193 + memcpy(dev->dev_addr, def_mac, 6);
1194 + }
1195 + }
1196 +#endif
1197
1198 dev->base_addr = (unsigned long __force) ioaddr;
1199 dev->irq = irq;
1200 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1201 --- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1203 @@ -0,0 +1,1273 @@
1204 +/**************************************************************************
1205 + *
1206 + * BRIEF MODULE DESCRIPTION
1207 + * Driver for the IDT RC32434 on-chip ethernet controller.
1208 + *
1209 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1210 + *
1211 + * This program is free software; you can redistribute it and/or modify it
1212 + * under the terms of the GNU General Public License as published by the
1213 + * Free Software Foundation; either version 2 of the License, or (at your
1214 + * option) any later version.
1215 + *
1216 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1217 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1218 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1219 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1220 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1221 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1222 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1223 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1224 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1225 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1226 + *
1227 + * You should have received a copy of the GNU General Public License along
1228 + * with this program; if not, write to the Free Software Foundation, Inc.,
1229 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1230 + *
1231 + *
1232 + **************************************************************************
1233 + * May 2004 rkt, neb
1234 + *
1235 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1236 + *
1237 + * Aug 2004 Sadik
1238 + *
1239 + * Added NAPI
1240 + *
1241 + **************************************************************************
1242 + */
1243 +
1244 +#include <linux/config.h>
1245 +#include <linux/version.h>
1246 +#include <linux/module.h>
1247 +#include <linux/kernel.h>
1248 +#include <linux/moduleparam.h>
1249 +#include <linux/sched.h>
1250 +#include <linux/ctype.h>
1251 +#include <linux/types.h>
1252 +#include <linux/fcntl.h>
1253 +#include <linux/interrupt.h>
1254 +#include <linux/ptrace.h>
1255 +#include <linux/init.h>
1256 +#include <linux/ioport.h>
1257 +#include <linux/proc_fs.h>
1258 +#include <linux/in.h>
1259 +#include <linux/slab.h>
1260 +#include <linux/string.h>
1261 +#include <linux/delay.h>
1262 +#include <linux/netdevice.h>
1263 +#include <linux/etherdevice.h>
1264 +#include <linux/skbuff.h>
1265 +#include <linux/errno.h>
1266 +#include <asm/bootinfo.h>
1267 +#include <asm/system.h>
1268 +#include <asm/bitops.h>
1269 +#include <asm/pgtable.h>
1270 +#include <asm/segment.h>
1271 +#include <asm/io.h>
1272 +#include <asm/dma.h>
1273 +
1274 +#include "rc32434_eth.h"
1275 +
1276 +#define DRIVER_VERSION "(mar2904)"
1277 +
1278 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1279 +
1280 +
1281 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1282 + ((dev)->dev_addr[1]))
1283 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1284 + ((dev)->dev_addr[3] << 16) | \
1285 + ((dev)->dev_addr[4] << 8) | \
1286 + ((dev)->dev_addr[5]))
1287 +
1288 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1289 +static char mac0[18] = "08:00:06:05:40:01";
1290 +
1291 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,17)
1292 +module_param_string(mac0, mac0, 18, 0);
1293 +#else
1294 +MODULE_PARM(mac0, "c18");
1295 +#endif
1296 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1297 +
1298 +static struct rc32434_if_t {
1299 + char *name;
1300 + struct net_device *dev;
1301 + char* mac_str;
1302 + int weight;
1303 + u32 iobase;
1304 + u32 rxdmabase;
1305 + u32 txdmabase;
1306 + int rx_dma_irq;
1307 + int tx_dma_irq;
1308 + int rx_ovr_irq;
1309 + int tx_und_irq;
1310 +} rc32434_iflist[] =
1311 +{
1312 + {
1313 + "rc32434_eth0", NULL, mac0,
1314 + 64,
1315 + ETH0_PhysicalAddress,
1316 + ETH0_RX_DMA_ADDR,
1317 + ETH0_TX_DMA_ADDR,
1318 + ETH0_DMA_RX_IRQ,
1319 + ETH0_DMA_TX_IRQ,
1320 + ETH0_RX_OVR_IRQ,
1321 + ETH0_TX_UND_IRQ
1322 + }
1323 +};
1324 +
1325 +
1326 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1327 +{
1328 + int i, j;
1329 + unsigned char result, value;
1330 +
1331 + for (i=0; i<6; i++) {
1332 + result = 0;
1333 + if (i != 5 && *(macstr+2) != ':') {
1334 + ERR("invalid mac address format: %d %c\n",
1335 + i, *(macstr+2));
1336 + return -EINVAL;
1337 + }
1338 + for (j=0; j<2; j++) {
1339 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1340 + toupper(*macstr)-'A'+10) < 16) {
1341 + result = result*16 + value;
1342 + macstr++;
1343 + }
1344 + else {
1345 + ERR("invalid mac address "
1346 + "character: %c\n", *macstr);
1347 + return -EINVAL;
1348 + }
1349 + }
1350 +
1351 + macstr++;
1352 + dev->dev_addr[i] = result;
1353 + }
1354 +
1355 + return 0;
1356 +}
1357 +
1358 +
1359 +
1360 +static inline void rc32434_abort_tx(struct net_device *dev)
1361 +{
1362 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1363 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1364 +
1365 +}
1366 +
1367 +static inline void rc32434_abort_rx(struct net_device *dev)
1368 +{
1369 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1370 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1371 +
1372 +}
1373 +
1374 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1375 +{
1376 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1377 +}
1378 +
1379 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1380 +{
1381 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1382 +}
1383 +
1384 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1385 +{
1386 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1387 +}
1388 +
1389 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1390 +{
1391 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1392 +}
1393 +
1394 +#ifdef RC32434_PROC_DEBUG
1395 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1396 + int length, int *eof, void *data)
1397 +{
1398 + struct net_device *dev = (struct net_device *)data;
1399 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1400 + int len = 0;
1401 +
1402 + /* print out header */
1403 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1404 + len += sprintf (buf + len,
1405 + "DMA halt count = %10d, DMA run count = %10d\n",
1406 + lp->dma_halt_cnt, lp->dma_run_cnt);
1407 +
1408 + if (fpos >= len) {
1409 + *start = buf;
1410 + *eof = 1;
1411 + return 0;
1412 + }
1413 + *start = buf + fpos;
1414 +
1415 + if ((len -= fpos) > length)
1416 + return length;
1417 + *eof = 1;
1418 +
1419 + return len;
1420 +
1421 +}
1422 +#endif
1423 +
1424 +
1425 +/*
1426 + * Restart the RC32434 ethernet controller.
1427 + */
1428 +static int rc32434_restart(struct net_device *dev)
1429 +{
1430 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1431 +
1432 + /*
1433 + * Disable interrupts
1434 + */
1435 + disable_irq(lp->rx_irq);
1436 + disable_irq(lp->tx_irq);
1437 +#ifdef RC32434_REVISION
1438 + disable_irq(lp->ovr_irq);
1439 +#endif
1440 + disable_irq(lp->und_irq);
1441 +
1442 + /* Mask F E bit in Tx DMA */
1443 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1444 + /* Mask D H E bit in Rx DMA */
1445 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1446 +
1447 + rc32434_init(dev);
1448 + rc32434_multicast_list(dev);
1449 +
1450 + enable_irq(lp->und_irq);
1451 +#ifdef RC32434_REVISION
1452 + enable_irq(lp->ovr_irq);
1453 +#endif
1454 + enable_irq(lp->tx_irq);
1455 + enable_irq(lp->rx_irq);
1456 +
1457 + return 0;
1458 +}
1459 +
1460 +int rc32434_init_module(void)
1461 +{
1462 +#ifdef CONFIG_MACH_ARUBA
1463 + if (mips_machtype != MACH_ARUBA_AP70)
1464 + return 1;
1465 +#endif
1466 +
1467 + printk(KERN_INFO DRIVER_NAME " \n");
1468 + return rc32434_probe(0);
1469 +}
1470 +
1471 +static int rc32434_probe(int port_num)
1472 +{
1473 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1474 + struct rc32434_local *lp = NULL;
1475 + struct net_device *dev = NULL;
1476 + int i, retval,err;
1477 +
1478 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1479 + if(!dev) {
1480 + ERR("rc32434_eth: alloc_etherdev failed\n");
1481 + return -1;
1482 + }
1483 +
1484 + SET_MODULE_OWNER(dev);
1485 + bif->dev = dev;
1486 +
1487 +#ifdef CONFIG_MACH_ARUBA
1488 + {
1489 + extern char * getenv(char *e);
1490 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1491 + }
1492 +#endif
1493 +
1494 + printk("mac: %s\n", bif->mac_str);
1495 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1496 + ERR("MAC address parse failed\n");
1497 + free_netdev(dev);
1498 + return -1;
1499 + }
1500 +
1501 +
1502 + /* Initialize the device structure. */
1503 + if (dev->priv == NULL) {
1504 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1505 + memset(lp, 0, sizeof(struct rc32434_local));
1506 + }
1507 + else {
1508 + lp = (struct rc32434_local *)dev->priv;
1509 + }
1510 +
1511 + lp->rx_irq = bif->rx_dma_irq;
1512 + lp->tx_irq = bif->tx_dma_irq;
1513 + lp->ovr_irq = bif->rx_ovr_irq;
1514 + lp->und_irq = bif->tx_und_irq;
1515 +
1516 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1517 +
1518 + if (!lp->eth_regs) {
1519 + ERR("Can't remap eth registers\n");
1520 + retval = -ENXIO;
1521 + goto probe_err_out;
1522 + }
1523 +
1524 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1525 +
1526 + if (!lp->rx_dma_regs) {
1527 + ERR("Can't remap Rx DMA registers\n");
1528 + retval = -ENXIO;
1529 + goto probe_err_out;
1530 + }
1531 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1532 +
1533 + if (!lp->tx_dma_regs) {
1534 + ERR("Can't remap Tx DMA registers\n");
1535 + retval = -ENXIO;
1536 + goto probe_err_out;
1537 + }
1538 +
1539 +#ifdef RC32434_PROC_DEBUG
1540 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1541 + rc32434_read_proc, dev);
1542 +#endif
1543 +
1544 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1545 + if (!lp->td_ring) {
1546 + ERR("Can't allocate descriptors\n");
1547 + retval = -ENOMEM;
1548 + goto probe_err_out;
1549 + }
1550 +
1551 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1552 +
1553 + /* now convert TD_RING pointer to KSEG1 */
1554 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1555 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1556 +
1557 +
1558 + spin_lock_init(&lp->lock);
1559 +
1560 + dev->base_addr = bif->iobase;
1561 + /* just use the rx dma irq */
1562 + dev->irq = bif->rx_dma_irq;
1563 +
1564 + dev->priv = lp;
1565 +
1566 + dev->open = rc32434_open;
1567 + dev->stop = rc32434_close;
1568 + dev->hard_start_xmit = rc32434_send_packet;
1569 + dev->get_stats = rc32434_get_stats;
1570 + dev->set_multicast_list = &rc32434_multicast_list;
1571 + dev->tx_timeout = rc32434_tx_timeout;
1572 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1573 +
1574 +#ifdef CONFIG_IDT_USE_NAPI
1575 + dev->poll = rc32434_poll;
1576 + dev->weight = bif->weight;
1577 + printk("Using NAPI with weight %d\n",dev->weight);
1578 +#else
1579 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1580 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1581 +#endif
1582 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1583 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1584 +
1585 + if ((err = register_netdev(dev))) {
1586 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1587 + free_netdev(dev);
1588 + retval = -EINVAL;
1589 + goto probe_err_out;
1590 + }
1591 +
1592 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1593 + for (i = 0; i < 6; i++) {
1594 + printk("%2.2x", dev->dev_addr[i]);
1595 + if (i<5)
1596 + printk(":");
1597 + }
1598 + printk("\n");
1599 +
1600 + return 0;
1601 +
1602 + probe_err_out:
1603 + rc32434_cleanup_module();
1604 + ERR(" failed. Returns %d\n", retval);
1605 + return retval;
1606 +
1607 +}
1608 +
1609 +
1610 +static void rc32434_cleanup_module(void)
1611 +{
1612 + int i;
1613 +
1614 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1615 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1616 + if (bif->dev != NULL) {
1617 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1618 + if (lp != NULL) {
1619 + if (lp->eth_regs)
1620 + iounmap((void*)lp->eth_regs);
1621 + if (lp->rx_dma_regs)
1622 + iounmap((void*)lp->rx_dma_regs);
1623 + if (lp->tx_dma_regs)
1624 + iounmap((void*)lp->tx_dma_regs);
1625 + if (lp->td_ring)
1626 + kfree((void*)KSEG0ADDR(lp->td_ring));
1627 +
1628 +#ifdef RC32434_PROC_DEBUG
1629 + if (lp->ps) {
1630 + remove_proc_entry(bif->name, proc_net);
1631 + }
1632 +#endif
1633 + kfree(lp);
1634 + }
1635 +
1636 + unregister_netdev(bif->dev);
1637 + free_netdev(bif->dev);
1638 + kfree(bif->dev);
1639 + }
1640 + }
1641 +}
1642 +
1643 +
1644 +
1645 +static int rc32434_open(struct net_device *dev)
1646 +{
1647 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1648 +
1649 + /* Initialize */
1650 + if (rc32434_init(dev)) {
1651 + ERR("Error: cannot open the Ethernet device\n");
1652 + return -EAGAIN;
1653 + }
1654 +
1655 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1656 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1657 + SA_SHIRQ | SA_INTERRUPT,
1658 + "rc32434 ethernet Rx", dev)) {
1659 + ERR(": unable to get Rx DMA IRQ %d\n",
1660 + lp->rx_irq);
1661 + return -EAGAIN;
1662 + }
1663 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1664 + SA_SHIRQ | SA_INTERRUPT,
1665 + "rc32434 ethernet Tx", dev)) {
1666 + ERR(": unable to get Tx DMA IRQ %d\n",
1667 + lp->tx_irq);
1668 + free_irq(lp->rx_irq, dev);
1669 + return -EAGAIN;
1670 + }
1671 +
1672 +#ifdef RC32434_REVISION
1673 + /* Install handler for overrun error. */
1674 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1675 + SA_SHIRQ | SA_INTERRUPT,
1676 + "Ethernet Overflow", dev)) {
1677 + ERR(": unable to get OVR IRQ %d\n",
1678 + lp->ovr_irq);
1679 + free_irq(lp->rx_irq, dev);
1680 + free_irq(lp->tx_irq, dev);
1681 + return -EAGAIN;
1682 + }
1683 +#endif
1684 +
1685 + /* Install handler for underflow error. */
1686 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1687 + SA_SHIRQ | SA_INTERRUPT,
1688 + "Ethernet Underflow", dev)) {
1689 + ERR(": unable to get UND IRQ %d\n",
1690 + lp->und_irq);
1691 + free_irq(lp->rx_irq, dev);
1692 + free_irq(lp->tx_irq, dev);
1693 +#ifdef RC32434_REVISION
1694 + free_irq(lp->ovr_irq, dev);
1695 +#endif
1696 + return -EAGAIN;
1697 + }
1698 +
1699 +
1700 + return 0;
1701 +}
1702 +
1703 +
1704 +
1705 +
1706 +static int rc32434_close(struct net_device *dev)
1707 +{
1708 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1709 + u32 tmp;
1710 +
1711 + /* Disable interrupts */
1712 + disable_irq(lp->rx_irq);
1713 + disable_irq(lp->tx_irq);
1714 +#ifdef RC32434_REVISION
1715 + disable_irq(lp->ovr_irq);
1716 +#endif
1717 + disable_irq(lp->und_irq);
1718 +
1719 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1720 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1721 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1722 +
1723 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1724 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1725 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1726 +
1727 + free_irq(lp->rx_irq, dev);
1728 + free_irq(lp->tx_irq, dev);
1729 +#ifdef RC32434_REVISION
1730 + free_irq(lp->ovr_irq, dev);
1731 +#endif
1732 + free_irq(lp->und_irq, dev);
1733 + return 0;
1734 +}
1735 +
1736 +
1737 +/* transmit packet */
1738 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1739 +{
1740 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1741 + unsigned long flags;
1742 + u32 length;
1743 + DMAD_t td;
1744 +
1745 +
1746 + spin_lock_irqsave(&lp->lock, flags);
1747 +
1748 + td = &lp->td_ring[lp->tx_chain_tail];
1749 +
1750 + /* stop queue when full, drop pkts if queue already full */
1751 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1752 + lp->tx_full = 1;
1753 +
1754 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1755 + netif_stop_queue(dev);
1756 + }
1757 + else {
1758 + lp->stats.tx_dropped++;
1759 + dev_kfree_skb_any(skb);
1760 + spin_unlock_irqrestore(&lp->lock, flags);
1761 + return 1;
1762 + }
1763 + }
1764 +
1765 + lp->tx_count ++;
1766 +
1767 + lp->tx_skb[lp->tx_chain_tail] = skb;
1768 +
1769 + length = skb->len;
1770 +
1771 + /* Setup the transmit descriptor. */
1772 + td->ca = CPHYSADDR(skb->data);
1773 +
1774 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1775 + if( lp->tx_chain_status == empty ) {
1776 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1777 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1778 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1779 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1780 + }
1781 + else {
1782 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1783 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1784 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1785 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1786 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1787 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1788 + lp->tx_chain_status = empty;
1789 + }
1790 + }
1791 + else {
1792 + if( lp->tx_chain_status == empty ) {
1793 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1794 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1795 + lp->tx_chain_status = filled;
1796 + }
1797 + else {
1798 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1799 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1800 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1801 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1802 + }
1803 + }
1804 +
1805 + dev->trans_start = jiffies;
1806 +
1807 + spin_unlock_irqrestore(&lp->lock, flags);
1808 +
1809 + return 0;
1810 +}
1811 +
1812 +
1813 +/* Ethernet MII-PHY Handler */
1814 +static void rc32434_mii_handler(unsigned long data)
1815 +{
1816 + struct net_device *dev = (struct net_device *)data;
1817 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1818 + unsigned long flags;
1819 + unsigned long duplex_status;
1820 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1821 +
1822 + spin_lock_irqsave(&lp->lock, flags);
1823 +
1824 + /* Two ports are using the same MII, the difference is the PHY address */
1825 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1826 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1827 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1828 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1829 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1830 +
1831 + ERR("irq:%x port_addr:%x RDD:%x\n",
1832 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1833 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1834 + if(duplex_status != lp->duplex_mode) {
1835 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1836 + lp->duplex_mode = duplex_status;
1837 + rc32434_restart(dev);
1838 + }
1839 +
1840 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1841 + add_timer(&lp->mii_phy_timer);
1842 +
1843 + spin_unlock_irqrestore(&lp->lock, flags);
1844 +
1845 +}
1846 +
1847 +#ifdef RC32434_REVISION
1848 +/* Ethernet Rx Overflow interrupt */
1849 +static irqreturn_t
1850 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1851 +{
1852 + struct net_device *dev = (struct net_device *)dev_id;
1853 + struct rc32434_local *lp;
1854 + unsigned int ovr;
1855 + irqreturn_t retval = IRQ_NONE;
1856 +
1857 + ASSERT(dev != NULL);
1858 +
1859 + lp = (struct rc32434_local *)dev->priv;
1860 + spin_lock(&lp->lock);
1861 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1862 +
1863 + if(ovr & ETHINTFC_ovr_m) {
1864 + netif_stop_queue(dev);
1865 +
1866 + /* clear OVR bit */
1867 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1868 +
1869 + /* Restart interface */
1870 + rc32434_restart(dev);
1871 + retval = IRQ_HANDLED;
1872 + }
1873 + spin_unlock(&lp->lock);
1874 +
1875 + return retval;
1876 +}
1877 +
1878 +#endif
1879 +
1880 +
1881 +/* Ethernet Tx Underflow interrupt */
1882 +static irqreturn_t
1883 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1884 +{
1885 + struct net_device *dev = (struct net_device *)dev_id;
1886 + struct rc32434_local *lp;
1887 + unsigned int und;
1888 + irqreturn_t retval = IRQ_NONE;
1889 +
1890 + ASSERT(dev != NULL);
1891 +
1892 + lp = (struct rc32434_local *)dev->priv;
1893 +
1894 + spin_lock(&lp->lock);
1895 +
1896 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1897 +
1898 + if(und & ETHINTFC_und_m) {
1899 + netif_stop_queue(dev);
1900 +
1901 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1902 +
1903 + /* Restart interface */
1904 + rc32434_restart(dev);
1905 + retval = IRQ_HANDLED;
1906 + }
1907 +
1908 + spin_unlock(&lp->lock);
1909 +
1910 + return retval;
1911 +}
1912 +
1913 +
1914 +/* Ethernet Rx DMA interrupt */
1915 +static irqreturn_t
1916 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1917 +{
1918 + struct net_device *dev = (struct net_device *)dev_id;
1919 + struct rc32434_local* lp;
1920 + volatile u32 dmas,dmasm;
1921 + irqreturn_t retval;
1922 +
1923 + ASSERT(dev != NULL);
1924 +
1925 + lp = (struct rc32434_local *)dev->priv;
1926 +
1927 + spin_lock(&lp->lock);
1928 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1929 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1930 + /* Mask D H E bit in Rx DMA */
1931 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1932 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1933 +#ifdef CONFIG_IDT_USE_NAPI
1934 + if(netif_rx_schedule_prep(dev))
1935 + __netif_rx_schedule(dev);
1936 +#else
1937 + tasklet_hi_schedule(lp->rx_tasklet);
1938 +#endif
1939 +
1940 + if (dmas & DMAS_e_m)
1941 + ERR(": DMA error\n");
1942 +
1943 + retval = IRQ_HANDLED;
1944 + }
1945 + else
1946 + retval = IRQ_NONE;
1947 +
1948 + spin_unlock(&lp->lock);
1949 + return retval;
1950 +}
1951 +
1952 +#ifdef CONFIG_IDT_USE_NAPI
1953 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1954 +#else
1955 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1956 +#endif
1957 +{
1958 + struct net_device *dev = (struct net_device *)rx_data_dev;
1959 + struct rc32434_local* lp = netdev_priv(dev);
1960 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1961 + struct sk_buff *skb, *skb_new;
1962 + u8* pkt_buf;
1963 + u32 devcs, count, pkt_len, pktuncrc_len;
1964 + volatile u32 dmas;
1965 +#ifdef CONFIG_IDT_USE_NAPI
1966 + u32 received = 0;
1967 + int rx_work_limit = min(*budget,dev->quota);
1968 +#else
1969 + unsigned long flags;
1970 + spin_lock_irqsave(&lp->lock, flags);
1971 +#endif
1972 +
1973 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1974 +#ifdef CONFIG_IDT_USE_NAPI
1975 + if(--rx_work_limit <0)
1976 + {
1977 + break;
1978 + }
1979 +#endif
1980 + /* init the var. used for the later operations within the while loop */
1981 + skb_new = NULL;
1982 + devcs = rd->devcs;
1983 + pkt_len = RCVPKT_LENGTH(devcs);
1984 + skb = lp->rx_skb[lp->rx_next_done];
1985 +
1986 + if (count < 64) {
1987 + lp->stats.rx_errors++;
1988 + lp->stats.rx_dropped++;
1989 + }
1990 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1991 + /* check that this is a whole packet */
1992 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1993 + lp->stats.rx_errors++;
1994 + lp->stats.rx_dropped++;
1995 + }
1996 + else if ( (devcs & ETHRX_rok_m) ) {
1997 +
1998 + {
1999 + /* must be the (first and) last descriptor then */
2000 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2001 +
2002 + pktuncrc_len = pkt_len - 4;
2003 + /* invalidate the cache */
2004 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2005 +
2006 + /* Malloc up new buffer. */
2007 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2008 +
2009 + if (skb_new != NULL){
2010 + /* Make room */
2011 + skb_put(skb, pktuncrc_len);
2012 +
2013 + skb->protocol = eth_type_trans(skb, dev);
2014 +
2015 + /* pass the packet to upper layers */
2016 +#ifdef CONFIG_IDT_USE_NAPI
2017 + netif_receive_skb(skb);
2018 +#else
2019 + netif_rx(skb);
2020 +#endif
2021 +
2022 + dev->last_rx = jiffies;
2023 + lp->stats.rx_packets++;
2024 + lp->stats.rx_bytes += pktuncrc_len;
2025 +
2026 + if (IS_RCV_MP(devcs))
2027 + lp->stats.multicast++;
2028 +
2029 + /* 16 bit align */
2030 + skb_reserve(skb_new, 2);
2031 +
2032 + skb_new->dev = dev;
2033 + lp->rx_skb[lp->rx_next_done] = skb_new;
2034 + }
2035 + else {
2036 + ERR("no memory, dropping rx packet.\n");
2037 + lp->stats.rx_errors++;
2038 + lp->stats.rx_dropped++;
2039 + }
2040 + }
2041 +
2042 + }
2043 + else {
2044 + /* This should only happen if we enable accepting broken packets */
2045 + lp->stats.rx_errors++;
2046 + lp->stats.rx_dropped++;
2047 +
2048 + /* add statistics counters */
2049 + if (IS_RCV_CRC_ERR(devcs)) {
2050 + DBG(2, "RX CRC error\n");
2051 + lp->stats.rx_crc_errors++;
2052 + }
2053 + else if (IS_RCV_LOR_ERR(devcs)) {
2054 + DBG(2, "RX LOR error\n");
2055 + lp->stats.rx_length_errors++;
2056 + }
2057 + else if (IS_RCV_LE_ERR(devcs)) {
2058 + DBG(2, "RX LE error\n");
2059 + lp->stats.rx_length_errors++;
2060 + }
2061 + else if (IS_RCV_OVR_ERR(devcs)) {
2062 + lp->stats.rx_over_errors++;
2063 + }
2064 + else if (IS_RCV_CV_ERR(devcs)) {
2065 + /* code violation */
2066 + DBG(2, "RX CV error\n");
2067 + lp->stats.rx_frame_errors++;
2068 + }
2069 + else if (IS_RCV_CES_ERR(devcs)) {
2070 + DBG(2, "RX Preamble error\n");
2071 + }
2072 + }
2073 +
2074 + rd->devcs = 0;
2075 +
2076 + /* restore descriptor's curr_addr */
2077 + if(skb_new)
2078 + rd->ca = CPHYSADDR(skb_new->data);
2079 + else
2080 + rd->ca = CPHYSADDR(skb->data);
2081 +
2082 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2083 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2084 +
2085 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2086 + rd = &lp->rd_ring[lp->rx_next_done];
2087 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2088 + }
2089 +#ifdef CONFIG_IDT_USE_NAPI
2090 + dev->quota -= received;
2091 + *budget =- received;
2092 + if(rx_work_limit < 0)
2093 + goto not_done;
2094 +#endif
2095 +
2096 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2097 +
2098 + if(dmas & DMAS_h_m) {
2099 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2100 +#ifdef RC32434_PROC_DEBUG
2101 + lp->dma_halt_cnt++;
2102 +#endif
2103 + rd->devcs = 0;
2104 + skb = lp->rx_skb[lp->rx_next_done];
2105 + rd->ca = CPHYSADDR(skb->data);
2106 + rc32434_chain_rx(lp,rd);
2107 + }
2108 +
2109 +#ifdef CONFIG_IDT_USE_NAPI
2110 + netif_rx_complete(dev);
2111 +#endif
2112 + /* Enable D H E bit in Rx DMA */
2113 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2114 +#ifdef CONFIG_IDT_USE_NAPI
2115 + return 0;
2116 + not_done:
2117 + return 1;
2118 +#else
2119 + spin_unlock_irqrestore(&lp->lock, flags);
2120 + return;
2121 +#endif
2122 +
2123 +
2124 +}
2125 +
2126 +
2127 +
2128 +/* Ethernet Tx DMA interrupt */
2129 +static irqreturn_t
2130 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2131 +{
2132 + struct net_device *dev = (struct net_device *)dev_id;
2133 + struct rc32434_local *lp;
2134 + volatile u32 dmas,dmasm;
2135 + irqreturn_t retval;
2136 +
2137 + ASSERT(dev != NULL);
2138 +
2139 + lp = (struct rc32434_local *)dev->priv;
2140 +
2141 + spin_lock(&lp->lock);
2142 +
2143 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2144 +
2145 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2146 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2147 + /* Mask F E bit in Tx DMA */
2148 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2149 +
2150 + tasklet_hi_schedule(lp->tx_tasklet);
2151 +
2152 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2153 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2154 + lp->tx_chain_status = empty;
2155 + lp->tx_chain_head = lp->tx_chain_tail;
2156 + dev->trans_start = jiffies;
2157 + }
2158 +
2159 + if (dmas & DMAS_e_m)
2160 + ERR(": DMA error\n");
2161 +
2162 + retval = IRQ_HANDLED;
2163 + }
2164 + else
2165 + retval = IRQ_NONE;
2166 +
2167 + spin_unlock(&lp->lock);
2168 +
2169 + return retval;
2170 +}
2171 +
2172 +
2173 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2174 +{
2175 + struct net_device *dev = (struct net_device *)tx_data_dev;
2176 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2177 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2178 + u32 devcs;
2179 + unsigned long flags;
2180 + volatile u32 dmas;
2181 +
2182 + spin_lock_irqsave(&lp->lock, flags);
2183 +
2184 + /* process all desc that are done */
2185 + while(IS_DMA_FINISHED(td->control)) {
2186 + if(lp->tx_full == 1) {
2187 + netif_wake_queue(dev);
2188 + lp->tx_full = 0;
2189 + }
2190 +
2191 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2192 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2193 + lp->stats.tx_errors++;
2194 + lp->stats.tx_dropped++;
2195 +
2196 + /* should never happen */
2197 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2198 + }
2199 + else if (IS_TX_TOK(devcs)) {
2200 + lp->stats.tx_packets++;
2201 + }
2202 + else {
2203 + lp->stats.tx_errors++;
2204 + lp->stats.tx_dropped++;
2205 +
2206 + /* underflow */
2207 + if (IS_TX_UND_ERR(devcs))
2208 + lp->stats.tx_fifo_errors++;
2209 +
2210 + /* oversized frame */
2211 + if (IS_TX_OF_ERR(devcs))
2212 + lp->stats.tx_aborted_errors++;
2213 +
2214 + /* excessive deferrals */
2215 + if (IS_TX_ED_ERR(devcs))
2216 + lp->stats.tx_carrier_errors++;
2217 +
2218 + /* collisions: medium busy */
2219 + if (IS_TX_EC_ERR(devcs))
2220 + lp->stats.collisions++;
2221 +
2222 + /* late collision */
2223 + if (IS_TX_LC_ERR(devcs))
2224 + lp->stats.tx_window_errors++;
2225 +
2226 + }
2227 +
2228 + /* We must always free the original skb */
2229 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2230 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2231 + lp->tx_skb[lp->tx_next_done] = NULL;
2232 + }
2233 +
2234 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2235 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2236 + lp->td_ring[lp->tx_next_done].link = 0;
2237 + lp->td_ring[lp->tx_next_done].ca = 0;
2238 + lp->tx_count --;
2239 +
2240 + /* go on to next transmission */
2241 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2242 + td = &lp->td_ring[lp->tx_next_done];
2243 +
2244 + }
2245 +
2246 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2247 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2248 +
2249 + /* Enable F E bit in Tx DMA */
2250 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2251 + spin_unlock_irqrestore(&lp->lock, flags);
2252 +
2253 +}
2254 +
2255 +
2256 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2257 +{
2258 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2259 + return &lp->stats;
2260 +}
2261 +
2262 +
2263 +/*
2264 + * Set or clear the multicast filter for this adaptor.
2265 + */
2266 +static void rc32434_multicast_list(struct net_device *dev)
2267 +{
2268 + /* listen to broadcasts always and to treat */
2269 + /* IFF bits independantly */
2270 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2271 + unsigned long flags;
2272 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2273 +
2274 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2275 + recognise |= ETHARC_pro_m;
2276 +
2277 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2278 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2279 + else if (dev->mc_count > 0) {
2280 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2281 + recognise |= ETHARC_am_m; /* for the time being */
2282 + }
2283 +
2284 + spin_lock_irqsave(&lp->lock, flags);
2285 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2286 + spin_unlock_irqrestore(&lp->lock, flags);
2287 +}
2288 +
2289 +
2290 +static void rc32434_tx_timeout(struct net_device *dev)
2291 +{
2292 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2293 + unsigned long flags;
2294 +
2295 + spin_lock_irqsave(&lp->lock, flags);
2296 + rc32434_restart(dev);
2297 + spin_unlock_irqrestore(&lp->lock, flags);
2298 +
2299 +}
2300 +
2301 +
2302 +/*
2303 + * Initialize the RC32434 ethernet controller.
2304 + */
2305 +static int rc32434_init(struct net_device *dev)
2306 +{
2307 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2308 + int i, j;
2309 +
2310 + /* Disable DMA */
2311 + rc32434_abort_tx(dev);
2312 + rc32434_abort_rx(dev);
2313 +
2314 + /* reset ethernet logic */
2315 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2316 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2317 + dev->trans_start = jiffies;
2318 +
2319 + /* Enable Ethernet Interface */
2320 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2321 +
2322 +#ifndef CONFIG_IDT_USE_NAPI
2323 + tasklet_disable(lp->rx_tasklet);
2324 +#endif
2325 + tasklet_disable(lp->tx_tasklet);
2326 +
2327 + /* Initialize the transmit Descriptors */
2328 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2329 + lp->td_ring[i].control = DMAD_iof_m;
2330 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2331 + lp->td_ring[i].ca = 0;
2332 + lp->td_ring[i].link = 0;
2333 + if (lp->tx_skb[i] != NULL) {
2334 + dev_kfree_skb_any(lp->tx_skb[i]);
2335 + lp->tx_skb[i] = NULL;
2336 + }
2337 + }
2338 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2339 + lp-> tx_chain_status = empty;
2340 +
2341 + /*
2342 + * Initialize the receive descriptors so that they
2343 + * become a circular linked list, ie. let the last
2344 + * descriptor point to the first again.
2345 + */
2346 + for (i=0; i<RC32434_NUM_RDS; i++) {
2347 + struct sk_buff *skb = lp->rx_skb[i];
2348 +
2349 + if (lp->rx_skb[i] == NULL) {
2350 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2351 + if (skb == NULL) {
2352 + ERR("No memory in the system\n");
2353 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2354 + if (lp->rx_skb[j] != NULL)
2355 + dev_kfree_skb_any(lp->rx_skb[j]);
2356 +
2357 + return 1;
2358 + }
2359 + else {
2360 + skb->dev = dev;
2361 + skb_reserve(skb, 2);
2362 + lp->rx_skb[i] = skb;
2363 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2364 +
2365 + }
2366 + }
2367 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2368 + lp->rd_ring[i].devcs = 0;
2369 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2370 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2371 +
2372 + }
2373 + /* loop back */
2374 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2375 + lp->rx_next_done = 0;
2376 +
2377 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2378 + lp->rx_chain_head = 0;
2379 + lp->rx_chain_tail = 0;
2380 + lp->rx_chain_status = empty;
2381 +
2382 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2383 + /* Start Rx DMA */
2384 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2385 +
2386 + /* Enable F E bit in Tx DMA */
2387 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2388 + /* Enable D H E bit in Rx DMA */
2389 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2390 +
2391 + /* Accept only packets destined for this Ethernet device address */
2392 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2393 +
2394 + /* Set all Ether station address registers to their initial values */
2395 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2396 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2397 +
2398 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2399 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2400 +
2401 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2402 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2403 +
2404 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2405 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2406 +
2407 +
2408 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2409 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2410 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2411 +
2412 + /* Back to back inter-packet-gap */
2413 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2414 + /* Non - Back to back inter-packet-gap */
2415 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2416 +
2417 + /* Management Clock Prescaler Divisor */
2418 + /* Clock independent setting */
2419 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2420 + &lp->eth_regs->ethmcp);
2421 +
2422 + /* don't transmit until fifo contains 48b */
2423 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2424 +
2425 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2426 +
2427 +#ifndef CONFIG_IDT_USE_NAPI
2428 + tasklet_enable(lp->rx_tasklet);
2429 +#endif
2430 + tasklet_enable(lp->tx_tasklet);
2431 +
2432 + netif_start_queue(dev);
2433 +
2434 +
2435 + return 0;
2436 +
2437 +}
2438 +
2439 +
2440 +#ifndef MODULE
2441 +
2442 +static int __init rc32434_setup(char *options)
2443 +{
2444 + /* no options yet */
2445 + return 1;
2446 +}
2447 +
2448 +static int __init rc32434_setup_ethaddr0(char *options)
2449 +{
2450 + memcpy(mac0, options, 17);
2451 + mac0[17]= '\0';
2452 + return 1;
2453 +}
2454 +
2455 +__setup("rc32434eth=", rc32434_setup);
2456 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2457 +
2458 +
2459 +#endif /* MODULE */
2460 +
2461 +module_init(rc32434_init_module);
2462 +module_exit(rc32434_cleanup_module);
2463 +
2464 +
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 +
2473 +
2474 +
2475 +
2476 +
2477 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2478 --- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2479 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2480 @@ -0,0 +1,187 @@
2481 +/**************************************************************************
2482 + *
2483 + * BRIEF MODULE DESCRIPTION
2484 + * Definitions for IDT RC32434 on-chip ethernet controller.
2485 + *
2486 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2487 + *
2488 + * This program is free software; you can redistribute it and/or modify it
2489 + * under the terms of the GNU General Public License as published by the
2490 + * Free Software Foundation; either version 2 of the License, or (at your
2491 + * option) any later version.
2492 + *
2493 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2494 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2495 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2496 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2497 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2498 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2499 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2500 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2501 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2502 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2503 + *
2504 + * You should have received a copy of the GNU General Public License along
2505 + * with this program; if not, write to the Free Software Foundation, Inc.,
2506 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2507 + *
2508 + *
2509 + **************************************************************************
2510 + * May 2004 rkt, neb
2511 + *
2512 + * Initial Release
2513 + *
2514 + * Aug 2004
2515 + *
2516 + * Added NAPI
2517 + *
2518 + **************************************************************************
2519 + */
2520 +
2521 +
2522 +#include <asm/idt-boards/rc32434/rc32434.h>
2523 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2524 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2525 +
2526 +#define RC32434_DEBUG 2
2527 +//#define RC32434_PROC_DEBUG
2528 +#undef RC32434_DEBUG
2529 +
2530 +#ifdef RC32434_DEBUG
2531 +
2532 +/* use 0 for production, 1 for verification, >2 for debug */
2533 +static int rc32434_debug = RC32434_DEBUG;
2534 +#define ASSERT(expr) \
2535 + if(!(expr)) { \
2536 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2537 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2538 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2539 +#else
2540 +#define ASSERT(expr) do {} while (0)
2541 +#define DBG(lvl, format, arg...) do {} while (0)
2542 +#endif
2543 +
2544 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2545 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2546 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2547 +
2548 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2549 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2550 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2551 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2552 +
2553 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2554 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2555 +
2556 +/* the following must be powers of two */
2557 +#ifdef CONFIG_IDT_USE_NAPI
2558 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2559 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2560 +#else
2561 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2562 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2563 +#endif
2564 +
2565 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2566 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2567 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2568 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2569 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2570 +
2571 +#define RC32434_TX_TIMEOUT HZ * 100
2572 +
2573 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2574 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2575 +
2576 +enum status { filled, empty};
2577 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2578 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2579 +
2580 +
2581 +/* Information that need to be kept for each board. */
2582 +struct rc32434_local {
2583 + ETH_t eth_regs;
2584 + DMA_Chan_t rx_dma_regs;
2585 + DMA_Chan_t tx_dma_regs;
2586 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2587 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2588 +
2589 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2590 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2591 +
2592 +#ifndef CONFIG_IDT_USE_NAPI
2593 + struct tasklet_struct * rx_tasklet;
2594 +#endif
2595 + struct tasklet_struct * tx_tasklet;
2596 +
2597 + int rx_next_done;
2598 + int rx_chain_head;
2599 + int rx_chain_tail;
2600 + enum status rx_chain_status;
2601 +
2602 + int tx_next_done;
2603 + int tx_chain_head;
2604 + int tx_chain_tail;
2605 + enum status tx_chain_status;
2606 + int tx_count;
2607 + int tx_full;
2608 +
2609 + struct timer_list mii_phy_timer;
2610 + unsigned long duplex_mode;
2611 +
2612 + int rx_irq;
2613 + int tx_irq;
2614 + int ovr_irq;
2615 + int und_irq;
2616 +
2617 + struct net_device_stats stats;
2618 + spinlock_t lock;
2619 +
2620 + /* debug /proc entry */
2621 + struct proc_dir_entry *ps;
2622 + int dma_halt_cnt; int dma_run_cnt;
2623 +};
2624 +
2625 +extern unsigned int idt_cpu_freq;
2626 +
2627 +/* Index to functions, as function prototypes. */
2628 +static int rc32434_open(struct net_device *dev);
2629 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2630 +static void rc32434_mii_handler(unsigned long data);
2631 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2632 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2633 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2634 +#ifdef RC32434_REVISION
2635 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2636 +#endif
2637 +static int rc32434_close(struct net_device *dev);
2638 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2639 +static void rc32434_multicast_list(struct net_device *dev);
2640 +static int rc32434_init(struct net_device *dev);
2641 +static void rc32434_tx_timeout(struct net_device *dev);
2642 +
2643 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2644 +#ifdef CONFIG_IDT_USE_NAPI
2645 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2646 +#else
2647 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2648 +#endif
2649 +static void rc32434_cleanup_module(void);
2650 +static int rc32434_probe(int port_num);
2651 +int rc32434_init_module(void);
2652 +
2653 +
2654 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2655 +{
2656 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2657 + rc32434_writel(0x10, &ch->dmac);
2658 +
2659 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2660 + dev->trans_start = jiffies;
2661 +
2662 + rc32434_writel(0, &ch->dmas);
2663 + }
2664 +
2665 + rc32434_writel(0, &ch->dmadptr);
2666 + rc32434_writel(0, &ch->dmandptr);
2667 +}
2668 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2669 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
2670 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
2671 @@ -218,6 +218,17 @@
2672 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2673 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2674
2675 +
2676 +/*
2677 + * Valid machtype for group ARUBA
2678 + */
2679 +#define MACH_GROUP_ARUBA 23
2680 +#define MACH_ARUBA_UNKNOWN 0
2681 +#define MACH_ARUBA_AP60 1
2682 +#define MACH_ARUBA_AP65 2
2683 +#define MACH_ARUBA_AP70 3
2684 +#define MACH_ARUBA_AP40 4
2685 +
2686 #define CL_SIZE COMMAND_LINE_SIZE
2687
2688 const char *get_system_type(void);
2689 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2690 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2691 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
2692 @@ -54,6 +54,9 @@
2693 #define PRID_IMP_R14000 0x0f00
2694 #define PRID_IMP_R8000 0x1000
2695 #define PRID_IMP_PR4450 0x1200
2696 +#define PRID_IMP_RC32334 0x1800
2697 +#define PRID_IMP_RC32355 0x1900
2698 +#define PRID_IMP_RC32365 0x1900
2699 #define PRID_IMP_R4600 0x2000
2700 #define PRID_IMP_R4700 0x2100
2701 #define PRID_IMP_TX39 0x2200
2702 @@ -200,7 +203,8 @@
2703 #define CPU_SB1A 62
2704 #define CPU_74K 63
2705 #define CPU_R14000 64
2706 -#define CPU_LAST 64
2707 +#define CPU_RC32300 65
2708 +#define CPU_LAST 65
2709
2710 /*
2711 * ISA Level encodings
2712 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2713 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2714 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
2715 @@ -0,0 +1,142 @@
2716 +/**************************************************************************
2717 + *
2718 + * BRIEF MODULE DESCRIPTION
2719 + * RC32300 helper routines
2720 + *
2721 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2722 + *
2723 + * This program is free software; you can redistribute it and/or modify it
2724 + * under the terms of the GNU General Public License as published by the
2725 + * Free Software Foundation; either version 2 of the License, or (at your
2726 + * option) any later version.
2727 + *
2728 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2729 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2730 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2731 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2732 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2733 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2734 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2735 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2736 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2737 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2738 + *
2739 + * You should have received a copy of the GNU General Public License along
2740 + * with this program; if not, write to the Free Software Foundation, Inc.,
2741 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2742 + *
2743 + *
2744 + **************************************************************************
2745 + * May 2004 P. Sadik.
2746 + *
2747 + * Initial Release
2748 + *
2749 + *
2750 + *
2751 + **************************************************************************
2752 + */
2753 +
2754 +#ifndef __IDT_RC32300_H__
2755 +#define __IDT_RC32300_H__
2756 +
2757 +#include <linux/delay.h>
2758 +#include <asm/io.h>
2759 +
2760 +
2761 +/* cpu pipeline flush */
2762 +static inline void rc32300_sync(void)
2763 +{
2764 + __asm__ volatile ("sync");
2765 +}
2766 +
2767 +static inline void rc32300_sync_udelay(int us)
2768 +{
2769 + __asm__ volatile ("sync");
2770 + udelay(us);
2771 +}
2772 +
2773 +static inline void rc32300_sync_delay(int ms)
2774 +{
2775 + __asm__ volatile ("sync");
2776 + mdelay(ms);
2777 +}
2778 +
2779 +/*
2780 + * Macros to access internal RC32300 registers. No byte
2781 + * swapping should be done when accessing the internal
2782 + * registers.
2783 + */
2784 +
2785 +static inline u8 rc32300_readb(unsigned long pa)
2786 +{
2787 + return *((volatile u8 *)KSEG1ADDR(pa));
2788 +}
2789 +static inline u16 rc32300_readw(unsigned long pa)
2790 +{
2791 + return *((volatile u16 *)KSEG1ADDR(pa));
2792 +}
2793 +static inline u32 rc32300_readl(unsigned long pa)
2794 +{
2795 + return *((volatile u32 *)KSEG1ADDR(pa));
2796 +}
2797 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2798 +{
2799 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2800 +}
2801 +static inline void rc32300_writew(u16 val, unsigned long pa)
2802 +{
2803 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2804 +}
2805 +static inline void rc32300_writel(u32 val, unsigned long pa)
2806 +{
2807 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2808 +}
2809 +
2810 +
2811 +#define local_readb __raw_readb
2812 +#define local_readw __raw_readw
2813 +#define local_readl __raw_readl
2814 +
2815 +#define local_writeb __raw_writeb
2816 +#define local_writew __raw_writew
2817 +#define local_writel __raw_writel
2818 +
2819 +
2820 +/*
2821 + * C access to CLZ and CLO instructions
2822 + * (count leading zeroes/ones).
2823 + */
2824 +static inline int rc32300_clz(unsigned long val)
2825 +{
2826 + int ret;
2827 + __asm__ volatile (
2828 + ".set\tnoreorder\n\t"
2829 + ".set\tnoat\n\t"
2830 + ".set\tmips32\n\t"
2831 + "clz\t%0,%1\n\t"
2832 + ".set\tmips0\n\t"
2833 + ".set\tat\n\t"
2834 + ".set\treorder"
2835 + : "=r" (ret)
2836 + : "r" (val));
2837 +
2838 + return ret;
2839 +}
2840 +static inline int rc32300_clo(unsigned long val)
2841 +{
2842 + int ret;
2843 + __asm__ volatile (
2844 + ".set\tnoreorder\n\t"
2845 + ".set\tnoat\n\t"
2846 + ".set\tmips32\n\t"
2847 + "clo\t%0,%1\n\t"
2848 + ".set\tmips0\n\t"
2849 + ".set\tat\n\t"
2850 + ".set\treorder"
2851 + : "=r" (ret)
2852 + : "r" (val));
2853 +
2854 + return ret;
2855 +}
2856 +
2857 +#endif // __IDT_RC32300_H__
2858 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2859 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2860 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
2861 @@ -0,0 +1,207 @@
2862 +/**************************************************************************
2863 + *
2864 + * BRIEF MODULE DESCRIPTION
2865 + * Definitions for IDT RC32334 CPU.
2866 + *
2867 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2868 + *
2869 + * This program is free software; you can redistribute it and/or modify it
2870 + * under the terms of the GNU General Public License as published by the
2871 + * Free Software Foundation; either version 2 of the License, or (at your
2872 + * option) any later version.
2873 + *
2874 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2875 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2876 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2877 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2878 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2879 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2880 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2881 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2882 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2883 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2884 + *
2885 + * You should have received a copy of the GNU General Public License along
2886 + * with this program; if not, write to the Free Software Foundation, Inc.,
2887 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2888 + *
2889 + *
2890 + **************************************************************************
2891 + * May 2004 P. Sadik.
2892 + *
2893 + * Initial Release
2894 + *
2895 + *
2896 + *
2897 + **************************************************************************
2898 + */
2899 +
2900 +
2901 +#ifndef __IDT_RC32334_H__
2902 +#define __IDT_RC32334_H__
2903 +
2904 +#include <linux/delay.h>
2905 +#include <asm/io.h>
2906 +
2907 +/* Base address of internal registers */
2908 +#define RC32334_REG_BASE 0x18000000
2909 +
2910 +/* CPU and IP Bus Control */
2911 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2912 +#define CPU_BTA 0xffffe204 // virtual!
2913 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2914 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2915 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2916 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2917 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2918 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2919 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2920 +
2921 +/* Memory Controller */
2922 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2923 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2924 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2925 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2926 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2927 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2928 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2929 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2930 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2931 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2932 +
2933 +/* PCI Controller */
2934 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2935 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2936 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2937 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2938 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2939 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2940 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2941 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2942 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2943 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2944 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2945 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2946 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2947 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2948 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2949 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2950 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2951 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2952 +
2953 +/* Timers */
2954 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2955 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2956 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2957 +#define TIMER_REG_OFFSET 0x10
2958 +
2959 +/* Programmable I/O */
2960 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2961 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2962 +
2963 +/*
2964 + * DMA
2965 + *
2966 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2967 + *
2968 + * DMA0: 18001400
2969 + * DMA1: 18001440
2970 + * DMA2: 18001900
2971 + * DMA3: 18001940
2972 + * NB: dma number must be immediate value or variable.
2973 + * It MUST NOT be a function since it would get called twice!
2974 + */
2975 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2976 +
2977 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2978 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2979 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2980 +
2981 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2982 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2983 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2984 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2985 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2986 +
2987 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2988 +
2989 +/* Expansion Interrupt Controller */
2990 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2991 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2992 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2993 +#define IC_GROUP_OFFSET 0x10
2994 +
2995 +#define NUM_INTR_GROUPS 15
2996 +/*
2997 + * The IRQ mapping is as follows:
2998 + *
2999 + * IRQ Mapped To
3000 + * --- -------------------
3001 + * 0 SW0 (IP0) SW0 intr
3002 + * 1 SW1 (IP1) SW1 intr
3003 + * 2 Int0 (IP2) board-specific
3004 + * 3 Int1 (IP3) board-specific
3005 + * 4 Int2 (IP4) board-specific
3006 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3007 + * 6 Int4 (IP6) board-specific
3008 + * 7 Int5 (IP7) CP0 Timer
3009 + *
3010 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3011 + * internally on the RC32334 is routed to the Expansion
3012 + * Interrupt Controller.
3013 + */
3014 +#define MIPS_CPU_TIMER_IRQ 7
3015 +
3016 +#define GROUP1_IRQ_BASE 8 // bus error
3017 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3018 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3019 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3020 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3021 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3022 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3023 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3024 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3025 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3026 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3027 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3028 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3029 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3030 +
3031 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3032 +
3033 +/* 16550 UARTs */
3034 +#ifdef __MIPSEB__
3035 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3036 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3037 +#else
3038 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3039 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3040 +#endif
3041 +
3042 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3043 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3044 +
3045 +#define IDT_CLOCK_MULT 2
3046 +
3047 +/* NVRAM */
3048 +#define NVRAM_BASE 0x12000000
3049 +#define NVRAM_ENVSIZE_OFF 4
3050 +#define NVRAM_ENVSTART_OFF 0x40
3051 +
3052 +/* LCD 4-digit display */
3053 +#define LCD_CLEAR 0x14000400
3054 +#define LCD_DIGIT0 0x1400000f
3055 +#define LCD_DIGIT1 0x14000008
3056 +#define LCD_DIGIT2 0x14000007
3057 +#define LCD_DIGIT3 0x14000003
3058 +
3059 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3060 +#define RC32334_SCC8530_IRQ 2
3061 +#define RC32334_PCI_INTA_IRQ 3
3062 +#define RC32334_PCI_INTB_IRQ 4
3063 +#define RC32334_PCI_INTC_IRQ 6
3064 +#define RC32334_PCI_INTD_IRQ 7
3065 +
3066 +#define RAM_SIZE (32*1024*1024)
3067 +
3068 +#endif // __IDT_RC32334_H__
3069 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3070 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3071 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3072 @@ -0,0 +1,206 @@
3073 +/**************************************************************************
3074 + *
3075 + * BRIEF MODULE DESCRIPTION
3076 + * DMA controller defines on IDT RC32355
3077 + *
3078 + * Copyright 2004 IDT Inc.
3079 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3080 + *
3081 + *
3082 + * This program is free software; you can redistribute it and/or modify it
3083 + * under the terms of the GNU General Public License as published by the
3084 + * Free Software Foundation; either version 2 of the License, or (at your
3085 + * option) any later version.
3086 + *
3087 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3088 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3089 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3090 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3091 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3092 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3093 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3094 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3095 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3096 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3097 + *
3098 + * You should have received a copy of the GNU General Public License along
3099 + * with this program; if not, write to the Free Software Foundation, Inc.,
3100 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3101 + *
3102 + *
3103 + * May 2004 rkt
3104 + * Initial Release
3105 + *
3106 + **************************************************************************
3107 + */
3108 +
3109 +#ifndef BANYAN_DMA_H
3110 +#define BANYAN_DMA_H
3111 +#include <asm/idt-boards/rc32300/rc32300.h>
3112 +
3113 +/*
3114 + * An image of one RC32355 dma channel registers
3115 + */
3116 +typedef struct {
3117 + u32 dmac;
3118 + u32 dmas;
3119 + u32 dmasm;
3120 + u32 dmadptr;
3121 + u32 dmandptr;
3122 +} rc32355_dma_ch_t;
3123 +
3124 +/*
3125 + * An image of all RC32355 dma channel registers
3126 + */
3127 +typedef struct {
3128 + rc32355_dma_ch_t ch[16];
3129 +} rc32355_dma_regs_t;
3130 +
3131 +
3132 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3133 +
3134 +
3135 +/* DMAC register layout */
3136 +
3137 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3138 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3139 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3140 +
3141 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3142 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3143 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3144 +
3145 +/* DMAS and DMASM register layout */
3146 +
3147 +#define DMAS_F 0x01 /* Finished */
3148 +#define DMAS_D 0x02 /* Done */
3149 +#define DMAS_C 0x04 /* Chain */
3150 +#define DMAS_E 0x08 /* Error */
3151 +#define DMAS_H 0x10 /* Halt */
3152 +
3153 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3154 +#define DMA_HALT_TIMEOUT 500
3155 +
3156 +
3157 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3158 +{
3159 + int timeout=1;
3160 +
3161 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3162 + local_writel(0, &ch->dmac);
3163 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3164 + if (local_readl(&ch->dmas) & DMAS_H) {
3165 + local_writel(0, &ch->dmas);
3166 + break;
3167 + }
3168 + }
3169 + }
3170 +
3171 + return timeout ? 0 : 1;
3172 +}
3173 +
3174 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3175 +{
3176 + local_writel(0, &ch->dmandptr);
3177 + local_writel(dma_addr, &ch->dmadptr);
3178 +}
3179 +
3180 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3181 +{
3182 + local_writel(dma_addr, &ch->dmandptr);
3183 +}
3184 +
3185 +
3186 +/* The following can be used to describe DMA channels 0 to 15, and the */
3187 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3188 +
3189 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3190 +
3191 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3192 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3193 +
3194 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3195 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3196 +
3197 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3198 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3199 +
3200 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3201 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3202 +
3203 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3204 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3205 +#define DMA_DEV_ATMVCC(entry) 0
3206 +
3207 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3208 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3209 +
3210 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3211 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3212 +
3213 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3214 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3215 +
3216 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3217 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3218 +
3219 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3220 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3221 +
3222 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3223 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3224 +
3225 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3226 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3227 +
3228 +#define DMA_CHAN_USBIN 13 /* USB input */
3229 +#define DMA_DEV_USBIN 0 /* USB input */
3230 +
3231 +#define DMA_CHAN_USBOUT 14 /* USB output */
3232 +#define DMA_DEV_USBOUT 0 /* USB output */
3233 +
3234 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3235 +#define DMA_DEV_EXTERN 0 /* External DMA */
3236 +
3237 +/*
3238 + * An RC32355 dma descriptor in system memory
3239 + */
3240 +typedef struct {
3241 + u32 cmdstat; /* control and status */
3242 + u32 curr_addr; /* current address of data */
3243 + u32 devcs; /* peripheral-specific control and status */
3244 + u32 link; /* link to next descriptor */
3245 +} rc32355_dma_desc_t;
3246 +
3247 +/* Values for the descriptor cmdstat word */
3248 +
3249 +#define DMADESC_F 0x80000000u /* Finished bit */
3250 +#define DMADESC_D 0x40000000u /* Done bit */
3251 +#define DMADESC_T 0x20000000u /* Terminated bit */
3252 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3253 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3254 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3255 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3256 +
3257 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3258 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3259 +
3260 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3261 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3262 +
3263 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3264 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3265 +
3266 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3267 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3268 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3269 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3270 +
3271 +#define DMA_DEVCMD(devcmd) \
3272 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3273 +#define DMA_DS(ds) \
3274 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3275 +#define DMA_COUNT(count) \
3276 + ((count) & DMADESC_COUNT_MASK)
3277 +
3278 +#endif /* RC32355_DMA_H */
3279 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3280 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3281 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3282 @@ -0,0 +1,442 @@
3283 +/**************************************************************************
3284 + *
3285 + * BRIEF MODULE DESCRIPTION
3286 + * Ethernet registers on IDT RC32355
3287 + *
3288 + * Copyright 2004 IDT Inc.
3289 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3290 + *
3291 + *
3292 + * This program is free software; you can redistribute it and/or modify it
3293 + * under the terms of the GNU General Public License as published by the
3294 + * Free Software Foundation; either version 2 of the License, or (at your
3295 + * option) any later version.
3296 + *
3297 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3298 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3299 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3300 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3301 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3302 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3303 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3304 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3305 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3306 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3307 + *
3308 + * You should have received a copy of the GNU General Public License along
3309 + * with this program; if not, write to the Free Software Foundation, Inc.,
3310 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3311 + *
3312 + *
3313 + * May 2004 rkt
3314 + * Initial Release
3315 + *
3316 + **************************************************************************
3317 + */
3318 +
3319 +
3320 +#ifndef RC32355_ETHER_H
3321 +#define RC32355_ETHER_H
3322 +
3323 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3324 +
3325 +/*
3326 + * A partial image of the RC32355 ethernet registers
3327 + */
3328 +typedef struct {
3329 + u32 ethintfc;
3330 + u32 ethfifott;
3331 + u32 etharc;
3332 + u32 ethhash0;
3333 + u32 ethhash1;
3334 + u32 ethfifost;
3335 + u32 ethfifos;
3336 + u32 ethodeops;
3337 + u32 ethis;
3338 + u32 ethos;
3339 + u32 ethmcp;
3340 + u32 _u1;
3341 + u32 ethid;
3342 + u32 _u2;
3343 + u32 _u3;
3344 + u32 _u4;
3345 + u32 ethod;
3346 + u32 _u5;
3347 + u32 _u6;
3348 + u32 _u7;
3349 + u32 ethodeop;
3350 + u32 _u8[43];
3351 + u32 ethsal0;
3352 + u32 ethsah0;
3353 + u32 ethsal1;
3354 + u32 ethsah1;
3355 + u32 ethsal2;
3356 + u32 ethsah2;
3357 + u32 ethsal3;
3358 + u32 ethsah3;
3359 + u32 ethrbc;
3360 + u32 ethrpc;
3361 + u32 ethrupc;
3362 + u32 ethrfc;
3363 + u32 ethtbc;
3364 + u32 ethgpf;
3365 + u32 _u9[50];
3366 + u32 ethmac1;
3367 + u32 ethmac2;
3368 + u32 ethipgt;
3369 + u32 ethipgr;
3370 + u32 ethclrt;
3371 + u32 ethmaxf;
3372 + u32 _u10;
3373 + u32 ethmtest;
3374 + u32 miimcfg;
3375 + u32 miimcmd;
3376 + u32 miimaddr;
3377 + u32 miimwtd;
3378 + u32 miimrdd;
3379 + u32 miimind;
3380 + u32 _u11;
3381 + u32 _u12;
3382 + u32 ethcfsa0;
3383 + u32 ethcfsa1;
3384 + u32 ethcfsa2;
3385 +} rc32355_eth_regs_t;
3386 +
3387 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3388 +
3389 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3390 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3391 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3392 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3393 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3394 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3395 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3396 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3397 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3398 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3399 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3400 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3401 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3402 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3403 +
3404 +/* for n in { 0, 1, 2, 3 } */
3405 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3406 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3407 +
3408 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3409 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3410 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3411 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3412 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3413 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3414 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3415 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3416 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3417 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3418 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3419 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3420 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3421 +
3422 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3423 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3424 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3425 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3426 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3427 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3428 +
3429 +/* for n in { 0, 1, 2 } */
3430 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3431 +
3432 +
3433 +/*
3434 + * Register Interpretations follow
3435 + */
3436 +
3437 +/******************************************************************************
3438 + * ETHINTFC register
3439 + *****************************************************************************/
3440 +
3441 +#define ETHERINTFC_EN (1<<0)
3442 +#define ETHERINTFC_ITS (1<<1)
3443 +#define ETHERINTFC_RES (1<<2)
3444 +#define ETHERINTFC_RIP (1<<2)
3445 +#define ETHERINTFC_JAM (1<<3)
3446 +
3447 +/******************************************************************************
3448 + * ETHFIFOTT register
3449 + *****************************************************************************/
3450 +
3451 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3452 +
3453 +/******************************************************************************
3454 + * ETHARC register
3455 + *****************************************************************************/
3456 +
3457 +#define ETHERARC_PRO (1<<0)
3458 +#define ETHERARC_AM (1<<1)
3459 +#define ETHERARC_AFM (1<<2)
3460 +#define ETHERARC_AB (1<<3)
3461 +
3462 +/******************************************************************************
3463 + * ETHHASH registers
3464 + *****************************************************************************/
3465 +
3466 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3467 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3468 +
3469 +/******************************************************************************
3470 + * ETHSA registers
3471 + *****************************************************************************/
3472 +
3473 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3474 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3475 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3476 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3477 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3478 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3479 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3480 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3481 +
3482 +/******************************************************************************
3483 + * ETHFIFOST register
3484 + *****************************************************************************/
3485 +
3486 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3487 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3488 +
3489 +/******************************************************************************
3490 + * ETHFIFOS register
3491 + *****************************************************************************/
3492 +
3493 +#define ETHERFIFOS_IR (1<<0)
3494 +#define ETHERFIFOS_OR (1<<1)
3495 +#define ETHERFIFOS_OVR (1<<2)
3496 +#define ETHERFIFOS_UND (1<<3)
3497 +
3498 +/******************************************************************************
3499 + * DATA registers
3500 + *****************************************************************************/
3501 +
3502 +#define ETHERID(v) (((v)&0xffff)<<0)
3503 +#define ETHEROD(v) (((v)&0xffff)<<0)
3504 +
3505 +/******************************************************************************
3506 + * ETHODEOPS register
3507 + *****************************************************************************/
3508 +
3509 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3510 +
3511 +/******************************************************************************
3512 + * ETHODEOP register
3513 + *****************************************************************************/
3514 +
3515 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3516 +
3517 +/******************************************************************************
3518 + * ETHIS register
3519 + *****************************************************************************/
3520 +
3521 +#define ETHERIS_EOP (1<<0)
3522 +#define ETHERIS_ROK (1<<2)
3523 +#define ETHERIS_FM (1<<3)
3524 +#define ETHERIS_MP (1<<4)
3525 +#define ETHERIS_BP (1<<5)
3526 +#define ETHERIS_VLT (1<<6)
3527 +#define ETHERIS_CF (1<<7)
3528 +#define ETHERIS_OVR (1<<8)
3529 +#define ETHERIS_CRC (1<<9)
3530 +#define ETHERIS_CV (1<<10)
3531 +#define ETHERIS_DB (1<<11)
3532 +#define ETHERIS_LE (1<<12)
3533 +#define ETHERIS_LOR (1<<13)
3534 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3535 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3536 +
3537 +/******************************************************************************
3538 + * ETHOS register
3539 + *****************************************************************************/
3540 +
3541 +#define ETHEROS_T (1<<0)
3542 +#define ETHEROS_TOK (1<<6)
3543 +#define ETHEROS_MP (1<<7)
3544 +#define ETHEROS_BP (1<<8)
3545 +#define ETHEROS_UND (1<<9)
3546 +#define ETHEROS_OF (1<<10)
3547 +#define ETHEROS_ED (1<<11)
3548 +#define ETHEROS_EC (1<<12)
3549 +#define ETHEROS_LC (1<<13)
3550 +#define ETHEROS_TD (1<<14)
3551 +#define ETHEROS_CRC (1<<15)
3552 +#define ETHEROS_LE (1<<16)
3553 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3554 +#define ETHEROS_PFD (1<<21)
3555 +
3556 +/******************************************************************************
3557 + * Statistics registers
3558 + *****************************************************************************/
3559 +
3560 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3561 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3562 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3563 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3564 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3565 +
3566 +/******************************************************************************
3567 + * ETHGPF register
3568 + *****************************************************************************/
3569 +
3570 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3571 +
3572 +/******************************************************************************
3573 + * MAC registers
3574 + *****************************************************************************/
3575 +//ETHMAC1
3576 +#define ETHERMAC1_RE (1<<0)
3577 +#define ETHERMAC1_PAF (1<<1)
3578 +#define ETHERMAC1_RFC (1<<2)
3579 +#define ETHERMAC1_TFC (1<<3)
3580 +#define ETHERMAC1_LB (1<<4)
3581 +#define ETHERMAC1_MR (1<<15)
3582 +
3583 +//ETHMAC2
3584 +#define ETHERMAC2_FD (1<<0)
3585 +#define ETHERMAC2_FLC (1<<1)
3586 +#define ETHERMAC2_HFE (1<<2)
3587 +#define ETHERMAC2_DC (1<<3)
3588 +#define ETHERMAC2_CEN (1<<4)
3589 +#define ETHERMAC2_PE (1<<5)
3590 +#define ETHERMAC2_VPE (1<<6)
3591 +#define ETHERMAC2_APE (1<<7)
3592 +#define ETHERMAC2_PPE (1<<8)
3593 +#define ETHERMAC2_LPE (1<<9)
3594 +#define ETHERMAC2_NB (1<<12)
3595 +#define ETHERMAC2_BP (1<<13)
3596 +#define ETHERMAC2_ED (1<<14)
3597 +
3598 +//ETHIPGT
3599 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3600 +
3601 +//ETHIPGR
3602 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3603 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3604 +
3605 +//ETHCLRT
3606 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3607 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3608 +
3609 +//ETHMAXF
3610 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3611 +
3612 +//ETHMTEST
3613 +#define ETHERMTEST_TB (1<<2)
3614 +
3615 +//ETHMCP
3616 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3617 +
3618 +//MIIMCFG
3619 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3620 +#define ETHERMIIMCFG_R (1<<15)
3621 +
3622 +//MIIMCMD
3623 +#define ETHERMIIMCMD_RD (1<<0)
3624 +#define ETHERMIIMCMD_SCN (1<<1)
3625 +
3626 +//MIIMADDR
3627 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3628 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3629 +
3630 +//MIIMWTD
3631 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3632 +
3633 +//MIIMRDD
3634 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3635 +
3636 +//MIIMIND
3637 +#define ETHERMIIMIND_BSY (1<<0)
3638 +#define ETHERMIIMIND_SCN (1<<1)
3639 +#define ETHERMIIMIND_NV (1<<2)
3640 +
3641 +//DMA DEVCS IN
3642 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3643 +#define ETHERDMA_IN_CES (1<<14)
3644 +#define ETHERDMA_IN_LOR (1<<13)
3645 +#define ETHERDMA_IN_LE (1<<12)
3646 +#define ETHERDMA_IN_DB (1<<11)
3647 +#define ETHERDMA_IN_CV (1<<10)
3648 +#define ETHERDMA_IN_CRC (1<<9)
3649 +#define ETHERDMA_IN_OVR (1<<8)
3650 +#define ETHERDMA_IN_CF (1<<7)
3651 +#define ETHERDMA_IN_VLT (1<<6)
3652 +#define ETHERDMA_IN_BP (1<<5)
3653 +#define ETHERDMA_IN_MP (1<<4)
3654 +#define ETHERDMA_IN_FM (1<<3)
3655 +#define ETHERDMA_IN_ROK (1<<2)
3656 +#define ETHERDMA_IN_LD (1<<1)
3657 +#define ETHERDMA_IN_FD (1<<0)
3658 +
3659 +//DMA DEVCS OUT
3660 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3661 +#define ETHERDMA_OUT_CNT 0x001e0000
3662 +#define ETHERDMA_OUT_SHFT 17
3663 +#define ETHERDMA_OUT_LE (1<<16)
3664 +
3665 +#define ETHERDMA_OUT_CRC (1<<15)
3666 +#define ETHERDMA_OUT_TD (1<<14)
3667 +#define ETHERDMA_OUT_LC (1<<13)
3668 +#define ETHERDMA_OUT_EC (1<<12)
3669 +#define ETHERDMA_OUT_ED (1<<11)
3670 +#define ETHERDMA_OUT_OF (1<<10)
3671 +#define ETHERDMA_OUT_UND (1<<9)
3672 +#define ETHERDMA_OUT_BP (1<<8)
3673 +#define ETHERDMA_OUT_MP (1<<7)
3674 +#define ETHERDMA_OUT_TOK (1<<6)
3675 +#define ETHERDMA_OUT_HEN (1<<5)
3676 +#define ETHERDMA_OUT_CEN (1<<4)
3677 +#define ETHERDMA_OUT_PEN (1<<3)
3678 +#define ETHERDMA_OUT_OEN (1<<2)
3679 +#define ETHERDMA_OUT_LD (1<<1)
3680 +#define ETHERDMA_OUT_FD (1<<0)
3681 +
3682 +#define RCV_ERRS \
3683 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3684 +#define TX_ERRS \
3685 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3686 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3687 +
3688 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3689 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3690 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3691 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3692 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3693 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3694 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3695 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3696 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3697 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3698 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3699 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3700 + Range */
3701 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3702 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3703 + received packet */
3704 +
3705 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3706 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3707 +
3708 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3709 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3710 + Underflow */
3711 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3712 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3713 + deferral */
3714 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3715 + collisions */
3716 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3717 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3718 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3719 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3720 +
3721 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3722 +
3723 +#endif /* RC32355_ETHER_H */
3724 +
3725 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3726 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3727 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-06-18 12:44:28.000000000 +0200
3728 @@ -0,0 +1,177 @@
3729 +/**************************************************************************
3730 + *
3731 + * BRIEF MODULE DESCRIPTION
3732 + * Definitions for IDT RC32355 CPU.
3733 + *
3734 + * Copyright 2004 IDT Inc.
3735 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3736 + *
3737 + *
3738 + * This program is free software; you can redistribute it and/or modify it
3739 + * under the terms of the GNU General Public License as published by the
3740 + * Free Software Foundation; either version 2 of the License, or (at your
3741 + * option) any later version.
3742 + *
3743 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3744 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3745 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3746 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3747 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3748 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3749 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3750 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3751 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3752 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3753 + *
3754 + * You should have received a copy of the GNU General Public License along
3755 + * with this program; if not, write to the Free Software Foundation, Inc.,
3756 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3757 + *
3758 + *
3759 + * May 2004 rkt
3760 + * Initial Release
3761 + *
3762 + **************************************************************************
3763 + */
3764 +
3765 +
3766 +#ifndef _RC32355_H_
3767 +#define _RC32355_H_
3768 +
3769 +#include <linux/delay.h>
3770 +#include <asm/io.h>
3771 +
3772 +/* Base address of internal registers */
3773 +#define RC32355_REG_BASE 0x18000000
3774 +
3775 +/* System ID Registers */
3776 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3777 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3778 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3779 +
3780 +/* Reset Controller */
3781 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3782 +
3783 +/* Device Controller */
3784 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3785 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3786 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3787 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3788 +#define DEV_REG_OFFSET 0x10
3789 +
3790 +/* SDRAM Controller */
3791 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3792 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3793 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3794 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3795 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3796 +
3797 +/* Bus Arbiter */
3798 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3799 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3800 +
3801 +/* Counters/Timers */
3802 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3803 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3804 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3805 +#define TIMER_REG_OFFSET 0x0C
3806 +
3807 +/* System Integrity */
3808 +
3809 +/* Interrupt Controller */
3810 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3811 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3812 +#define IC_GROUP_OFFSET 0x08
3813 +
3814 +#define NUM_INTR_GROUPS 5
3815 +/*
3816 + * The IRQ mapping is as follows:
3817 + *
3818 + * IRQ Mapped To
3819 + * --- -------------------
3820 + * 0 SW0 (IP0) SW0 intr
3821 + * 1 SW1 (IP1) SW1 intr
3822 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3823 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3824 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3825 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3826 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3827 + * 7 Int5 (IP7) CP0 Timer
3828 + *
3829 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3830 + * internally on the RC32355 is routed to the Expansion
3831 + * Interrupt Controller.
3832 + */
3833 +#define MIPS_CPU_TIMER_IRQ 7
3834 +
3835 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3836 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3837 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3838 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3839 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3840 +
3841 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3842 +
3843 +/* DMA - see rc32355_dma.h for full list of registers */
3844 +
3845 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3846 +#define DMA_CHAN_OFFSET 0x14
3847 +
3848 +/* GPIO Controller */
3849 +
3850 +/* TDM Bus */
3851 +
3852 +/* 16550 UARTs */
3853 +#ifdef __MIPSEB__
3854 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3855 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3856 +#else
3857 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3858 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3859 +#endif
3860 +
3861 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3862 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3863 +
3864 +/* ATM */
3865 +
3866 +/* Ethernet - see rc32355_eth.h for full list of registers */
3867 +
3868 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3869 +
3870 +
3871 +#define IDT_CLOCK_MULT 2
3872 +
3873 +/* Memory map of 79EB355 board */
3874 +
3875 +/* DRAM */
3876 +#define RAM_BASE 0x00000000
3877 +#define RAM_SIZE (32*1024*1024)
3878 +
3879 +/* SRAM (device 1) */
3880 +#define SRAM_BASE 0x02000000
3881 +#define SRAM_SIZE 0x00100000
3882 +
3883 +/* FLASH (device 2) */
3884 +#define FLASH_BASE 0x0C000000
3885 +#define FLASH_SIZE 0x00C00000
3886 +
3887 +/* ATM PHY (device 4) */
3888 +#define ATM_PHY_BASE 0x14000000
3889 +
3890 +/* TDM switch (device 3) */
3891 +#define TDM_BASE 0x1A000000
3892 +
3893 +/* LCD panel (device 3) */
3894 +#define LCD_BASE 0x1A002000
3895 +
3896 +/* RTC (DS1511W) (device 3) */
3897 +#define RTC_BASE 0x1A004000
3898 +
3899 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3900 +#define NVRAM_ADDR RTC_BASE + 0x10
3901 +#define NVRAM_DATA RTC_BASE + 0x13
3902 +#define NVRAM_ENVSIZE_OFF 4
3903 +#define NVRAM_ENVSTART_OFF 32
3904 +
3905 +#endif /* _RC32355_H_ */
3906 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3907 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3908 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
3909 @@ -0,0 +1,226 @@
3910 +/**************************************************************************
3911 + *
3912 + * BRIEF MODULE DESCRIPTION
3913 + * RC32365/336 DMA hardware abstraction.
3914 + *
3915 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3916 + *
3917 + * This program is free software; you can redistribute it and/or modify it
3918 + * under the terms of the GNU General Public License as published by the
3919 + * Free Software Foundation; either version 2 of the License, or (at your
3920 + * option) any later version.
3921 + *
3922 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3923 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3924 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3925 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3926 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3927 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3928 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3929 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3930 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3931 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3932 + *
3933 + * You should have received a copy of the GNU General Public License along
3934 + * with this program; if not, write to the Free Software Foundation, Inc.,
3935 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3936 + *
3937 + *
3938 + **************************************************************************
3939 + * May 2004 P. Sadik.
3940 + *
3941 + * Initial Release
3942 + *
3943 + *
3944 + *
3945 + **************************************************************************
3946 + */
3947 +
3948 +#ifndef __IDT_RC32365_DMA_H__
3949 +#define __IDT_RC32365_DMA_H__
3950 +
3951 +enum
3952 +{
3953 + DMA0_PhysicalAddress = 0x18038000,
3954 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3955 +
3956 + DMA0_VirtualAddress = 0xb8038000,
3957 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3958 +} ;
3959 +
3960 +/*
3961 + * DMA descriptor (in physical memory).
3962 + */
3963 +
3964 +typedef struct DMAD_s
3965 +{
3966 + u32 control ; // Control. use DMAD_*
3967 + u32 ca ; // Current Address.
3968 + u32 devcs ; // Device control and status.
3969 + u32 link ; // Next descriptor in chain.
3970 +} volatile *DMAD_t ;
3971 +
3972 +enum
3973 +{
3974 + DMAD_size = sizeof (struct DMAD_s),
3975 + DMAD_count_b = 0, // in DMAD_t -> control
3976 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3977 + DMAD_ds_b = 20, // in DMAD_t -> control
3978 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3979 + DMAD_ds_extToMem0_v = 0,
3980 + DMAD_ds_memToExt0_v = 1,
3981 + DMAD_ds_extToMem1_v = 0,
3982 + DMAD_ds_memToExt1_v = 1,
3983 + DMAD_ds_ethRcv0_v = 0,
3984 + DMAD_ds_ethXmt0_v = 0,
3985 + DMAD_ds_ethRcv1_v = 0,
3986 + DMAD_ds_ethXmt2_v = 0,
3987 + DMAD_ds_memToFifo_v = 0,
3988 + DMAD_ds_fifoToMem_v = 0,
3989 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3990 + DMAD_ds_pciToMem_v = 0,
3991 + DMAD_ds_memToPci_v = 0,
3992 + DMAD_ds_securityInput_v = 0,
3993 + DMAD_ds_securityOutput_v = 0,
3994 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3995 +
3996 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3997 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
3998 + DMAD_devcmd_byte_v = 0, //memory-to-memory
3999 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
4000 + DMAD_devcmd_word_v = 2, //memory-to-memory
4001 + DMAD_devcmd_2words_v = 3, //memory-to-memory
4002 + DMAD_devcmd_4words_v = 4, //memory-to-memory
4003 + DMAD_devcmd_6words_v = 5, //memory-to-memory
4004 + DMAD_devcmd_8words_v = 6, //memory-to-memory
4005 + DMAD_devcmd_16words_v = 7, //memory-to-memory
4006 + DMAD_cof_b = 25, // chain on finished
4007 + DMAD_cof_m = 0x02000000, //
4008 + DMAD_cod_b = 26, // chain on done
4009 + DMAD_cod_m = 0x04000000, //
4010 + DMAD_iof_b = 27, // interrupt on finished
4011 + DMAD_iof_m = 0x08000000, //
4012 + DMAD_iod_b = 28, // interrupt on done
4013 + DMAD_iod_m = 0x10000000, //
4014 + DMAD_t_b = 29, // terminated
4015 + DMAD_t_m = 0x20000000, //
4016 + DMAD_d_b = 30, // done
4017 + DMAD_d_m = 0x40000000, //
4018 + DMAD_f_b = 31, // finished
4019 + DMAD_f_m = 0x80000000, //
4020 +} ;
4021 +
4022 +/*
4023 + * DMA register (within Internal Register Map).
4024 + */
4025 +
4026 +struct DMA_Chan_s
4027 +{
4028 + u32 dmac ; // Control.
4029 + u32 dmas ; // Status.
4030 + u32 dmasm ; // Mask.
4031 + u32 dmadptr ; // Descriptor pointer.
4032 + u32 dmandptr ; // Next descriptor pointer.
4033 +};
4034 +
4035 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4036 +
4037 +//DMA_Channels use DMACH_count instead
4038 +
4039 +enum
4040 +{
4041 + DMAC_run_b = 0, //
4042 + DMAC_run_m = 0x00000001, //
4043 + DMAC_dm_b = 1, // done mask
4044 + DMAC_dm_m = 0x00000002, //
4045 + DMAC_mode_b = 2, //
4046 + DMAC_mode_m = 0x0000000c, //
4047 + DMAC_mode_auto_v = 0,
4048 + DMAC_mode_burst_v = 1,
4049 + DMAC_mode_transfer_v = 2, //usually used
4050 + DMAC_mode_reserved_v = 3,
4051 + DMAC_a_b = 4, //
4052 + DMAC_a_m = 0x00000010, //
4053 +
4054 + DMAS_f_b = 0, // finished (sticky)
4055 + DMAS_f_m = 0x00000001, //
4056 + DMAS_d_b = 1, // done (sticky)
4057 + DMAS_d_m = 0x00000002, //
4058 + DMAS_c_b = 2, // chain (sticky)
4059 + DMAS_c_m = 0x00000004, //
4060 + DMAS_e_b = 3, // error (sticky)
4061 + DMAS_e_m = 0x00000008, //
4062 + DMAS_h_b = 4, // halt (sticky)
4063 + DMAS_h_m = 0x00000010, //
4064 +
4065 + DMASM_f_b = 0, // finished (1=mask)
4066 + DMASM_f_m = 0x00000001, //
4067 + DMASM_d_b = 1, // done (1=mask)
4068 + DMASM_d_m = 0x00000002, //
4069 + DMASM_c_b = 2, // chain (1=mask)
4070 + DMASM_c_m = 0x00000004, //
4071 + DMASM_e_b = 3, // error (1=mask)
4072 + DMASM_e_m = 0x00000008, //
4073 + DMASM_h_b = 4, // halt (1=mask)
4074 + DMASM_h_m = 0x00000010, //
4075 +} ;
4076 +
4077 +/*
4078 + * DMA channel definitions
4079 + */
4080 +
4081 +enum
4082 +{
4083 + DMACH_ethRcv0 = 0,
4084 + DMACH_ethXmt0 = 1,
4085 + DMACH_ethRcv1 = 2,
4086 + DMACH_ethXmt2 = 3,
4087 + DMACH_pciToMem = 4,
4088 + DMACH_memToPci = 5,
4089 + DMACH_securityInput = 6,
4090 + DMACH_securityOutput = 7,
4091 + DMACH_rng = 8,
4092 +
4093 + DMACH_count //must be last
4094 +};
4095 +
4096 +
4097 +typedef struct DMAC_s
4098 +{
4099 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4100 +} volatile *DMA_t ;
4101 +
4102 +
4103 +/*
4104 + * External DMA parameters
4105 +*/
4106 +
4107 +enum
4108 +{
4109 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4110 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4111 + DMADEVCMD_ts_byte_v = 0,
4112 + DMADEVCMD_ts_halfword_v = 1,
4113 + DMADEVCMD_ts_word_v = 2,
4114 + DMADEVCMD_ts_2word_v = 3,
4115 + DMADEVCMD_ts_4word_v = 4,
4116 + DMADEVCMD_ts_6word_v = 5,
4117 + DMADEVCMD_ts_8word_v = 6,
4118 + DMADEVCMD_ts_16word_v = 7
4119 +};
4120 +
4121 +
4122 +#if 1 // aws - Compatibility.
4123 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4124 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4125 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4126 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4127 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4128 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4129 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4130 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4131 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4132 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4133 +#endif // aws - Compatibility.
4134 +
4135 +#endif // __IDT_RC32365_DMA_H__
4136 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4137 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4138 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-06-18 12:44:28.000000000 +0200
4139 @@ -0,0 +1,86 @@
4140 +/**************************************************************************
4141 + *
4142 + * BRIEF MODULE DESCRIPTION
4143 + * RC32365/336 DMA interface routines.
4144 + *
4145 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4146 + *
4147 + * This program is free software; you can redistribute it and/or modify it
4148 + * under the terms of the GNU General Public License as published by the
4149 + * Free Software Foundation; either version 2 of the License, or (at your
4150 + * option) any later version.
4151 + *
4152 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4153 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4154 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4155 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4156 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4157 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4158 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4159 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4160 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4161 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4162 + *
4163 + * You should have received a copy of the GNU General Public License along
4164 + * with this program; if not, write to the Free Software Foundation, Inc.,
4165 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4166 + *
4167 + *
4168 + **************************************************************************
4169 + * May 2004 P. Sadik.
4170 + *
4171 + * Initial Release
4172 + *
4173 + *
4174 + *
4175 + **************************************************************************
4176 + */
4177 +
4178 +#ifndef __IDT_RC32365_DMA_V_H__
4179 +#define __IDT_RC32365_DMA_V_H__
4180 +
4181 +
4182 +#include <asm/idt-boards/rc32300/rc32300.h>
4183 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4184 +#include <asm/idt-boards/rc32300/rc32365.h>
4185 +
4186 +#define DMA_CHAN_OFFSET 0x14
4187 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4188 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4189 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4190 +
4191 +#define DMA_COUNT(count) \
4192 + ((count) & DMAD_count_m)
4193 +
4194 +#define DMA_HALT_TIMEOUT 500
4195 +
4196 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4197 +{
4198 + int timeout=1;
4199 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4200 + local_writel(0, &ch->dmac);
4201 +
4202 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4203 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4204 + local_writel(0, &ch->dmas);
4205 + break;
4206 + }
4207 + }
4208 +
4209 + }
4210 +
4211 + return timeout ? 0 : 1;
4212 +}
4213 +
4214 +
4215 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4216 +{
4217 + local_writel(0, &ch->dmandptr);
4218 + local_writel(dma_addr, &ch->dmadptr);
4219 +}
4220 +
4221 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4222 +{
4223 + local_writel(dma_addr, &ch->dmandptr);
4224 +}
4225 +#endif //__IDT_RC32365_DMA_V_H__
4226 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4227 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4228 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
4229 @@ -0,0 +1,344 @@
4230 +/**************************************************************************
4231 + *
4232 + * BRIEF MODULE DESCRIPTION
4233 + * RC32365/336 Ethernet hardware abstraction.
4234 + *
4235 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4236 + *
4237 + * This program is free software; you can redistribute it and/or modify it
4238 + * under the terms of the GNU General Public License as published by the
4239 + * Free Software Foundation; either version 2 of the License, or (at your
4240 + * option) any later version.
4241 + *
4242 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4243 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4244 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4245 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4246 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4247 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4248 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4249 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4250 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4251 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4252 + *
4253 + * You should have received a copy of the GNU General Public License along
4254 + * with this program; if not, write to the Free Software Foundation, Inc.,
4255 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4256 + *
4257 + *
4258 + **************************************************************************
4259 + * May 2004 P. Sadik.
4260 + *
4261 + * Initial Release
4262 + *
4263 + *
4264 + *
4265 + **************************************************************************
4266 + */
4267 +
4268 +#ifndef __IDT_RC32365_ETH_H__
4269 +#define __IDT_RC32365_ETH_H__
4270 +
4271 +enum
4272 +{
4273 + ETH0_PhysicalAddress = 0x18058000,
4274 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4275 + ETH0_VirtualAddress = 0xb8058000,
4276 +
4277 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4278 +
4279 + ETH1_PhysicalAddress = 0x18060000,
4280 + ETH1_VirtualAddress = 0xb8060000, // Default
4281 +} ;
4282 +
4283 +typedef struct
4284 +{
4285 + u32 ethintfc ;
4286 + u32 ethfifott ;
4287 + u32 etharc ;
4288 + u32 ethhash0 ;
4289 + u32 ethhash1 ;
4290 + u32 ethu0 [4] ; // Reserved.
4291 + u32 ethpfs ;
4292 + u32 ethmcp ;
4293 + u32 eth_u1 [10] ; // Reserved.
4294 + u32 ethspare ;
4295 + u32 eth_u2 [42] ; // Reserved.
4296 + u32 ethsal0 ;
4297 + u32 ethsah0 ;
4298 + u32 ethsal1 ;
4299 + u32 ethsah1 ;
4300 + u32 ethsal2 ;
4301 + u32 ethsah2 ;
4302 + u32 ethsal3 ;
4303 + u32 ethsah3 ;
4304 + u32 ethrbc ;
4305 + u32 ethrpc ;
4306 + u32 ethrupc ;
4307 + u32 ethrfc ;
4308 + u32 ethtbc ;
4309 + u32 ethgpf ;
4310 + u32 eth_u9 [50] ; // Reserved.
4311 + u32 ethmac1 ;
4312 + u32 ethmac2 ;
4313 + u32 ethipgt ;
4314 + u32 ethipgr ;
4315 + u32 ethclrt ;
4316 + u32 ethmaxf ;
4317 + u32 eth_u10 ; // Reserved.
4318 + u32 ethmtest ;
4319 + u32 miimcfg ;
4320 + u32 miimcmd ;
4321 + u32 miimaddr ;
4322 + u32 miimwtd ;
4323 + u32 miimrdd ;
4324 + u32 miimind ;
4325 + u32 eth_u11 ; // Reserved.
4326 + u32 eth_u12 ; // Reserved.
4327 + u32 ethcfsa0 ;
4328 + u32 ethcfsa1 ;
4329 + u32 ethcfsa2 ;
4330 +} volatile *ETH_t;
4331 +
4332 +enum
4333 +{
4334 + ETHINTFC_en_b = 0,
4335 + ETHINTFC_en_m = 0x00000001,
4336 + ETHINTFC_its_b = 1,
4337 + ETHINTFC_its_m = 0x00000002,
4338 + ETHINTFC_rip_b = 2,
4339 + ETHINTFC_rip_m = 0x00000004,
4340 + ETHINTFC_jam_b = 3,
4341 + ETHINTFC_jam_m = 0x00000008,
4342 + ETHINTFC_ovr_b = 4,
4343 + ETHINTFC_ovr_m = 0x00000010,
4344 + ETHINTFC_und_b = 5,
4345 + ETHINTFC_und_m = 0x00000020,
4346 +
4347 + ETHFIFOTT_tth_b = 0,
4348 + ETHFIFOTT_tth_m = 0x0000007f,
4349 +
4350 + ETHARC_pro_b = 0,
4351 + ETHARC_pro_m = 0x00000001,
4352 + ETHARC_am_b = 1,
4353 + ETHARC_am_m = 0x00000002,
4354 + ETHARC_afm_b = 2,
4355 + ETHARC_afm_m = 0x00000004,
4356 + ETHARC_ab_b = 3,
4357 + ETHARC_ab_m = 0x00000008,
4358 +
4359 + ETHSAL_byte5_b = 0,
4360 + ETHSAL_byte5_m = 0x000000ff,
4361 + ETHSAL_byte4_b = 8,
4362 + ETHSAL_byte4_m = 0x0000ff00,
4363 + ETHSAL_byte3_b = 16,
4364 + ETHSAL_byte3_m = 0x00ff0000,
4365 + ETHSAL_byte2_b = 24,
4366 + ETHSAL_byte2_m = 0xff000000,
4367 +
4368 + ETHSAH_byte1_b = 0,
4369 + ETHSAH_byte1_m = 0x000000ff,
4370 + ETHSAH_byte0_b = 8,
4371 + ETHSAH_byte0_m = 0x0000ff00,
4372 +
4373 + ETHGPF_ptv_b = 0,
4374 + ETHGPF_ptv_m = 0x0000ffff,
4375 +
4376 + ETHPFS_pfd_b = 0,
4377 + ETHPFS_pfd_m = 0x00000001,
4378 +
4379 + ETHCFSA0_cfsa4_b = 0,
4380 + ETHCFSA0_cfsa4_m = 0x000000ff,
4381 + ETHCFSA0_cfsa5_b = 8,
4382 + ETHCFSA0_cfsa5_m = 0x0000ff00,
4383 +
4384 + ETHCFSA1_cfsa2_b = 0,
4385 + ETHCFSA1_cfsa2_m = 0x000000ff,
4386 + ETHCFSA1_cfsa3_b = 8,
4387 + ETHCFSA1_cfsa3_m = 0x0000ff00,
4388 +
4389 + ETHCFSA2_cfsa0_b = 0,
4390 + ETHCFSA2_cfsa0_m = 0x000000ff,
4391 + ETHCFSA2_cfsa1_b = 8,
4392 + ETHCFSA2_cfsa1_m = 0x0000ff00,
4393 +
4394 + ETHMAC1_re_b = 0,
4395 + ETHMAC1_re_m = 0x00000001,
4396 + ETHMAC1_paf_b = 1,
4397 + ETHMAC1_paf_m = 0x00000002,
4398 + ETHMAC1_rfc_b = 2,
4399 + ETHMAC1_rfc_m = 0x00000004,
4400 + ETHMAC1_tfc_b = 3,
4401 + ETHMAC1_tfc_m = 0x00000008,
4402 + ETHMAC1_lb_b = 4,
4403 + ETHMAC1_lb_m = 0x00000010,
4404 + ETHMAC1_mr_b = 31,
4405 + ETHMAC1_mr_m = 0x80000000,
4406 +
4407 + ETHMAC2_fd_b = 0,
4408 + ETHMAC2_fd_m = 0x00000001,
4409 + ETHMAC2_flc_b = 1,
4410 + ETHMAC2_flc_m = 0x00000002,
4411 + ETHMAC2_hfe_b = 2,
4412 + ETHMAC2_hfe_m = 0x00000004,
4413 + ETHMAC2_dc_b = 3,
4414 + ETHMAC2_dc_m = 0x00000008,
4415 + ETHMAC2_cen_b = 4,
4416 + ETHMAC2_cen_m = 0x00000010,
4417 + ETHMAC2_pe_b = 5,
4418 + ETHMAC2_pe_m = 0x00000020,
4419 + ETHMAC2_vpe_b = 6,
4420 + ETHMAC2_vpe_m = 0x00000040,
4421 + ETHMAC2_ape_b = 7,
4422 + ETHMAC2_ape_m = 0x00000080,
4423 + ETHMAC2_ppe_b = 8,
4424 + ETHMAC2_ppe_m = 0x00000100,
4425 + ETHMAC2_lpe_b = 9,
4426 + ETHMAC2_lpe_m = 0x00000200,
4427 + ETHMAC2_nb_b = 12,
4428 + ETHMAC2_nb_m = 0x00001000,
4429 + ETHMAC2_bp_b = 13,
4430 + ETHMAC2_bp_m = 0x00002000,
4431 + ETHMAC2_ed_b = 14,
4432 + ETHMAC2_ed_m = 0x00004000,
4433 +
4434 + ETHIPGT_ipgt_b = 0,
4435 + ETHIPGT_ipgt_m = 0x0000007f,
4436 +
4437 + ETHIPGR_ipgr2_b = 0,
4438 + ETHIPGR_ipgr2_m = 0x0000007f,
4439 + ETHIPGR_ipgr1_b = 8,
4440 + ETHIPGR_ipgr1_m = 0x00007f00,
4441 +
4442 + ETHCLRT_maxret_b = 0,
4443 + ETHCLRT_maxret_m = 0x0000000f,
4444 + ETHCLRT_colwin_b = 8,
4445 + ETHCLRT_colwin_m = 0x00003f00,
4446 +
4447 + ETHMAXF_maxf_b = 0,
4448 + ETHMAXF_maxf_m = 0x0000ffff,
4449 +
4450 + ETHMTEST_tb_b = 2,
4451 + ETHMTEST_tb_m = 0x00000004,
4452 +
4453 + ETHMCP_div_b = 0,
4454 + ETHMCP_div_m = 0x000000ff,
4455 +
4456 + MIIMCFG_rsv_b = 0,
4457 + MIIMCFG_rsv_m = 0x0000000c,
4458 +
4459 + MIIMCMD_rd_b = 0,
4460 + MIIMCMD_rd_m = 0x00000001,
4461 + MIIMCMD_scn_b = 1,
4462 + MIIMCMD_scn_m = 0x00000002,
4463 +
4464 + MIIMADDR_regaddr_b = 0,
4465 + MIIMADDR_regaddr_m = 0x0000001f,
4466 + MIIMADDR_phyaddr_b = 8,
4467 + MIIMADDR_phyaddr_m = 0x00001f00,
4468 +
4469 + MIIMWTD_wdata_b = 0,
4470 + MIIMWTD_wdata_m = 0x0000ffff,
4471 +
4472 + MIIMRDD_rdata_b = 0,
4473 + MIIMRDD_rdata_m = 0x0000ffff,
4474 +
4475 + MIIMIND_bsy_b = 0,
4476 + MIIMIND_bsy_m = 0x00000001,
4477 + MIIMIND_scn_b = 1,
4478 + MIIMIND_scn_m = 0x00000002,
4479 + MIIMIND_nv_b = 2,
4480 + MIIMIND_nv_m = 0x00000004,
4481 +
4482 +} ;
4483 +
4484 +/*
4485 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4486 + */
4487 +enum
4488 +{
4489 + ETHRX_fd_b = 0,
4490 + ETHRX_fd_m = 0x00000001,
4491 + ETHRX_ld_b = 1,
4492 + ETHRX_ld_m = 0x00000002,
4493 + ETHRX_rok_b = 2,
4494 + ETHRX_rok_m = 0x00000004,
4495 + ETHRX_fm_b = 3,
4496 + ETHRX_fm_m = 0x00000008,
4497 + ETHRX_mp_b = 4,
4498 + ETHRX_mp_m = 0x00000010,
4499 + ETHRX_bp_b = 5,
4500 + ETHRX_bp_m = 0x00000020,
4501 + ETHRX_vlt_b = 6,
4502 + ETHRX_vlt_m = 0x00000040,
4503 + ETHRX_cf_b = 7,
4504 + ETHRX_cf_m = 0x00000080,
4505 + ETHRX_ovr_b = 8,
4506 + ETHRX_ovr_m = 0x00000100,
4507 + ETHRX_crc_b = 9,
4508 + ETHRX_crc_m = 0x00000200,
4509 + ETHRX_cv_b = 10,
4510 + ETHRX_cv_m = 0x00000400,
4511 + ETHRX_db_b = 11,
4512 + ETHRX_db_m = 0x00000800,
4513 + ETHRX_le_b = 12,
4514 + ETHRX_le_m = 0x00001000,
4515 + ETHRX_lor_b = 13,
4516 + ETHRX_lor_m = 0x00002000,
4517 + ETHRX_ces_b = 14,
4518 + ETHRX_ces_m = 0x00004000,
4519 + ETHRX_length_b = 16,
4520 + ETHRX_length_m = 0xffff0000,
4521 +
4522 + ETHTX_fd_b = 0,
4523 + ETHTX_fd_m = 0x00000001,
4524 + ETHTX_ld_b = 1,
4525 + ETHTX_ld_m = 0x00000002,
4526 + ETHTX_oen_b = 2,
4527 + ETHTX_oen_m = 0x00000004,
4528 + ETHTX_pen_b = 3,
4529 + ETHTX_pen_m = 0x00000008,
4530 + ETHTX_cen_b = 4,
4531 + ETHTX_cen_m = 0x00000010,
4532 + ETHTX_hen_b = 5,
4533 + ETHTX_hen_m = 0x00000020,
4534 + ETHTX_tok_b = 6,
4535 + ETHTX_tok_m = 0x00000040,
4536 + ETHTX_mp_b = 7,
4537 + ETHTX_mp_m = 0x00000080,
4538 + ETHTX_bp_b = 8,
4539 + ETHTX_bp_m = 0x00000100,
4540 + ETHTX_und_b = 9,
4541 + ETHTX_und_m = 0x00000200,
4542 + ETHTX_of_b = 10,
4543 + ETHTX_of_m = 0x00000400,
4544 + ETHTX_ed_b = 11,
4545 + ETHTX_ed_m = 0x00000800,
4546 + ETHTX_ec_b = 12,
4547 + ETHTX_ec_m = 0x00001000,
4548 + ETHTX_lc_b = 13,
4549 + ETHTX_lc_m = 0x00002000,
4550 + ETHTX_td_b = 14,
4551 + ETHTX_td_m = 0x00004000,
4552 + ETHTX_crc_b = 15,
4553 + ETHTX_crc_m = 0x00008000,
4554 + ETHTX_le_b = 16,
4555 + ETHTX_le_m = 0x00010000,
4556 + ETHTX_cc_b = 17,
4557 + ETHTX_cc_m = 0x001E0000,
4558 +} ;
4559 +
4560 +enum
4561 +{
4562 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
4563 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
4564 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
4565 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
4566 +} ;
4567 +
4568 +typedef struct
4569 +{
4570 + u32 ipabmcrx ;
4571 + u32 ipabmctx ;
4572 +}volatile *IPABM_ETH_t;
4573 +#endif //__IDT_RC32365_ETH_H__
4574 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4575 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
4576 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-06-18 12:44:28.000000000 +0200
4577 @@ -0,0 +1,72 @@
4578 +/**************************************************************************
4579 + *
4580 + * BRIEF MODULE DESCRIPTION
4581 + * RC32365/336 Ethernet status checking.
4582 + *
4583 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4584 + *
4585 + * This program is free software; you can redistribute it and/or modify it
4586 + * under the terms of the GNU General Public License as published by the
4587 + * Free Software Foundation; either version 2 of the License, or (at your
4588 + * option) any later version.
4589 + *
4590 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4591 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4592 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4593 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4594 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4595 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4596 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4597 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4598 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4599 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4600 + *
4601 + * You should have received a copy of the GNU General Public License along
4602 + * with this program; if not, write to the Free Software Foundation, Inc.,
4603 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4604 + *
4605 + *
4606 + **************************************************************************
4607 + * May 2004 P. Sadik.
4608 + *
4609 + * Initial Release
4610 + *
4611 + *
4612 + *
4613 + **************************************************************************
4614 + */
4615 +
4616 +#ifndef __IDT_RC32365_ETH_V_H__
4617 +#define __IDT_RC32365_ETH_V_H__
4618 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
4619 +
4620 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
4621 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
4622 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
4623 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
4624 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
4625 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
4626 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
4627 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
4628 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
4629 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
4630 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
4631 +
4632 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
4633 +
4634 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
4635 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
4636 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
4637 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
4638 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
4639 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
4640 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
4641 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
4642 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
4643 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
4644 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
4645 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
4646 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
4647 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
4648 +
4649 +#endif //__IDT_RC32365_ETH_V_H__
4650 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4651 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
4652 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-06-18 12:44:28.000000000 +0200
4653 @@ -0,0 +1,181 @@
4654 +/**************************************************************************
4655 + *
4656 + * BRIEF MODULE DESCRIPTION
4657 + * RC32365/336 GPIO hardware abstraction.
4658 + *
4659 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4660 + *
4661 + * This program is free software; you can redistribute it and/or modify it
4662 + * under the terms of the GNU General Public License as published by the
4663 + * Free Software Foundation; either version 2 of the License, or (at your
4664 + * option) any later version.
4665 + *
4666 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4667 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4668 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4669 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4670 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4671 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4672 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4673 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4674 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4675 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4676 + *
4677 + * You should have received a copy of the GNU General Public License along
4678 + * with this program; if not, write to the Free Software Foundation, Inc.,
4679 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4680 + *
4681 + *
4682 + **************************************************************************
4683 + * May 2004 P. Sadik.
4684 + *
4685 + * Initial Release
4686 + *
4687 + *
4688 + *
4689 + **************************************************************************
4690 + */
4691 +
4692 +#ifndef __IDT_RC32365_GPIO_H__
4693 +#define __IDT_RC32365_GPIO_H__
4694 +
4695 +enum
4696 +{
4697 + GPIO0_PhysicalAddress = 0x18048000,
4698 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
4699 +
4700 + GPIO0_VirtualAddress = 0xb8048000,
4701 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
4702 +} ;
4703 +
4704 +typedef struct
4705 +{
4706 + u32 gpiofunc; /* GPIO Function Register
4707 + * gpiofunc[x]==0 bit = gpio
4708 + * func[x]==1 bit = altfunc
4709 + */
4710 + u32 gpiocfg; /* GPIO Configuration Register
4711 + * gpiocfg[x]==0 bit = input
4712 + * gpiocfg[x]==1 bit = output
4713 + */
4714 + u32 gpiod; /* GPIO Data Register
4715 + * gpiod[x] read/write gpio pinX status
4716 + */
4717 + u32 gpioilevel; /* GPIO Interrupt Status Register
4718 + * interrupt level (see gpioistat)
4719 + */
4720 + u32 gpioistat; /* Gpio Interrupt Status Register
4721 + * istat[x] = (gpiod[x] == level[x])
4722 + * cleared in ISR (STICKY bits)
4723 + */
4724 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
4725 +} volatile * GPIO_t ;
4726 +
4727 +typedef enum
4728 +{
4729 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
4730 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
4731 + GPIO_input_v = 0, // gpiocfg use pin as input.
4732 + GPIO_output_v = 1, // gpiocfg use pin as output.
4733 + GPIO_pin0_b = 0,
4734 + GPIO_pin0_m = 0x00000001,
4735 + GPIO_pin1_b = 1,
4736 + GPIO_pin1_m = 0x00000002,
4737 + GPIO_pin2_b = 2,
4738 + GPIO_pin2_m = 0x00000004,
4739 + GPIO_pin3_b = 3,
4740 + GPIO_pin3_m = 0x00000008,
4741 + GPIO_pin4_b = 4,
4742 + GPIO_pin4_m = 0x00000010,
4743 + GPIO_pin5_b = 5,
4744 + GPIO_pin5_m = 0x00000020,
4745 + GPIO_pin6_b = 6,
4746 + GPIO_pin6_m = 0x00000040,
4747 + GPIO_pin7_b = 7,
4748 + GPIO_pin7_m = 0x00000080,
4749 + GPIO_pin8_b = 8,
4750 + GPIO_pin8_m = 0x00000100,
4751 + GPIO_pin9_b = 9,
4752 + GPIO_pin9_m = 0x00000200,
4753 + GPIO_pin10_b = 10,
4754 + GPIO_pin10_m = 0x00000400,
4755 + GPIO_pin11_b = 11,
4756 + GPIO_pin11_m = 0x00000800,
4757 + GPIO_pin12_b = 12,
4758 + GPIO_pin12_m = 0x00001000,
4759 + GPIO_pin13_b = 13,
4760 + GPIO_pin13_m = 0x00002000,
4761 + GPIO_pin14_b = 14,
4762 + GPIO_pin14_m = 0x00004000,
4763 + GPIO_pin15_b = 15,
4764 + GPIO_pin15_m = 0x00008000,
4765 +
4766 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
4767 +
4768 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
4769 + GPIO_u0sout_m = GPIO_pin0_m,
4770 + GPIO_u0sout_cfg_v = GPIO_output_v,
4771 +
4772 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
4773 + GPIO_u0sinp_m = GPIO_pin1_m,
4774 + GPIO_u0sinp_cfg_v = GPIO_input_v,
4775 +
4776 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
4777 + GPIO_maddr22_m = GPIO_pin2_m,
4778 + GPIO_maddr22_cfg_v = GPIO_output_v,
4779 +
4780 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
4781 + GPIO_maddr23_m = GPIO_pin3_m,
4782 + GPIO_maddr23_cfg_v = GPIO_output_v,
4783 +
4784 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
4785 + GPIO_maddr24_m = GPIO_pin4_m,
4786 + GPIO_maddr24_cfg_v = GPIO_output_v,
4787 +
4788 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
4789 + GPIO_maddr25_m = GPIO_pin5_m,
4790 + GPIO_maddr25_cfg_v = GPIO_output_v,
4791 +
4792 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
4793 + GPIO_rngclk_m = GPIO_pin6_m,
4794 + GPIO_rngclk_cfg_v = GPIO_input_v,
4795 +
4796 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
4797 + GPIO_sdckenp_m = GPIO_pin7_m,
4798 + GPIO_sdckenp_cfg_v = GPIO_output_v,
4799 +
4800 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
4801 + GPIO_cen1_m = GPIO_pin8_m,
4802 + GPIO_cen1_cfg_v = GPIO_output_v,
4803 +
4804 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
4805 + GPIO_cen2_m = GPIO_pin9_m,
4806 + GPIO_cen2_cfg_v = GPIO_output_v,
4807 +
4808 + GPIO_regn_b = GPIO_pin10_b, // reserved.
4809 + GPIO_regn_m = GPIO_pin10_m,
4810 + GPIO_regn_cfg_v = GPIO_output_v,
4811 +
4812 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
4813 + GPIO_iordn_m = GPIO_pin11_m,
4814 + GPIO_iordn_cfg_v = GPIO_output_v,
4815 +
4816 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
4817 + GPIO_iowrn_m = GPIO_pin12_m,
4818 + GPIO_iowrn_cfg_v = GPIO_output_v,
4819 +
4820 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
4821 + GPIO_pcireqn2_m = GPIO_pin13_m,
4822 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
4823 +
4824 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
4825 + GPIO_pcigntn2_m = GPIO_pin14_m,
4826 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
4827 +
4828 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
4829 + GPIO_pcimuintn_m = GPIO_pin15_m,
4830 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
4831 +
4832 +} GPIO_DEFS_t;
4833 +
4834 +#endif //__IDT_RC32365_GPIO_H__
4835 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4836 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
4837 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-06-18 12:44:28.000000000 +0200
4838 @@ -0,0 +1,91 @@
4839 +/**************************************************************************
4840 + *
4841 + * BRIEF MODULE DESCRIPTION
4842 + * Routines to set/clear/toggle GPIO on RC32365
4843 + *
4844 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4845 + *
4846 + * This program is free software; you can redistribute it and/or modify it
4847 + * under the terms of the GNU General Public License as published by the
4848 + * Free Software Foundation; either version 2 of the License, or (at your
4849 + * option) any later version.
4850 + *
4851 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4852 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4853 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4854 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4855 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4856 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4857 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4858 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4859 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4860 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4861 + *
4862 + * You should have received a copy of the GNU General Public License along
4863 + * with this program; if not, write to the Free Software Foundation, Inc.,
4864 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4865 + *
4866 + *
4867 + **************************************************************************
4868 + * May 2004 P. Sadik.
4869 + *
4870 + * Initial Release
4871 + *
4872 + *
4873 + *
4874 + **************************************************************************
4875 + */
4876 +#ifndef __IDT_RC32365_GPIO_V_H__
4877 +#define __IDT_RC32365_GPIO_V_H__
4878 +
4879 +
4880 +#ifdef _LANGUAGE_ASSEMBLY
4881 +#define SET_GPIO(pin) \
4882 + lui t5,0xb804 ; \
4883 + ori t5,t5,0x8000 ; \
4884 + lw t4,8(t5) ; \
4885 + ori t4,t4,pin ; \
4886 + sw t4,8(t5) ;
4887 +
4888 +#define CLEAR_GPIO(pin) \
4889 + lui t5,0xb804 ; \
4890 + ori t5,t5,0x8000 ; \
4891 + lw t4,8(t5) ; \
4892 + lui t6,0xFFFF; \
4893 + ori t6,t6,0xFFFF; \
4894 + xori t6,t6,pin ; \
4895 + and t4,t6 ; \
4896 + sw t4,8(t5) ;
4897 +
4898 +#define TOGGLE_GPIO(pin) \
4899 + lui t5,0xb804 ; \
4900 + ori t5,t5,0x8000 ; \
4901 + lw t4,8(t5) ; \
4902 + xori t4,t4,pin ; \
4903 + sw t4,8(t5) ;
4904 +
4905 +#else // !_LANGUAGE_ASSEMBLY
4906 +#include <asm/rc32300/types.h>
4907 +#include <asm/rc32300/rc32365_gpio.h>
4908 +#include <asm/rc32300/rc32365.h>
4909 +
4910 +static inline void set_gpio(unsigned long pin)
4911 +{
4912 + idt_gpio->gpiod |= pin;
4913 +}
4914 +
4915 +static inline void clear_gpio(unsigned long pin)
4916 +{
4917 + idt_gpio->gpiod &= ~pin;
4918 +}
4919 +static inline void toggle_gpio(unsigned long pin)
4920 +{
4921 + idt_gpio->gpiod ^= pin;
4922 +}
4923 +#define SET_GPIO(pin) set_gpio(pin)
4924 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4925 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4926 +#endif // _LANGUAGE_ASSEMBLY
4927 +
4928 +#endif //__IDT_RC32365_GPIO_V_H__
4929 +
4930 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4931 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
4932 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-06-18 12:44:28.000000000 +0200
4933 @@ -0,0 +1,160 @@
4934 +/**************************************************************************
4935 + *
4936 + * BRIEF MODULE DESCRIPTION
4937 + * Definitions for IDT RC32365 CPU.
4938 + *
4939 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4940 + *
4941 + * This program is free software; you can redistribute it and/or modify it
4942 + * under the terms of the GNU General Public License as published by the
4943 + * Free Software Foundation; either version 2 of the License, or (at your
4944 + * option) any later version.
4945 + *
4946 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4947 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4948 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4949 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4950 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4951 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4952 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4953 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4954 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4955 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4956 + *
4957 + * You should have received a copy of the GNU General Public License along
4958 + * with this program; if not, write to the Free Software Foundation, Inc.,
4959 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4960 + *
4961 + *
4962 + **************************************************************************
4963 + * May 2004 P. Sadik.
4964 + *
4965 + * Initial Release
4966 + *
4967 + *
4968 + *
4969 + **************************************************************************
4970 + */
4971 +
4972 +#ifndef __IDT_RC32365_H__
4973 +#define __IDT_RC32365_H__
4974 +
4975 +extern unsigned int cedar_za;
4976 +
4977 +/* Base address of internal registers */
4978 +#define RC32365_REG_BASE 0x18000000
4979 +
4980 +/* System ID Registers */
4981 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
4982 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
4983 +
4984 +/* Reset Controller */
4985 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
4986 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
4987 +
4988 +/* Device Controller */
4989 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
4990 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
4991 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
4992 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
4993 +#define DEV_REG_OFFSET 0x10
4994 +
4995 +/* SDRAM Controller */
4996 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
4997 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
4998 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
4999 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
5000 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
5001 +
5002 +/* Counters/Timers */
5003 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
5004 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
5005 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
5006 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
5007 +#define TIMER_REG_OFFSET 0x10
5008 +
5009 +/* System Integrity */
5010 +
5011 +/* Interrupt Controller */
5012 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
5013 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
5014 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
5015 +#define IC_GROUP_OFFSET 0x0c
5016 +
5017 +#define NUM_INTR_GROUPS 5
5018 +/*
5019 + * The IRQ mapping is as follows:
5020 + *
5021 + * IRQ Mapped To
5022 + * --- -------------------
5023 + * 0 SW0 (IP0) SW0 intr
5024 + * 1 SW1 (IP1) SW1 intr
5025 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
5026 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
5027 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
5028 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
5029 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
5030 + * 7 Int5 (IP7) CP0 Timer
5031 + *
5032 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5033 + * internally on the RC32365 is routed to the Expansion
5034 + * Interrupt Controller.
5035 + */
5036 +#define MIPS_CPU_TIMER_IRQ 7
5037 +
5038 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
5039 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
5040 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
5041 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5042 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
5043 +
5044 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
5045 +
5046 +/* DMA - see rc32365_dma.h for full list of registers */
5047 +
5048 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5049 +#define DMA_CHAN_OFFSET 0x14
5050 +
5051 +/* GPIO Controller */
5052 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
5053 +
5054 +/* 16550 UARTs */
5055 +#ifdef __MIPSEB__
5056 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5057 +#else
5058 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5059 +#endif
5060 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
5061 +
5062 +/* Ethernet - see rc32365_eth.h for full list of registers */
5063 +
5064 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
5065 +
5066 +#define IDT_CLOCK_MULT 2
5067 +
5068 +/* FLASH (device 1) */
5069 +#define FLASH_BASE 0x08000000
5070 +#define FLASH_SIZE 0x00800000
5071 +
5072 +/* LCD 4-digit display (device 2) */
5073 +#define LCD_DIGIT0 0x0C000003
5074 +#define LCD_DIGIT1 0x0C000002
5075 +#define LCD_DIGIT2 0x0C000001
5076 +#define LCD_DIGIT3 0x0C000000
5077 +
5078 +/* RTC (DS1553) (device 2) */
5079 +#define RTC_BASE 0x0c800000
5080 +/* NVRAM */
5081 +#define NVRAM_BASE RTC_BASE
5082 +#define NVRAM_ENVSIZE_OFF 4
5083 +#define NVRAM_ENVSTART_OFF 32
5084 +
5085 +/* Interrupts routed on 79EB365 board */
5086 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
5087 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
5088 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5089 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5090 +
5091 +#define RAM_SIZE (32 * 1024 * 1024)
5092 +
5093 +#endif //__IDT_RC32365_H__
5094 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5095 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
5096 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-06-18 12:44:28.000000000 +0200
5097 @@ -0,0 +1,515 @@
5098 +/**************************************************************************
5099 + *
5100 + * BRIEF MODULE DESCRIPTION
5101 + * Datatype declaration for IDT 79EB365/336 PCI
5102 + *
5103 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5104 + *
5105 + * This program is free software; you can redistribute it and/or modify it
5106 + * under the terms of the GNU General Public License as published by the
5107 + * Free Software Foundation; either version 2 of the License, or (at your
5108 + * option) any later version.
5109 + *
5110 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5111 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5112 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5113 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5114 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5115 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5116 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5117 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5118 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5119 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5120 + *
5121 + * You should have received a copy of the GNU General Public License along
5122 + * with this program; if not, write to the Free Software Foundation, Inc.,
5123 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5124 + *
5125 + *
5126 + **************************************************************************
5127 + * May 2004 P. Sadik.
5128 + *
5129 + * Initial Release
5130 + *
5131 + *
5132 + *
5133 + **************************************************************************
5134 + */
5135 +
5136 +#ifndef __IDT_RC32365_PCI_H__
5137 +#define __IDT_RC32365_PCI_H__
5138 +
5139 +enum
5140 +{
5141 + PCI0_PhysicalAddress = 0x18068000,
5142 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
5143 +
5144 + PCI0_VirtualAddress = 0xb8068000,
5145 + PCI_VirtualAddress = PCI0_VirtualAddress,
5146 +} ;
5147 +
5148 +enum
5149 +{
5150 + PCI_LbaCount = 4, // Local base addresses.
5151 +} ;
5152 +
5153 +typedef struct
5154 +{
5155 + u32 a ; // Address.
5156 + u32 c ; // Control.
5157 + u32 m ; // mapping.
5158 +} PCI_Map_s ;
5159 +
5160 +typedef struct
5161 +{
5162 + u32 pcic ;
5163 + u32 pcis ;
5164 + u32 pcism ;
5165 + u32 pcicfga ;
5166 + u32 pcicfgd ;
5167 + PCI_Map_s pcilba [PCI_LbaCount] ;
5168 + u32 pcidac ;
5169 + u32 pcidas ;
5170 + u32 pcidasm ;
5171 + u32 pcidad ;
5172 + u32 pcidma8c ;
5173 + u32 pcidma9c ;
5174 + u32 pcitc ;
5175 +} volatile *PCI_t ;
5176 +
5177 +// PCI messaging unit.
5178 +enum
5179 +{
5180 + PCIM_Count = 2,
5181 +} ;
5182 +typedef struct
5183 +{
5184 + u32 pciim [PCIM_Count] ;
5185 + u32 pciom [PCIM_Count] ;
5186 + u32 pciid ;
5187 + u32 pciiic ;
5188 + u32 pciiim ;
5189 + u32 pciiod ;
5190 + u32 pciioic ;
5191 + u32 pciioim ;
5192 +} volatile *PCIM_t ;
5193 +
5194 +/*******************************************************************************
5195 + *
5196 + * PCI Control Register
5197 + *
5198 + ******************************************************************************/
5199 +enum
5200 +{
5201 + PCIC_en_b = 0,
5202 + PCIC_en_m = 0x00000001,
5203 + PCIC_tnr_b = 1,
5204 + PCIC_tnr_m = 0x00000002,
5205 + PCIC_sce_b = 2,
5206 + PCIC_sce_m = 0x00000004,
5207 + PCIC_ien_b = 3,
5208 + PCIC_ien_m = 0x00000008,
5209 + PCIC_aaa_b = 4,
5210 + PCIC_aaa_m = 0x00000010,
5211 + PCIC_eap_b = 5,
5212 + PCIC_eap_m = 0x00000020,
5213 + PCIC_pcim_b = 6,
5214 + PCIC_pcim_m = 0x000001c0,
5215 + PCIC_pcim_disabled_v = 0,
5216 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
5217 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
5218 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
5219 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
5220 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
5221 + PCIC_pcim_reserved6_v = 6,
5222 + PCIC_pcim_reserved7_v = 7,
5223 + PCIC_igm_b = 9,
5224 + PCIC_igm_m = 0x00000200,
5225 +} ;
5226 +
5227 +/*******************************************************************************
5228 + *
5229 + * PCI Status Register
5230 + *
5231 + ******************************************************************************/
5232 +enum {
5233 + PCIS_eed_b = 0,
5234 + PCIS_eed_m = 0x00000001,
5235 + PCIS_wr_b = 1,
5236 + PCIS_wr_m = 0x00000002,
5237 + PCIS_nmi_b = 2,
5238 + PCIS_nmi_m = 0x00000004,
5239 + PCIS_ii_b = 3,
5240 + PCIS_ii_m = 0x00000008,
5241 + PCIS_cwe_b = 4,
5242 + PCIS_cwe_m = 0x00000010,
5243 + PCIS_cre_b = 5,
5244 + PCIS_cre_m = 0x00000020,
5245 + PCIS_mdpe_b = 6,
5246 + PCIS_mdpe_m = 0x00000040,
5247 + PCIS_sta_b = 7,
5248 + PCIS_sta_m = 0x00000080,
5249 + PCIS_rta_b = 8,
5250 + PCIS_rta_m = 0x00000100,
5251 + PCIS_rma_b = 9,
5252 + PCIS_rma_m = 0x00000200,
5253 + PCIS_sse_b = 10,
5254 + PCIS_sse_m = 0x00000400,
5255 + PCIS_ose_b = 11,
5256 + PCIS_ose_m = 0x00000800,
5257 + PCIS_pe_b = 12,
5258 + PCIS_pe_m = 0x00001000,
5259 + PCIS_tae_b = 13,
5260 + PCIS_tae_m = 0x00002000,
5261 + PCIS_rle_b = 14,
5262 + PCIS_rle_m = 0x00004000,
5263 + PCIS_bme_b = 15,
5264 + PCIS_bme_m = 0x00008000,
5265 + PCIS_prd_b = 16,
5266 + PCIS_prd_m = 0x00010000,
5267 + PCIS_rip_b = 17,
5268 + PCIS_rip_m = 0x00020000,
5269 +} ;
5270 +
5271 +/*******************************************************************************
5272 + *
5273 + * PCI Status Mask Register
5274 + *
5275 + ******************************************************************************/
5276 +enum {
5277 + PCISM_eed_b = 0,
5278 + PCISM_eed_m = 0x00000001,
5279 + PCISM_wr_b = 1,
5280 + PCISM_wr_m = 0x00000002,
5281 + PCISM_nmi_b = 2,
5282 + PCISM_nmi_m = 0x00000004,
5283 + PCISM_ii_b = 3,
5284 + PCISM_ii_m = 0x00000008,
5285 + PCISM_cwe_b = 4,
5286 + PCISM_cwe_m = 0x00000010,
5287 + PCISM_cre_b = 5,
5288 + PCISM_cre_m = 0x00000020,
5289 + PCISM_mdpe_b = 6,
5290 + PCISM_mdpe_m = 0x00000040,
5291 + PCISM_sta_b = 7,
5292 + PCISM_sta_m = 0x00000080,
5293 + PCISM_rta_b = 8,
5294 + PCISM_rta_m = 0x00000100,
5295 + PCISM_rma_b = 9,
5296 + PCISM_rma_m = 0x00000200,
5297 + PCISM_sse_b = 10,
5298 + PCISM_sse_m = 0x00000400,
5299 + PCISM_ose_b = 11,
5300 + PCISM_ose_m = 0x00000800,
5301 + PCISM_pe_b = 12,
5302 + PCISM_pe_m = 0x00001000,
5303 + PCISM_tae_b = 13,
5304 + PCISM_tae_m = 0x00002000,
5305 + PCISM_rle_b = 14,
5306 + PCISM_rle_m = 0x00004000,
5307 + PCISM_bme_b = 15,
5308 + PCISM_bme_m = 0x00008000,
5309 + PCISM_prd_b = 16,
5310 + PCISM_prd_m = 0x00010000,
5311 + PCISM_rip_b = 17,
5312 + PCISM_rip_m = 0x00020000,
5313 +} ;
5314 +
5315 +/*******************************************************************************
5316 + *
5317 + * PCI Configuration Address Register
5318 + *
5319 + ******************************************************************************/
5320 +enum {
5321 + PCICFGA_reg_b = 2,
5322 + PCICFGA_reg_m = 0x000000fc,
5323 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
5324 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
5325 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
5326 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
5327 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
5328 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
5329 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
5330 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
5331 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5332 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
5333 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
5334 + PCICFGA_reg_pba0m_v = 0x48>>2,
5335 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
5336 + PCICFGA_reg_pba1m_v = 0x50>>2,
5337 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
5338 + PCICFGA_reg_pba2m_v = 0x58>>2,
5339 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
5340 + PCICFGA_reg_pba3m_v = 0x60>>2,
5341 + PCICFGA_reg_pmgt_v = 0x64>>2,
5342 + PCICFGA_func_b = 8,
5343 + PCICFGA_func_m = 0x00000700,
5344 + PCICFGA_dev_b = 11,
5345 + PCICFGA_dev_m = 0x0000f800,
5346 + PCICFGA_dev_internal_v = 0,
5347 + PCICFGA_bus_b = 16,
5348 + PCICFGA_bus_m = 0x00ff0000,
5349 + PCICFGA_bus_type0_v = 0, //local bus
5350 + PCICFGA_en_b = 31, // read only
5351 + PCICFGA_en_m = 0x80000000,
5352 +} ;
5353 +
5354 +enum {
5355 + PCFGID_vendor_b = 0,
5356 + PCFGID_vendor_m = 0x0000ffff,
5357 + PCFGID_vendor_IDT_v = 0x111d,
5358 + PCFGID_device_b = 16,
5359 + PCFGID_device_m = 0xffff0000,
5360 + PCFGID_device_Acaciade_v = 0x0207,
5361 +
5362 + PCFG04_command_ioena_b = 1,
5363 + PCFG04_command_ioena_m = 0x00000001,
5364 + PCFG04_command_memena_b = 2,
5365 + PCFG04_command_memena_m = 0x00000002,
5366 + PCFG04_command_bmena_b = 3,
5367 + PCFG04_command_bmena_m = 0x00000004,
5368 + PCFG04_command_mwinv_b = 5,
5369 + PCFG04_command_mwinv_m = 0x00000010,
5370 + PCFG04_command_parena_b = 7,
5371 + PCFG04_command_parena_m = 0x00000040,
5372 + PCFG04_command_serrena_b = 9,
5373 + PCFG04_command_serrena_m = 0x00000100,
5374 + PCFG04_command_fastbbena_b = 10,
5375 + PCFG04_command_fastbbena_m = 0x00000200,
5376 + PCFG04_status_b = 16,
5377 + PCFG04_status_m = 0xffff0000,
5378 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
5379 + PCFG04_status_66MHz_m = 0x00200000,
5380 + PCFG04_status_fbb_b = 23,
5381 + PCFG04_status_fbb_m = 0x00800000,
5382 + PCFG04_status_mdpe_b = 24,
5383 + PCFG04_status_mdpe_m = 0x01000000,
5384 + PCFG04_status_dst_b = 25,
5385 + PCFG04_status_dst_m = 0x06000000,
5386 + PCFG04_status_sta_b = 27,
5387 + PCFG04_status_sta_m = 0x08000000,
5388 + PCFG04_status_rta_b = 28,
5389 + PCFG04_status_rta_m = 0x10000000,
5390 + PCFG04_status_rma_b = 29,
5391 + PCFG04_status_rma_m = 0x20000000,
5392 + PCFG04_status_sse_b = 30,
5393 + PCFG04_status_sse_m = 0x40000000,
5394 + PCFG04_status_pe_b = 31,
5395 + PCFG04_status_pe_m = 0x40000000,
5396 +
5397 + PCFG08_revId_b = 0,
5398 + PCFG08_revId_m = 0x000000ff,
5399 + PCFG08_classCode_b = 0,
5400 + PCFG08_classCode_m = 0xffffff00,
5401 + PCFG08_classCode_bridge_v = 06,
5402 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
5403 + PCFG0C_cacheline_b = 0,
5404 + PCFG0C_cacheline_m = 0x000000ff,
5405 + PCFG0C_masterLatency_b = 8,
5406 + PCFG0C_masterLatency_m = 0x0000ff00,
5407 + PCFG0C_headerType_b = 16,
5408 + PCFG0C_headerType_m = 0x00ff0000,
5409 + PCFG0C_bist_b = 24,
5410 + PCFG0C_bist_m = 0xff000000,
5411 +
5412 + PCIPBA_msi_b = 0,
5413 + PCIPBA_msi_m = 0x00000001,
5414 + PCIPBA_p_b = 3,
5415 + PCIPBA_p_m = 0x00000004,
5416 + PCIPBA_baddr_b = 8,
5417 + PCIPBA_baddr_m = 0xffffff00,
5418 +
5419 + PCFGSS_vendorId_b = 0,
5420 + PCFGSS_vendorId_m = 0x0000ffff,
5421 + PCFGSS_id_b = 16,
5422 + PCFGSS_id_m = 0xffff0000,
5423 +
5424 + PCFG3C_interruptLine_b = 0,
5425 + PCFG3C_interruptLine_m = 0x000000ff,
5426 + PCFG3C_interruptPin_b = 8,
5427 + PCFG3C_interruptPin_m = 0x0000ff00,
5428 + PCFG3C_minGrant_b = 16,
5429 + PCFG3C_minGrant_m = 0x00ff0000,
5430 + PCFG3C_maxLat_b = 24,
5431 + PCFG3C_maxLat_m = 0xff000000,
5432 +
5433 + PCIPBAC_msi_b = 0,
5434 + PCIPBAC_msi_m = 0x00000001,
5435 + PCIPBAC_p_b = 1,
5436 + PCIPBAC_p_m = 0x00000002,
5437 + PCIPBAC_size_b = 2,
5438 + PCIPBAC_size_m = 0x0000007c,
5439 + PCIPBAC_sb_b = 7,
5440 + PCIPBAC_sb_m = 0x00000080,
5441 + PCIPBAC_pp_b = 8,
5442 + PCIPBAC_pp_m = 0x00000100,
5443 + PCIPBAC_mr_b = 9,
5444 + PCIPBAC_mr_m = 0x00000600,
5445 + PCIPBAC_mr_read_v =0, //no prefetching
5446 + PCIPBAC_mr_readLine_v =1,
5447 + PCIPBAC_mr_readMult_v =2,
5448 + PCIPBAC_mrl_b = 11,
5449 + PCIPBAC_mrl_m = 0x00000800,
5450 + PCIPBAC_mrm_b = 12,
5451 + PCIPBAC_mrm_m = 0x00001000,
5452 + PCIPBAC_trp_b = 13,
5453 + PCIPBAC_trp_m = 0x00002000,
5454 +
5455 + PCFG40_trdyTimeout_b = 0,
5456 + PCFG40_trdyTimeout_m = 0x000000ff,
5457 + PCFG40_retryLim_b = 8,
5458 + PCFG40_retryLim_m = 0x0000ff00,
5459 +};
5460 +
5461 +/*******************************************************************************
5462 + *
5463 + * PCI Local Base Address [0|1|2|3] Register
5464 + *
5465 + ******************************************************************************/
5466 +enum {
5467 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
5468 + PCILBA_baddr_m = 0xffffff00,
5469 +} ;
5470 +/*******************************************************************************
5471 + *
5472 + * PCI Local Base Address Control Register
5473 + *
5474 + ******************************************************************************/
5475 +enum {
5476 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
5477 + PCILBAC_msi_m = 0x00000001,
5478 + PCILBAC_msi_mem_v = 0,
5479 + PCILBAC_msi_io_v = 1,
5480 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
5481 + PCILBAC_size_m = 0x0000007c,
5482 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
5483 + PCILBAC_sb_m = 0x00000080,
5484 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
5485 + PCILBAC_rt_m = 0x00000100,
5486 + PCILBAC_rt_noprefetch_v = 0, // mem read
5487 + PCILBAC_rt_prefetch_v = 1, // mem readline
5488 +} ;
5489 +
5490 +/*******************************************************************************
5491 + *
5492 + * PCI Local Base Address [0|1|2|3] Mapping Register
5493 + *
5494 + ******************************************************************************/
5495 +enum {
5496 + PCILBAM_maddr_b = 8,
5497 + PCILBAM_maddr_m = 0xffffff00,
5498 +} ;
5499 +
5500 +/*******************************************************************************
5501 + *
5502 + * PCI Decoupled Access Control Register
5503 + *
5504 + ******************************************************************************/
5505 +enum {
5506 + PCIDAC_den_b = 0,
5507 + PCIDAC_den_m = 0x00000001,
5508 +} ;
5509 +
5510 +/*******************************************************************************
5511 + *
5512 + * PCI Decoupled Access Status Register
5513 + *
5514 + ******************************************************************************/
5515 +enum {
5516 + PCIDAS_d_b = 0,
5517 + PCIDAS_d_m = 0x00000001,
5518 + PCIDAS_b_b = 1,
5519 + PCIDAS_b_m = 0x00000002,
5520 + PCIDAS_e_b = 2,
5521 + PCIDAS_e_m = 0x00000004,
5522 + PCIDAS_ofe_b = 3,
5523 + PCIDAS_ofe_m = 0x00000008,
5524 + PCIDAS_off_b = 4,
5525 + PCIDAS_off_m = 0x00000010,
5526 + PCIDAS_ife_b = 5,
5527 + PCIDAS_ife_m = 0x00000020,
5528 + PCIDAS_iff_b = 6,
5529 + PCIDAS_iff_m = 0x00000040,
5530 +} ;
5531 +
5532 +/*******************************************************************************
5533 + *
5534 + * PCI DMA Channel 8 Configuration Register
5535 + *
5536 + ******************************************************************************/
5537 +enum
5538 +{
5539 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
5540 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
5541 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
5542 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
5543 +} ;
5544 +
5545 +/*******************************************************************************
5546 + *
5547 + * PCI DMA Channel 9 Configuration Register
5548 + *
5549 + ******************************************************************************/
5550 +enum
5551 +{
5552 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
5553 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
5554 +} ;
5555 +
5556 +/*******************************************************************************
5557 + *
5558 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5559 + *
5560 + ******************************************************************************/
5561 +enum {
5562 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
5563 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
5564 + // These are for reads (DMA channel 8)
5565 + PCIDMAD_devcmd_mr_v = 0, //memory read
5566 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
5567 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
5568 + PCIDMAD_devcmd_ior_v = 3, //I/O read
5569 + // These are for writes (DMA channel 9)
5570 + PCIDMAD_devcmd_mw_v = 0, //memory write
5571 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
5572 + PCIDMAD_devcmd_iow_v = 3, //I/O write
5573 +
5574 + // Swap byte field applies to both DMA channel 8 and 9
5575 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
5576 + PCIDMAD_sb_m = 0x01000000, // swap byte field
5577 +} ;
5578 +
5579 +
5580 +/*******************************************************************************
5581 + *
5582 + * PCI Target Control Register
5583 + *
5584 + ******************************************************************************/
5585 +enum
5586 +{
5587 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
5588 + PCITC_rtimer_m = 0x000000ff,
5589 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
5590 + PCITC_dtimer_m = 0x0000ff00,
5591 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
5592 + PCITC_rdr_m = 0x00040000,
5593 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
5594 + PCITC_ddt_m = 0x00080000,
5595 +} ;
5596 +/*******************************************************************************
5597 + *
5598 + * PCI messaging unit [applies to both inbound and outbound registers ]
5599 + *
5600 + ******************************************************************************/
5601 +enum
5602 +{
5603 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5604 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
5605 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5606 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
5607 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5608 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
5609 +};
5610 +
5611 +
5612 +#endif // __IDT_RC32365_PCI_H__
5613 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5614 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
5615 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-06-18 12:44:28.000000000 +0200
5616 @@ -0,0 +1,217 @@
5617 +/**************************************************************************
5618 + *
5619 + * BRIEF MODULE DESCRIPTION
5620 + * PCI header values for IDT 79EB365/336
5621 + *
5622 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5623 + *
5624 + * This program is free software; you can redistribute it and/or modify it
5625 + * under the terms of the GNU General Public License as published by the
5626 + * Free Software Foundation; either version 2 of the License, or (at your
5627 + * option) any later version.
5628 + *
5629 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5630 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5631 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5632 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5633 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5634 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5635 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5636 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5637 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5638 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5639 + *
5640 + * You should have received a copy of the GNU General Public License along
5641 + * with this program; if not, write to the Free Software Foundation, Inc.,
5642 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5643 + *
5644 + *
5645 + **************************************************************************
5646 + * May 2004 P. Sadik.
5647 + *
5648 + * Initial Release
5649 + *
5650 + *
5651 + *
5652 + **************************************************************************
5653 + */
5654 +
5655 +#ifndef __IDT_RC32365_PCI_V_H__
5656 +#define __IDT_RC32365_PCI_V_H__
5657 +
5658 +
5659 +#define PCI_MSG_VirtualAddress 0xB806C010
5660 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5661 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5662 +
5663 +#define PCIM_SHFT 0x6
5664 +#define PCIM_BIT_LEN 0x7
5665 +#define PCIM_H_EA 0x3
5666 +#define PCIM_H_IA_FIX 0x4
5667 +#define PCIM_H_IA_RR 0x5
5668 +
5669 +#define PCI_ADDR_START 0x50000000
5670 +
5671 +#define CPUTOPCI_MEM_WIN 0x02000000
5672 +#define CPUTOPCI_IO_WIN 0x00100000
5673 +#define PCILBA_SIZE_SHFT 2
5674 +#define PCILBA_SIZE_MASK 0x1F
5675 +#define SIZE_256MB 0x1C
5676 +#define SIZE_128MB 0x1B
5677 +#define SIZE_64MB 0x1A
5678 +#define SIZE_32MB 0x19
5679 +#define SIZE_16MB 0x18
5680 +#define SIZE_4MB 0x16
5681 +#define SIZE_2MB 0x15
5682 +#define SIZE_1MB 0x14
5683 +#define CEDAR_CONFIG0_ADDR 0x80000000
5684 +#define CEDAR_CONFIG1_ADDR 0x80000004
5685 +#define CEDAR_CONFIG2_ADDR 0x80000008
5686 +#define CEDAR_CONFIG3_ADDR 0x8000000C
5687 +#define CEDAR_CONFIG4_ADDR 0x80000010
5688 +#define CEDAR_CONFIG5_ADDR 0x80000014
5689 +#define CEDAR_CONFIG6_ADDR 0x80000018
5690 +#define CEDAR_CONFIG7_ADDR 0x8000001C
5691 +#define CEDAR_CONFIG8_ADDR 0x80000020
5692 +#define CEDAR_CONFIG9_ADDR 0x80000024
5693 +#define CEDAR_CONFIG10_ADDR 0x80000028
5694 +#define CEDAR_CONFIG11_ADDR 0x8000002C
5695 +#define CEDAR_CONFIG12_ADDR 0x80000030
5696 +#define CEDAR_CONFIG13_ADDR 0x80000034
5697 +#define CEDAR_CONFIG14_ADDR 0x80000038
5698 +#define CEDAR_CONFIG15_ADDR 0x8000003C
5699 +#define CEDAR_CONFIG16_ADDR 0x80000040
5700 +#define CEDAR_CONFIG17_ADDR 0x80000044
5701 +#define CEDAR_CONFIG18_ADDR 0x80000048
5702 +#define CEDAR_CONFIG19_ADDR 0x8000004C
5703 +#define CEDAR_CONFIG20_ADDR 0x80000050
5704 +#define CEDAR_CONFIG21_ADDR 0x80000054
5705 +#define CEDAR_CONFIG22_ADDR 0x80000058
5706 +#define CEDAR_CONFIG23_ADDR 0x8000005C
5707 +#define CEDAR_CONFIG24_ADDR 0x80000060
5708 +#define CEDAR_CONFIG25_ADDR 0x80000064
5709 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
5710 + PCFG04_command_memena_m | \
5711 + PCFG04_command_bmena_m | \
5712 + PCFG04_command_mwinv_m | \
5713 + PCFG04_command_parena_m | \
5714 + PCFG04_command_serrena_m )
5715 +
5716 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
5717 + PCFG04_status_sta_m | \
5718 + PCFG04_status_rta_m | \
5719 + PCFG04_status_rma_m | \
5720 + PCFG04_status_sse_m | \
5721 + PCFG04_status_pe_m)
5722 +
5723 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
5724 + CEDAR_CMD)
5725 +
5726 +#define CEDAR_REVID 0
5727 +#define CEDAR_CLASS_CODE 0
5728 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
5729 + CEDAR_REVID)
5730 +
5731 +#define CEDAR_CACHE_LINE_SIZE 4
5732 +#define CEDAR_MASTER_LAT 0x3c
5733 +#define CEDAR_HEADER_TYPE 0
5734 +#define CEDAR_BIST 0
5735 +
5736 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
5737 + (CEDAR_HEADER_TYPE << 16) | \
5738 + (CEDAR_MASTER_LAT << 8) | \
5739 + CEDAR_CACHE_LINE_SIZE)
5740 +
5741 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
5742 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
5743 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
5744 + internal Registers */
5745 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
5746 +
5747 +#define CEDAR_CNFG4 CEDAR_BAR0
5748 +#define CEDAR_CNFG5 CEDAR_BAR1
5749 +#define CEDAR_CNFG6 CEDAR_BAR2
5750 +#define CEDAR_CNFG7 CEDAR_BAR3
5751 +
5752 +#define CEDAR_SUBSYS_VENDOR_ID 0
5753 +#define CEDAR_SUBSYSTEM_ID 0
5754 +#define CEDAR_CNFG8 0
5755 +#define CEDAR_CNFG9 0
5756 +#define CEDAR_CNFG10 0
5757 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5758 + CEDAR_SUBSYSTEM_ID)
5759 +#define CEDAR_INT_LINE 1
5760 +#define CEDAR_INT_PIN 1
5761 +#define CEDAR_MIN_GNT 8
5762 +#define CEDAR_MAX_LAT 0x38
5763 +#define CEDAR_CNFG12 0
5764 +#define CEDAR_CNFG13 0
5765 +#define CEDAR_CNFG14 0
5766 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
5767 + (CEDAR_MIN_GNT << 16) | \
5768 + (CEDAR_INT_PIN << 8) | \
5769 + CEDAR_INT_LINE)
5770 +#define CEDAR_RETRY_LIMIT 0x80
5771 +#define CEDAR_TRDY_LIMIT 0x80
5772 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
5773 + CEDAR_TRDY_LIMIT)
5774 +#define PCI_PBAxC_R 0x0
5775 +#define PCI_PBAxC_RL 0x1
5776 +#define PCI_PBAxC_RM 0x2
5777 +#define SIZE_SHFT 2
5778 +#ifdef __MIPSEB__
5779 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5780 + PCIPBAC_pp_m | \
5781 + PCIPBAC_sb_m | \
5782 + (SIZE_128MB << SIZE_SHFT) | \
5783 + PCIPBAC_p_m)
5784 +#else
5785 +
5786 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5787 + PCIPBAC_pp_m | \
5788 + (SIZE_128MB << SIZE_SHFT) | \
5789 + PCIPBAC_p_m)
5790 +#endif
5791 +#define CEDAR_CNFG17 CEDAR_PBA0C
5792 +#define CEDAR_PBA0M 0x0
5793 +#define CEDAR_CNFG18 CEDAR_PBA0M
5794 +
5795 +#ifdef __MIPSEB__
5796 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5797 + PCIPBAC_sb_m | \
5798 + PCIPBAC_msi_m)
5799 +#else
5800 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5801 + PCIPBAC_msi_m)
5802 +#endif
5803 +#define CEDAR_CNFG19 CEDAR_PBA1C
5804 +#define CEDAR_PBA1M 0x0
5805 +#define CEDAR_CNFG20 CEDAR_PBA1M
5806 +
5807 +#ifdef __MIPSEB__
5808 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5809 + PCIPBAC_sb_m | \
5810 + PCIPBAC_msi_m)
5811 +#else
5812 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5813 + PCIPBAC_msi_m)
5814 +#endif
5815 +
5816 +#define CEDAR_CNFG21 CEDAR_PBA2C
5817 +#define CEDAR_PBA2M 0x18000000
5818 +#define CEDAR_CNFG22 CEDAR_PBA2M
5819 +
5820 +#ifdef __MIPSEB__
5821 +#define CEDAR_PBA3C PCIPBAC_sb_m
5822 +#else
5823 +#define CEDAR_PBA3C 0
5824 +#endif
5825 +
5826 +#define CEDAR_CNFG23 CEDAR_PBA3C
5827 +#define CEDAR_PBA3M 0
5828 +#define CEDAR_CNFG24 CEDAR_PBA3M
5829 +
5830 +#define PCITC_DTIMER_VAL 8
5831 +#define PCITC_RTIMER_VAL 0x10
5832 +
5833 +#endif //__IDT_RC32365_PCI_V_H__
5834 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5835 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
5836 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-06-18 12:44:28.000000000 +0200
5837 @@ -0,0 +1,205 @@
5838 +/**************************************************************************
5839 + *
5840 + * BRIEF MODULE DESCRIPTION
5841 + * DMA register definition
5842 + *
5843 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5844 + *
5845 + * This program is free software; you can redistribute it and/or modify it
5846 + * under the terms of the GNU General Public License as published by the
5847 + * Free Software Foundation; either version 2 of the License, or (at your
5848 + * option) any later version.
5849 + *
5850 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5851 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5852 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5853 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5854 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5855 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5856 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5857 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5858 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5859 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5860 + *
5861 + * You should have received a copy of the GNU General Public License along
5862 + * with this program; if not, write to the Free Software Foundation, Inc.,
5863 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5864 + *
5865 + *
5866 + **************************************************************************
5867 + * May 2004 rkt, neb
5868 + *
5869 + * Initial Release
5870 + *
5871 + *
5872 + *
5873 + **************************************************************************
5874 + */
5875 +
5876 +#ifndef __IDT_DMA_H__
5877 +#define __IDT_DMA_H__
5878 +
5879 +enum
5880 +{
5881 + DMA0_PhysicalAddress = 0x18040000,
5882 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5883 +
5884 + DMA0_VirtualAddress = 0xb8040000,
5885 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5886 +} ;
5887 +
5888 +/*
5889 + * DMA descriptor (in physical memory).
5890 + */
5891 +
5892 +typedef struct DMAD_s
5893 +{
5894 + u32 control ; // Control. use DMAD_*
5895 + u32 ca ; // Current Address.
5896 + u32 devcs ; // Device control and status.
5897 + u32 link ; // Next descriptor in chain.
5898 +} volatile *DMAD_t ;
5899 +
5900 +enum
5901 +{
5902 + DMAD_size = sizeof (struct DMAD_s),
5903 + DMAD_count_b = 0, // in DMAD_t -> control
5904 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5905 + DMAD_ds_b = 20, // in DMAD_t -> control
5906 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5907 + DMAD_ds_ethRcv0_v = 0,
5908 + DMAD_ds_ethXmt0_v = 0,
5909 + DMAD_ds_memToFifo_v = 0,
5910 + DMAD_ds_fifoToMem_v = 0,
5911 + DMAD_ds_pciToMem_v = 0,
5912 + DMAD_ds_memToPci_v = 0,
5913 +
5914 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5915 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5916 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5917 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5918 + DMAD_devcmd_word_v = 2, //memory-to-memory
5919 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5920 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5921 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5922 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5923 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5924 + DMAD_cof_b = 25, // chain on finished
5925 + DMAD_cof_m = 0x02000000, //
5926 + DMAD_cod_b = 26, // chain on done
5927 + DMAD_cod_m = 0x04000000, //
5928 + DMAD_iof_b = 27, // interrupt on finished
5929 + DMAD_iof_m = 0x08000000, //
5930 + DMAD_iod_b = 28, // interrupt on done
5931 + DMAD_iod_m = 0x10000000, //
5932 + DMAD_t_b = 29, // terminated
5933 + DMAD_t_m = 0x20000000, //
5934 + DMAD_d_b = 30, // done
5935 + DMAD_d_m = 0x40000000, //
5936 + DMAD_f_b = 31, // finished
5937 + DMAD_f_m = 0x80000000, //
5938 +} ;
5939 +
5940 +/*
5941 + * DMA register (within Internal Register Map).
5942 + */
5943 +
5944 +struct DMA_Chan_s
5945 +{
5946 + u32 dmac ; // Control.
5947 + u32 dmas ; // Status.
5948 + u32 dmasm ; // Mask.
5949 + u32 dmadptr ; // Descriptor pointer.
5950 + u32 dmandptr ; // Next descriptor pointer.
5951 +};
5952 +
5953 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5954 +
5955 +//DMA_Channels use DMACH_count instead
5956 +
5957 +enum
5958 +{
5959 + DMAC_run_b = 0, //
5960 + DMAC_run_m = 0x00000001, //
5961 + DMAC_dm_b = 1, // done mask
5962 + DMAC_dm_m = 0x00000002, //
5963 + DMAC_mode_b = 2, //
5964 + DMAC_mode_m = 0x0000000c, //
5965 + DMAC_mode_auto_v = 0,
5966 + DMAC_mode_burst_v = 1,
5967 + DMAC_mode_transfer_v = 2, //usually used
5968 + DMAC_mode_reserved_v = 3,
5969 + DMAC_a_b = 4, //
5970 + DMAC_a_m = 0x00000010, //
5971 +
5972 + DMAS_f_b = 0, // finished (sticky)
5973 + DMAS_f_m = 0x00000001, //
5974 + DMAS_d_b = 1, // done (sticky)
5975 + DMAS_d_m = 0x00000002, //
5976 + DMAS_c_b = 2, // chain (sticky)
5977 + DMAS_c_m = 0x00000004, //
5978 + DMAS_e_b = 3, // error (sticky)
5979 + DMAS_e_m = 0x00000008, //
5980 + DMAS_h_b = 4, // halt (sticky)
5981 + DMAS_h_m = 0x00000010, //
5982 +
5983 + DMASM_f_b = 0, // finished (1=mask)
5984 + DMASM_f_m = 0x00000001, //
5985 + DMASM_d_b = 1, // done (1=mask)
5986 + DMASM_d_m = 0x00000002, //
5987 + DMASM_c_b = 2, // chain (1=mask)
5988 + DMASM_c_m = 0x00000004, //
5989 + DMASM_e_b = 3, // error (1=mask)
5990 + DMASM_e_m = 0x00000008, //
5991 + DMASM_h_b = 4, // halt (1=mask)
5992 + DMASM_h_m = 0x00000010, //
5993 +} ;
5994 +
5995 +/*
5996 + * DMA channel definitions
5997 + */
5998 +
5999 +enum
6000 +{
6001 + DMACH_ethRcv0 = 0,
6002 + DMACH_ethXmt0 = 1,
6003 + DMACH_memToFifo = 2,
6004 + DMACH_fifoToMem = 3,
6005 + DMACH_pciToMem = 4,
6006 + DMACH_memToPci = 5,
6007 +
6008 + DMACH_count //must be last
6009 +};
6010 +
6011 +
6012 +typedef struct DMAC_s
6013 +{
6014 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
6015 +} volatile *DMA_t ;
6016 +
6017 +
6018 +/*
6019 + * External DMA parameters
6020 +*/
6021 +
6022 +enum
6023 +{
6024 + DMADEVCMD_ts_b = 0, // ts field in devcmd
6025 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
6026 + DMADEVCMD_ts_byte_v = 0,
6027 + DMADEVCMD_ts_halfword_v = 1,
6028 + DMADEVCMD_ts_word_v = 2,
6029 + DMADEVCMD_ts_2word_v = 3,
6030 + DMADEVCMD_ts_4word_v = 4,
6031 + DMADEVCMD_ts_6word_v = 5,
6032 + DMADEVCMD_ts_8word_v = 6,
6033 + DMADEVCMD_ts_16word_v = 7
6034 +};
6035 +
6036 +
6037 +#endif // __IDT_DMA_H__
6038 +
6039 +
6040 +
6041 +
6042 +
6043 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6044 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
6045 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-06-18 12:44:28.000000000 +0200
6046 @@ -0,0 +1,89 @@
6047 +/**************************************************************************
6048 + *
6049 + * BRIEF MODULE DESCRIPTION
6050 + * Definitions for DMA controller.
6051 + *
6052 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6053 + *
6054 + * This program is free software; you can redistribute it and/or modify it
6055 + * under the terms of the GNU General Public License as published by the
6056 + * Free Software Foundation; either version 2 of the License, or (at your
6057 + * option) any later version.
6058 + *
6059 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6060 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6061 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6062 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6063 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6064 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6065 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6066 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6067 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6068 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6069 + *
6070 + * You should have received a copy of the GNU General Public License along
6071 + * with this program; if not, write to the Free Software Foundation, Inc.,
6072 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6073 + *
6074 + *
6075 + **************************************************************************
6076 + * May 2004 rkt, neb.
6077 + *
6078 + * Initial Release
6079 + *
6080 + *
6081 + *
6082 + **************************************************************************
6083 + */
6084 +
6085 +#ifndef __IDT_DMA_V_H__
6086 +#define __IDT_DMA_V_H__
6087 +
6088 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
6089 +#include <asm/idt-boards/rc32434/rc32434.h>
6090 +
6091 +#define DMA_CHAN_OFFSET 0x14
6092 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6093 +#define DMA_COUNT(count) \
6094 + ((count) & DMAD_count_m)
6095 +
6096 +#define DMA_HALT_TIMEOUT 500
6097 +
6098 +
6099 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6100 +{
6101 + int timeout=1;
6102 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6103 + rc32434_writel(0, &ch->dmac);
6104 +
6105 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6106 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6107 + rc32434_writel(0, &ch->dmas);
6108 + break;
6109 + }
6110 + }
6111 +
6112 + }
6113 +
6114 + return timeout ? 0 : 1;
6115 +}
6116 +
6117 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6118 +{
6119 + rc32434_writel(0, &ch->dmandptr);
6120 + rc32434_writel(dma_addr, &ch->dmadptr);
6121 +}
6122 +
6123 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6124 +{
6125 + rc32434_writel(dma_addr, &ch->dmandptr);
6126 +}
6127 +
6128 +#endif // __IDT_DMA_V_H__
6129 +
6130 +
6131 +
6132 +
6133 +
6134 +
6135 +
6136 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6137 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
6138 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
6139 @@ -0,0 +1,333 @@
6140 +/**************************************************************************
6141 + *
6142 + * BRIEF MODULE DESCRIPTION
6143 + * Ethernet register definition
6144 + *
6145 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6146 + *
6147 + * This program is free software; you can redistribute it and/or modify it
6148 + * under the terms of the GNU General Public License as published by the
6149 + * Free Software Foundation; either version 2 of the License, or (at your
6150 + * option) any later version.
6151 + *
6152 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6153 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6154 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6155 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6156 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6157 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6158 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6159 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6160 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6161 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6162 + *
6163 + * You should have received a copy of the GNU General Public License along
6164 + * with this program; if not, write to the Free Software Foundation, Inc.,
6165 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6166 + *
6167 + *
6168 + **************************************************************************
6169 + * May 2004 rkt, neb.
6170 + *
6171 + * Initial Release
6172 + *
6173 + *
6174 + *
6175 + **************************************************************************
6176 + */
6177 +
6178 +#ifndef __IDT_ETH_H__
6179 +#define __IDT_ETH_H__
6180 +
6181 +
6182 +enum
6183 +{
6184 + ETH0_PhysicalAddress = 0x18060000,
6185 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
6186 +
6187 + ETH0_VirtualAddress = 0xb8060000,
6188 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
6189 +} ;
6190 +
6191 +typedef struct
6192 +{
6193 + u32 ethintfc ;
6194 + u32 ethfifott ;
6195 + u32 etharc ;
6196 + u32 ethhash0 ;
6197 + u32 ethhash1 ;
6198 + u32 ethu0 [4] ; // Reserved.
6199 + u32 ethpfs ;
6200 + u32 ethmcp ;
6201 + u32 eth_u1 [10] ; // Reserved.
6202 + u32 ethspare ;
6203 + u32 eth_u2 [42] ; // Reserved.
6204 + u32 ethsal0 ;
6205 + u32 ethsah0 ;
6206 + u32 ethsal1 ;
6207 + u32 ethsah1 ;
6208 + u32 ethsal2 ;
6209 + u32 ethsah2 ;
6210 + u32 ethsal3 ;
6211 + u32 ethsah3 ;
6212 + u32 ethrbc ;
6213 + u32 ethrpc ;
6214 + u32 ethrupc ;
6215 + u32 ethrfc ;
6216 + u32 ethtbc ;
6217 + u32 ethgpf ;
6218 + u32 eth_u9 [50] ; // Reserved.
6219 + u32 ethmac1 ;
6220 + u32 ethmac2 ;
6221 + u32 ethipgt ;
6222 + u32 ethipgr ;
6223 + u32 ethclrt ;
6224 + u32 ethmaxf ;
6225 + u32 eth_u10 ; // Reserved.
6226 + u32 ethmtest ;
6227 + u32 miimcfg ;
6228 + u32 miimcmd ;
6229 + u32 miimaddr ;
6230 + u32 miimwtd ;
6231 + u32 miimrdd ;
6232 + u32 miimind ;
6233 + u32 eth_u11 ; // Reserved.
6234 + u32 eth_u12 ; // Reserved.
6235 + u32 ethcfsa0 ;
6236 + u32 ethcfsa1 ;
6237 + u32 ethcfsa2 ;
6238 +} volatile *ETH_t;
6239 +
6240 +enum
6241 +{
6242 + ETHINTFC_en_b = 0,
6243 + ETHINTFC_en_m = 0x00000001,
6244 + ETHINTFC_its_b = 1,
6245 + ETHINTFC_its_m = 0x00000002,
6246 + ETHINTFC_rip_b = 2,
6247 + ETHINTFC_rip_m = 0x00000004,
6248 + ETHINTFC_jam_b = 3,
6249 + ETHINTFC_jam_m = 0x00000008,
6250 + ETHINTFC_ovr_b = 4,
6251 + ETHINTFC_ovr_m = 0x00000010,
6252 + ETHINTFC_und_b = 5,
6253 + ETHINTFC_und_m = 0x00000020,
6254 +
6255 + ETHFIFOTT_tth_b = 0,
6256 + ETHFIFOTT_tth_m = 0x0000007f,
6257 +
6258 + ETHARC_pro_b = 0,
6259 + ETHARC_pro_m = 0x00000001,
6260 + ETHARC_am_b = 1,
6261 + ETHARC_am_m = 0x00000002,
6262 + ETHARC_afm_b = 2,
6263 + ETHARC_afm_m = 0x00000004,
6264 + ETHARC_ab_b = 3,
6265 + ETHARC_ab_m = 0x00000008,
6266 +
6267 + ETHSAL_byte5_b = 0,
6268 + ETHSAL_byte5_m = 0x000000ff,
6269 + ETHSAL_byte4_b = 8,
6270 + ETHSAL_byte4_m = 0x0000ff00,
6271 + ETHSAL_byte3_b = 16,
6272 + ETHSAL_byte3_m = 0x00ff0000,
6273 + ETHSAL_byte2_b = 24,
6274 + ETHSAL_byte2_m = 0xff000000,
6275 +
6276 + ETHSAH_byte1_b = 0,
6277 + ETHSAH_byte1_m = 0x000000ff,
6278 + ETHSAH_byte0_b = 8,
6279 + ETHSAH_byte0_m = 0x0000ff00,
6280 +
6281 + ETHGPF_ptv_b = 0,
6282 + ETHGPF_ptv_m = 0x0000ffff,
6283 +
6284 + ETHPFS_pfd_b = 0,
6285 + ETHPFS_pfd_m = 0x00000001,
6286 +
6287 + ETHCFSA0_cfsa4_b = 0,
6288 + ETHCFSA0_cfsa4_m = 0x000000ff,
6289 + ETHCFSA0_cfsa5_b = 8,
6290 + ETHCFSA0_cfsa5_m = 0x0000ff00,
6291 +
6292 + ETHCFSA1_cfsa2_b = 0,
6293 + ETHCFSA1_cfsa2_m = 0x000000ff,
6294 + ETHCFSA1_cfsa3_b = 8,
6295 + ETHCFSA1_cfsa3_m = 0x0000ff00,
6296 +
6297 + ETHCFSA2_cfsa0_b = 0,
6298 + ETHCFSA2_cfsa0_m = 0x000000ff,
6299 + ETHCFSA2_cfsa1_b = 8,
6300 + ETHCFSA2_cfsa1_m = 0x0000ff00,
6301 +
6302 + ETHMAC1_re_b = 0,
6303 + ETHMAC1_re_m = 0x00000001,
6304 + ETHMAC1_paf_b = 1,
6305 + ETHMAC1_paf_m = 0x00000002,
6306 + ETHMAC1_rfc_b = 2,
6307 + ETHMAC1_rfc_m = 0x00000004,
6308 + ETHMAC1_tfc_b = 3,
6309 + ETHMAC1_tfc_m = 0x00000008,
6310 + ETHMAC1_lb_b = 4,
6311 + ETHMAC1_lb_m = 0x00000010,
6312 + ETHMAC1_mr_b = 31,
6313 + ETHMAC1_mr_m = 0x80000000,
6314 +
6315 + ETHMAC2_fd_b = 0,
6316 + ETHMAC2_fd_m = 0x00000001,
6317 + ETHMAC2_flc_b = 1,
6318 + ETHMAC2_flc_m = 0x00000002,
6319 + ETHMAC2_hfe_b = 2,
6320 + ETHMAC2_hfe_m = 0x00000004,
6321 + ETHMAC2_dc_b = 3,
6322 + ETHMAC2_dc_m = 0x00000008,
6323 + ETHMAC2_cen_b = 4,
6324 + ETHMAC2_cen_m = 0x00000010,
6325 + ETHMAC2_pe_b = 5,
6326 + ETHMAC2_pe_m = 0x00000020,
6327 + ETHMAC2_vpe_b = 6,
6328 + ETHMAC2_vpe_m = 0x00000040,
6329 + ETHMAC2_ape_b = 7,
6330 + ETHMAC2_ape_m = 0x00000080,
6331 + ETHMAC2_ppe_b = 8,
6332 + ETHMAC2_ppe_m = 0x00000100,
6333 + ETHMAC2_lpe_b = 9,
6334 + ETHMAC2_lpe_m = 0x00000200,
6335 + ETHMAC2_nb_b = 12,
6336 + ETHMAC2_nb_m = 0x00001000,
6337 + ETHMAC2_bp_b = 13,
6338 + ETHMAC2_bp_m = 0x00002000,
6339 + ETHMAC2_ed_b = 14,
6340 + ETHMAC2_ed_m = 0x00004000,
6341 +
6342 + ETHIPGT_ipgt_b = 0,
6343 + ETHIPGT_ipgt_m = 0x0000007f,
6344 +
6345 + ETHIPGR_ipgr2_b = 0,
6346 + ETHIPGR_ipgr2_m = 0x0000007f,
6347 + ETHIPGR_ipgr1_b = 8,
6348 + ETHIPGR_ipgr1_m = 0x00007f00,
6349 +
6350 + ETHCLRT_maxret_b = 0,
6351 + ETHCLRT_maxret_m = 0x0000000f,
6352 + ETHCLRT_colwin_b = 8,
6353 + ETHCLRT_colwin_m = 0x00003f00,
6354 +
6355 + ETHMAXF_maxf_b = 0,
6356 + ETHMAXF_maxf_m = 0x0000ffff,
6357 +
6358 + ETHMTEST_tb_b = 2,
6359 + ETHMTEST_tb_m = 0x00000004,
6360 +
6361 + ETHMCP_div_b = 0,
6362 + ETHMCP_div_m = 0x000000ff,
6363 +
6364 + MIIMCFG_rsv_b = 0,
6365 + MIIMCFG_rsv_m = 0x0000000c,
6366 +
6367 + MIIMCMD_rd_b = 0,
6368 + MIIMCMD_rd_m = 0x00000001,
6369 + MIIMCMD_scn_b = 1,
6370 + MIIMCMD_scn_m = 0x00000002,
6371 +
6372 + MIIMADDR_regaddr_b = 0,
6373 + MIIMADDR_regaddr_m = 0x0000001f,
6374 + MIIMADDR_phyaddr_b = 8,
6375 + MIIMADDR_phyaddr_m = 0x00001f00,
6376 +
6377 + MIIMWTD_wdata_b = 0,
6378 + MIIMWTD_wdata_m = 0x0000ffff,
6379 +
6380 + MIIMRDD_rdata_b = 0,
6381 + MIIMRDD_rdata_m = 0x0000ffff,
6382 +
6383 + MIIMIND_bsy_b = 0,
6384 + MIIMIND_bsy_m = 0x00000001,
6385 + MIIMIND_scn_b = 1,
6386 + MIIMIND_scn_m = 0x00000002,
6387 + MIIMIND_nv_b = 2,
6388 + MIIMIND_nv_m = 0x00000004,
6389 +
6390 +} ;
6391 +
6392 +/*
6393 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6394 + */
6395 +enum
6396 +{
6397 + ETHRX_fd_b = 0,
6398 + ETHRX_fd_m = 0x00000001,
6399 + ETHRX_ld_b = 1,
6400 + ETHRX_ld_m = 0x00000002,
6401 + ETHRX_rok_b = 2,
6402 + ETHRX_rok_m = 0x00000004,
6403 + ETHRX_fm_b = 3,
6404 + ETHRX_fm_m = 0x00000008,
6405 + ETHRX_mp_b = 4,
6406 + ETHRX_mp_m = 0x00000010,
6407 + ETHRX_bp_b = 5,
6408 + ETHRX_bp_m = 0x00000020,
6409 + ETHRX_vlt_b = 6,
6410 + ETHRX_vlt_m = 0x00000040,
6411 + ETHRX_cf_b = 7,
6412 + ETHRX_cf_m = 0x00000080,
6413 + ETHRX_ovr_b = 8,
6414 + ETHRX_ovr_m = 0x00000100,
6415 + ETHRX_crc_b = 9,
6416 + ETHRX_crc_m = 0x00000200,
6417 + ETHRX_cv_b = 10,
6418 + ETHRX_cv_m = 0x00000400,
6419 + ETHRX_db_b = 11,
6420 + ETHRX_db_m = 0x00000800,
6421 + ETHRX_le_b = 12,
6422 + ETHRX_le_m = 0x00001000,
6423 + ETHRX_lor_b = 13,
6424 + ETHRX_lor_m = 0x00002000,
6425 + ETHRX_ces_b = 14,
6426 + ETHRX_ces_m = 0x00004000,
6427 + ETHRX_length_b = 16,
6428 + ETHRX_length_m = 0xffff0000,
6429 +
6430 + ETHTX_fd_b = 0,
6431 + ETHTX_fd_m = 0x00000001,
6432 + ETHTX_ld_b = 1,
6433 + ETHTX_ld_m = 0x00000002,
6434 + ETHTX_oen_b = 2,
6435 + ETHTX_oen_m = 0x00000004,
6436 + ETHTX_pen_b = 3,
6437 + ETHTX_pen_m = 0x00000008,
6438 + ETHTX_cen_b = 4,
6439 + ETHTX_cen_m = 0x00000010,
6440 + ETHTX_hen_b = 5,
6441 + ETHTX_hen_m = 0x00000020,
6442 + ETHTX_tok_b = 6,
6443 + ETHTX_tok_m = 0x00000040,
6444 + ETHTX_mp_b = 7,
6445 + ETHTX_mp_m = 0x00000080,
6446 + ETHTX_bp_b = 8,
6447 + ETHTX_bp_m = 0x00000100,
6448 + ETHTX_und_b = 9,
6449 + ETHTX_und_m = 0x00000200,
6450 + ETHTX_of_b = 10,
6451 + ETHTX_of_m = 0x00000400,
6452 + ETHTX_ed_b = 11,
6453 + ETHTX_ed_m = 0x00000800,
6454 + ETHTX_ec_b = 12,
6455 + ETHTX_ec_m = 0x00001000,
6456 + ETHTX_lc_b = 13,
6457 + ETHTX_lc_m = 0x00002000,
6458 + ETHTX_td_b = 14,
6459 + ETHTX_td_m = 0x00004000,
6460 + ETHTX_crc_b = 15,
6461 + ETHTX_crc_m = 0x00008000,
6462 + ETHTX_le_b = 16,
6463 + ETHTX_le_m = 0x00010000,
6464 + ETHTX_cc_b = 17,
6465 + ETHTX_cc_m = 0x001E0000,
6466 +} ;
6467 +
6468 +#endif // __IDT_ETH_H__
6469 +
6470 +
6471 +
6472 +
6473 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6474 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
6475 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-06-18 12:44:28.000000000 +0200
6476 @@ -0,0 +1,77 @@
6477 +/**************************************************************************
6478 + *
6479 + * BRIEF MODULE DESCRIPTION
6480 + * Ethernet register definition
6481 + *
6482 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6483 + *
6484 + * This program is free software; you can redistribute it and/or modify it
6485 + * under the terms of the GNU General Public License as published by the
6486 + * Free Software Foundation; either version 2 of the License, or (at your
6487 + * option) any later version.
6488 + *
6489 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6490 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6491 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6492 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6493 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6494 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6495 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6496 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6497 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6498 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6499 + *
6500 + * You should have received a copy of the GNU General Public License along
6501 + * with this program; if not, write to the Free Software Foundation, Inc.,
6502 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6503 + *
6504 + *
6505 + **************************************************************************
6506 + * May 2004 rkt, neb.
6507 + *
6508 + * Initial Release
6509 + *
6510 + *
6511 + *
6512 + **************************************************************************
6513 + */
6514 +
6515 +#ifndef __IDT_ETH_V_H__
6516 +#define __IDT_ETH_V_H__
6517 +
6518 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
6519 +
6520 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
6521 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
6522 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
6523 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
6524 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
6525 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
6526 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
6527 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
6528 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
6529 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
6530 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
6531 +
6532 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
6533 +
6534 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
6535 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
6536 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
6537 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
6538 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
6539 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
6540 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
6541 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
6542 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
6543 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
6544 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
6545 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
6546 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
6547 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
6548 +#endif // __IDT_ETH_V_H__
6549 +
6550 +
6551 +
6552 +
6553 +
6554 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6555 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
6556 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-06-18 12:44:28.000000000 +0200
6557 @@ -0,0 +1,167 @@
6558 +/**************************************************************************
6559 + *
6560 + * BRIEF MODULE DESCRIPTION
6561 + * GPIO register definition
6562 + *
6563 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6564 + *
6565 + * This program is free software; you can redistribute it and/or modify it
6566 + * under the terms of the GNU General Public License as published by the
6567 + * Free Software Foundation; either version 2 of the License, or (at your
6568 + * option) any later version.
6569 + *
6570 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6571 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6572 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6573 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6574 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6575 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6576 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6577 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6578 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6579 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6580 + *
6581 + * You should have received a copy of the GNU General Public License along
6582 + * with this program; if not, write to the Free Software Foundation, Inc.,
6583 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6584 + *
6585 + *
6586 + **************************************************************************
6587 + * May 2004 rkt, neb.
6588 + *
6589 + * Initial Release
6590 + *
6591 + *
6592 + *
6593 + **************************************************************************
6594 + */
6595 +
6596 +#ifndef __IDT_GPIO_H__
6597 +#define __IDT_GPIO_H__
6598 +
6599 +enum
6600 +{
6601 + GPIO0_PhysicalAddress = 0x18050000,
6602 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
6603 +
6604 + GPIO0_VirtualAddress = 0xb8050000,
6605 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
6606 +} ;
6607 +
6608 +typedef struct
6609 +{
6610 + u32 gpiofunc; /* GPIO Function Register
6611 + * gpiofunc[x]==0 bit = gpio
6612 + * func[x]==1 bit = altfunc
6613 + */
6614 + u32 gpiocfg; /* GPIO Configuration Register
6615 + * gpiocfg[x]==0 bit = input
6616 + * gpiocfg[x]==1 bit = output
6617 + */
6618 + u32 gpiod; /* GPIO Data Register
6619 + * gpiod[x] read/write gpio pinX status
6620 + */
6621 + u32 gpioilevel; /* GPIO Interrupt Status Register
6622 + * interrupt level (see gpioistat)
6623 + */
6624 + u32 gpioistat; /* Gpio Interrupt Status Register
6625 + * istat[x] = (gpiod[x] == level[x])
6626 + * cleared in ISR (STICKY bits)
6627 + */
6628 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
6629 +} volatile * GPIO_t ;
6630 +
6631 +typedef enum
6632 +{
6633 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
6634 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
6635 + GPIO_input_v = 0, // gpiocfg use pin as input.
6636 + GPIO_output_v = 1, // gpiocfg use pin as output.
6637 + GPIO_pin0_b = 0,
6638 + GPIO_pin0_m = 0x00000001,
6639 + GPIO_pin1_b = 1,
6640 + GPIO_pin1_m = 0x00000002,
6641 + GPIO_pin2_b = 2,
6642 + GPIO_pin2_m = 0x00000004,
6643 + GPIO_pin3_b = 3,
6644 + GPIO_pin3_m = 0x00000008,
6645 + GPIO_pin4_b = 4,
6646 + GPIO_pin4_m = 0x00000010,
6647 + GPIO_pin5_b = 5,
6648 + GPIO_pin5_m = 0x00000020,
6649 + GPIO_pin6_b = 6,
6650 + GPIO_pin6_m = 0x00000040,
6651 + GPIO_pin7_b = 7,
6652 + GPIO_pin7_m = 0x00000080,
6653 + GPIO_pin8_b = 8,
6654 + GPIO_pin8_m = 0x00000100,
6655 + GPIO_pin9_b = 9,
6656 + GPIO_pin9_m = 0x00000200,
6657 + GPIO_pin10_b = 10,
6658 + GPIO_pin10_m = 0x00000400,
6659 + GPIO_pin11_b = 11,
6660 + GPIO_pin11_m = 0x00000800,
6661 + GPIO_pin12_b = 12,
6662 + GPIO_pin12_m = 0x00001000,
6663 + GPIO_pin13_b = 13,
6664 + GPIO_pin13_m = 0x00002000,
6665 +
6666 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
6667 +
6668 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
6669 + GPIO_u0sout_m = GPIO_pin0_m,
6670 + GPIO_u0sout_cfg_v = GPIO_output_v,
6671 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
6672 + GPIO_u0sinp_m = GPIO_pin1_m,
6673 + GPIO_u0sinp_cfg_v = GPIO_input_v,
6674 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
6675 + GPIO_u0rtsn_m = GPIO_pin2_m,
6676 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
6677 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
6678 + GPIO_u0ctsn_m = GPIO_pin3_m,
6679 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
6680 +
6681 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
6682 + GPIO_maddr22_m = GPIO_pin4_m,
6683 + GPIO_maddr22_cfg_v = GPIO_output_v,
6684 +
6685 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
6686 + GPIO_maddr23_m = GPIO_pin5_m,
6687 + GPIO_maddr23_cfg_v = GPIO_output_v,
6688 +
6689 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
6690 + GPIO_maddr24_m = GPIO_pin6_m,
6691 + GPIO_maddr24_cfg_v = GPIO_output_v,
6692 +
6693 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
6694 + GPIO_maddr25_m = GPIO_pin7_m,
6695 + GPIO_maddr25_cfg_v = GPIO_output_v,
6696 +
6697 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
6698 + GPIO_cpudmadebug_m = GPIO_pin8_m,
6699 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
6700 +
6701 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
6702 + GPIO_pcireq4_m = GPIO_pin9_m,
6703 + GPIO_pcireq4_cfg_v = GPIO_input_v,
6704 +
6705 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
6706 + GPIO_pcigrant4_m = GPIO_pin10_m,
6707 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
6708 +
6709 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
6710 + GPIO_pcireq5_m = GPIO_pin11_m,
6711 + GPIO_pcireq5_cfg_v = GPIO_input_v,
6712 +
6713 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
6714 + GPIO_pcigrant5_m = GPIO_pin12_m,
6715 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
6716 +
6717 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
6718 + GPIO_pcimuintn_m = GPIO_pin13_m,
6719 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
6720 +
6721 +} GPIO_DEFS_t;
6722 +
6723 +#endif // __IDT_GPIO_H__
6724 +
6725 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6726 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
6727 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-06-18 12:44:28.000000000 +0200
6728 @@ -0,0 +1,199 @@
6729 + /**************************************************************************
6730 + *
6731 + * BRIEF MODULE DESCRIPTION
6732 + * Definitions for IDT RC32434 CPU
6733 + *
6734 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6735 + *
6736 + * This program is free software; you can redistribute it and/or modify it
6737 + * under the terms of the GNU General Public License as published by the
6738 + * Free Software Foundation; either version 2 of the License, or (at your
6739 + * option) any later version.
6740 + *
6741 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6742 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6743 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6744 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6745 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6746 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6747 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6748 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6749 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6750 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6751 + *
6752 + * You should have received a copy of the GNU General Public License along
6753 + * with this program; if not, write to the Free Software Foundation, Inc.,
6754 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6755 + *
6756 + *
6757 + **************************************************************************
6758 + * May 2004 rkt, neb.
6759 + *
6760 + * Initial Release
6761 + *
6762 + *
6763 + *
6764 + **************************************************************************
6765 + */
6766 +
6767 +#ifndef _RC32434_H_
6768 +#define _RC32434_H_
6769 +
6770 +#include <linux/config.h>
6771 +#include <linux/delay.h>
6772 +#include <asm/io.h>
6773 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6774 +
6775 +#define RC32434_REG_BASE 0x18000000
6776 +
6777 +
6778 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6779 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
6780 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6781 +
6782 +#define IDT_CLOCK_MULT 2
6783 +#define MIPS_CPU_TIMER_IRQ 7
6784 +/* Interrupt Controller */
6785 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
6786 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
6787 +#define IC_GROUP_OFFSET 0x0C
6788 +#define RTC_BASE 0xBA001FF0
6789 +
6790 +#define NUM_INTR_GROUPS 5
6791 +/* 16550 UARTs */
6792 +
6793 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
6794 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6795 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6796 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6797 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6798 +
6799 +#ifdef __MIPSEB__
6800 +
6801 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6802 +#define EB434_UART1_BASE (0x19800003)
6803 +
6804 +#else
6805 +
6806 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6807 +#define EB434_UART1_BASE (0x19800000)
6808 +
6809 +#endif
6810 +
6811 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
6812 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
6813 +
6814 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
6815 +
6816 +/* cpu pipeline flush */
6817 +static inline void rc32434_sync(void)
6818 +{
6819 + __asm__ volatile ("sync");
6820 +}
6821 +
6822 +static inline void rc32434_sync_udelay(int us)
6823 +{
6824 + __asm__ volatile ("sync");
6825 + udelay(us);
6826 +}
6827 +
6828 +static inline void rc32434_sync_delay(int ms)
6829 +{
6830 + __asm__ volatile ("sync");
6831 + mdelay(ms);
6832 +}
6833 +
6834 +
6835 +
6836 +/*
6837 + * Macros to access internal RC32434 registers. No byte
6838 + * swapping should be done when accessing the internal
6839 + * registers.
6840 + */
6841 +
6842 +#define rc32434_readb __raw_readb
6843 +#define rc32434_readw __raw_readw
6844 +#define rc32434_readl __raw_readl
6845 +
6846 +#define rc32434_writeb __raw_writeb
6847 +#define rc32434_writew __raw_writew
6848 +#define rc32434_writel __raw_writel
6849 +
6850 +#if 0
6851 +static inline u8 rc32434_readb(unsigned long pa)
6852 +{
6853 + return *((volatile u8 *)KSEG1ADDR(pa));
6854 +}
6855 +static inline u16 rc32434_readw(unsigned long pa)
6856 +{
6857 + return *((volatile u16 *)KSEG1ADDR(pa));
6858 +}
6859 +static inline u32 rc32434_readl(unsigned long pa)
6860 +{
6861 + return *((volatile u32 *)KSEG1ADDR(pa));
6862 +}
6863 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6864 +{
6865 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
6866 +}
6867 +static inline void rc32434_writew(u16 val, unsigned long pa)
6868 +{
6869 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
6870 +}
6871 +static inline void rc32434_writel(u32 val, unsigned long pa)
6872 +{
6873 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
6874 +}
6875 +
6876 +#endif
6877 +
6878 +
6879 +/*
6880 + * C access to CLZ and CLO instructions
6881 + * (count leading zeroes/ones).
6882 + */
6883 +static inline int rc32434_clz(unsigned long val)
6884 +{
6885 + int ret;
6886 + __asm__ volatile (
6887 + ".set\tnoreorder\n\t"
6888 + ".set\tnoat\n\t"
6889 + ".set\tmips32\n\t"
6890 + "clz\t%0,%1\n\t"
6891 + ".set\tmips0\n\t"
6892 + ".set\tat\n\t"
6893 + ".set\treorder"
6894 + : "=r" (ret)
6895 + : "r" (val));
6896 +
6897 + return ret;
6898 +}
6899 +static inline int rc32434_clo(unsigned long val)
6900 +{
6901 + int ret;
6902 + __asm__ volatile (
6903 + ".set\tnoreorder\n\t"
6904 + ".set\tnoat\n\t"
6905 + ".set\tmips32\n\t"
6906 + "clo\t%0,%1\n\t"
6907 + ".set\tmips0\n\t"
6908 + ".set\tat\n\t"
6909 + ".set\treorder"
6910 + : "=r" (ret)
6911 + : "r" (val));
6912 +
6913 + return ret;
6914 +}
6915 +#endif /* _RC32434_H_ */
6916 +
6917 +
6918 +
6919 +
6920 +
6921 +
6922 +
6923 +
6924 +
6925 +
6926 +
6927 +
6928 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6929 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
6930 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-06-18 12:44:28.000000000 +0200
6931 @@ -0,0 +1,90 @@
6932 +/**************************************************************************
6933 + *
6934 + * BRIEF MODULE DESCRIPTION
6935 + * System Integrity register definition
6936 + *
6937 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6938 + *
6939 + * This program is free software; you can redistribute it and/or modify it
6940 + * under the terms of the GNU General Public License as published by the
6941 + * Free Software Foundation; either version 2 of the License, or (at your
6942 + * option) any later version.
6943 + *
6944 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6945 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6946 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6947 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6948 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6949 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6950 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6951 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6952 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6953 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6954 + *
6955 + * You should have received a copy of the GNU General Public License along
6956 + * with this program; if not, write to the Free Software Foundation, Inc.,
6957 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6958 + *
6959 + *
6960 + **************************************************************************
6961 + * May 2004 rkt, neb
6962 + *
6963 + * Initial Release
6964 + *
6965 + *
6966 + *
6967 + **************************************************************************
6968 + */
6969 +
6970 +#ifndef __IDT_INTEG_H__
6971 +#define __IDT_INTEG_H__
6972 +
6973 +enum
6974 +{
6975 + INTEG0_PhysicalAddress = 0x18030000,
6976 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
6977 +
6978 + INTEG0_VirtualAddress = 0xB8030000,
6979 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
6980 +} ;
6981 +
6982 +// if you are looking for CEA, try rst.h
6983 +typedef struct
6984 +{
6985 + u32 filler [0xc] ; // 0x30 bytes unused.
6986 + u32 errcs ; // sticky use ERRCS_
6987 + u32 wtcount ; // Watchdog timer count reg.
6988 + u32 wtcompare ; // Watchdog timer timeout value.
6989 + u32 wtc ; // Watchdog timer control. use WTC_
6990 +} volatile *INTEG_t ;
6991 +
6992 +enum
6993 +{
6994 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
6995 + ERRCS_wto_m = 0x00000001,
6996 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
6997 + ERRCS_wne_m = 0x00000002,
6998 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
6999 + ERRCS_ucw_m = 0x00000004,
7000 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
7001 + ERRCS_ucr_m = 0x00000008,
7002 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
7003 + ERRCS_upw_m = 0x00000010,
7004 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
7005 + ERRCS_upr_m = 0x00000020,
7006 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
7007 + ERRCS_udw_m = 0x00000040,
7008 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
7009 + ERRCS_udr_m = 0x00000080,
7010 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
7011 + ERRCS_sae_m = 0x00000100,
7012 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
7013 + ERRCS_wre_m = 0x00000200,
7014 +
7015 + WTC_en_b = 0, // In INTEG_t -> wtc
7016 + WTC_en_m = 0x00000001,
7017 + WTC_to_b = 1, // In INTEG_t -> wtc
7018 + WTC_to_m = 0x00000002,
7019 +} ;
7020 +
7021 +#endif // __IDT_INTEG_H__
7022 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7023 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
7024 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-06-18 12:44:28.000000000 +0200
7025 @@ -0,0 +1,174 @@
7026 +/**************************************************************************
7027 + *
7028 + * BRIEF MODULE DESCRIPTION
7029 + * Interrupt Controller register definition.
7030 + *
7031 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7032 + *
7033 + * This program is free software; you can redistribute it and/or modify it
7034 + * under the terms of the GNU General Public License as published by the
7035 + * Free Software Foundation; either version 2 of the License, or (at your
7036 + * option) any later version.
7037 + *
7038 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7039 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7040 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7041 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7042 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7043 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7044 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7045 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7046 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7047 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7048 + *
7049 + * You should have received a copy of the GNU General Public License along
7050 + * with this program; if not, write to the Free Software Foundation, Inc.,
7051 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7052 + *
7053 + *
7054 + **************************************************************************
7055 + * May 2004 rkt, neb.
7056 + *
7057 + * Initial Release
7058 + *
7059 + *
7060 + *
7061 + **************************************************************************
7062 + */
7063 +
7064 +#ifndef __IDT_INT_H__
7065 +#define __IDT_INT_H__
7066 +
7067 +enum
7068 +{
7069 + INT0_PhysicalAddress = 0x18038000,
7070 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
7071 +
7072 + INT0_VirtualAddress = 0xB8038000,
7073 + INT_VirtualAddress = INT0_VirtualAddress, // Default
7074 +} ;
7075 +
7076 +struct INT_s
7077 +{
7078 + u32 ipend ; //Pending interrupts. use INT?_
7079 + u32 itest ; //Test bits. use INT?_
7080 + u32 imask ; //Interrupt disabled when set. use INT?_
7081 +} ;
7082 +
7083 +enum
7084 +{
7085 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
7086 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
7087 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
7088 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
7089 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
7090 +
7091 + IPEND_count, // must be last (used in loops)
7092 + IPEND_min = IPEND2 // min IPEND (used in loops)
7093 +};
7094 +
7095 +typedef struct INTC_s
7096 +{
7097 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
7098 + u32 nmips ; // use NMIPS_
7099 +} volatile *INT_t ;
7100 +
7101 +enum
7102 +{
7103 + INT2_timer0_b = 0,
7104 + INT2_timer0_m = 0x00000001,
7105 + INT2_timer1_b = 1,
7106 + INT2_timer1_m = 0x00000002,
7107 + INT2_timer2_b = 2,
7108 + INT2_timer2_m = 0x00000004,
7109 + INT2_refresh_b = 3,
7110 + INT2_refresh_m = 0x00000008,
7111 + INT2_watchdogTimeout_b = 4,
7112 + INT2_watchdogTimeout_m = 0x00000010,
7113 + INT2_undecodedCpuWrite_b = 5,
7114 + INT2_undecodedCpuWrite_m = 0x00000020,
7115 + INT2_undecodedCpuRead_b = 6,
7116 + INT2_undecodedCpuRead_m = 0x00000040,
7117 + INT2_undecodedPciWrite_b = 7,
7118 + INT2_undecodedPciWrite_m = 0x00000080,
7119 + INT2_undecodedPciRead_b = 8,
7120 + INT2_undecodedPciRead_m = 0x00000100,
7121 + INT2_undecodedDmaWrite_b = 9,
7122 + INT2_undecodedDmaWrite_m = 0x00000200,
7123 + INT2_undecodedDmaRead_b = 10,
7124 + INT2_undecodedDmaRead_m = 0x00000400,
7125 + INT2_ipBusSlaveAckError_b = 11,
7126 + INT2_ipBusSlaveAckError_m = 0x00000800,
7127 +
7128 + INT3_dmaChannel0_b = 0,
7129 + INT3_dmaChannel0_m = 0x00000001,
7130 + INT3_dmaChannel1_b = 1,
7131 + INT3_dmaChannel1_m = 0x00000002,
7132 + INT3_dmaChannel2_b = 2,
7133 + INT3_dmaChannel2_m = 0x00000004,
7134 + INT3_dmaChannel3_b = 3,
7135 + INT3_dmaChannel3_m = 0x00000008,
7136 + INT3_dmaChannel4_b = 4,
7137 + INT3_dmaChannel4_m = 0x00000010,
7138 + INT3_dmaChannel5_b = 5,
7139 + INT3_dmaChannel5_m = 0x00000020,
7140 +
7141 + INT5_uartGeneral0_b = 0,
7142 + INT5_uartGeneral0_m = 0x00000001,
7143 + INT5_uartTxrdy0_b = 1,
7144 + INT5_uartTxrdy0_m = 0x00000002,
7145 + INT5_uartRxrdy0_b = 2,
7146 + INT5_uartRxrdy0_m = 0x00000004,
7147 + INT5_pci_b = 3,
7148 + INT5_pci_m = 0x00000008,
7149 + INT5_pciDecoupled_b = 4,
7150 + INT5_pciDecoupled_m = 0x00000010,
7151 + INT5_spi_b = 5,
7152 + INT5_spi_m = 0x00000020,
7153 + INT5_deviceDecoupled_b = 6,
7154 + INT5_deviceDecoupled_m = 0x00000040,
7155 + INT5_eth0Ovr_b = 9,
7156 + INT5_eth0Ovr_m = 0x00000200,
7157 + INT5_eth0Und_b = 10,
7158 + INT5_eth0Und_m = 0x00000400,
7159 + INT5_eth0Pfd_b = 11,
7160 + INT5_eth0Pfd_m = 0x00000800,
7161 + INT5_nvram_b = 12,
7162 + INT5_nvram_m = 0x00001000,
7163 +
7164 + INT6_gpio0_b = 0,
7165 + INT6_gpio0_m = 0x00000001,
7166 + INT6_gpio1_b = 1,
7167 + INT6_gpio1_m = 0x00000002,
7168 + INT6_gpio2_b = 2,
7169 + INT6_gpio2_m = 0x00000004,
7170 + INT6_gpio3_b = 3,
7171 + INT6_gpio3_m = 0x00000008,
7172 + INT6_gpio4_b = 4,
7173 + INT6_gpio4_m = 0x00000010,
7174 + INT6_gpio5_b = 5,
7175 + INT6_gpio5_m = 0x00000020,
7176 + INT6_gpio6_b = 6,
7177 + INT6_gpio6_m = 0x00000040,
7178 + INT6_gpio7_b = 7,
7179 + INT6_gpio7_m = 0x00000080,
7180 + INT6_gpio8_b = 8,
7181 + INT6_gpio8_m = 0x00000100,
7182 + INT6_gpio9_b = 9,
7183 + INT6_gpio9_m = 0x00000200,
7184 + INT6_gpio10_b = 10,
7185 + INT6_gpio10_m = 0x00000400,
7186 + INT6_gpio11_b = 11,
7187 + INT6_gpio11_m = 0x00000800,
7188 + INT6_gpio12_b = 12,
7189 + INT6_gpio12_m = 0x00001000,
7190 + INT6_gpio13_b = 13,
7191 + INT6_gpio13_m = 0x00002000,
7192 +
7193 + NMIPS_gpio_b = 0,
7194 + NMIPS_gpio_m = 0x00000001,
7195 +} ;
7196 +
7197 +#endif // __IDT_INT_H__
7198 +
7199 +
7200 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7201 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
7202 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-06-18 12:44:28.000000000 +0200
7203 @@ -0,0 +1,111 @@
7204 +/**************************************************************************
7205 + *
7206 + * BRIEF MODULE DESCRIPTION
7207 + * IP Arbiter register definitions
7208 + *
7209 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7210 + *
7211 + * This program is free software; you can redistribute it and/or modify it
7212 + * under the terms of the GNU General Public License as published by the
7213 + * Free Software Foundation; either version 2 of the License, or (at your
7214 + * option) any later version.
7215 + *
7216 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7217 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7218 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7219 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7220 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7221 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7222 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7223 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7224 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7225 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7226 + *
7227 + * You should have received a copy of the GNU General Public License along
7228 + * with this program; if not, write to the Free Software Foundation, Inc.,
7229 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7230 + *
7231 + *
7232 + **************************************************************************
7233 + * May 2004 rkt,neb
7234 + *
7235 + * Initial Release
7236 + *
7237 + *
7238 + *
7239 + **************************************************************************
7240 + */
7241 +
7242 +#ifndef __IDT_IPARB_H__
7243 +#define __IDT_IPARB_H__
7244 +
7245 +enum
7246 +{
7247 + IPARB0_PhysicalAddress = 0x18048000,
7248 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
7249 +
7250 + IPARB0_VirtualAddress = 0xB8048000,
7251 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
7252 +} ;
7253 +
7254 +enum
7255 +{
7256 + IPABMXC_ethernet0Receive = 0,
7257 + IPABMXC_ethernet0Transmit = 1,
7258 + IPABMXC_memoryToHoldFifo = 2,
7259 + IPABMXC_holdFifoToMemory = 3,
7260 + IPABMXC_pciToMemory = 4,
7261 + IPABMXC_memoryToPci = 5,
7262 + IPABMXC_pciTarget = 6,
7263 + IPABMXC_pciTargetStart = 7,
7264 + IPABMXC_cpuToIpBus = 8,
7265 +
7266 + IPABMXC_Count, // Must be last in list !
7267 + IPABMXC_Min = IPABMXC_ethernet0Receive,
7268 +
7269 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
7270 +} ;
7271 +
7272 +typedef struct
7273 +{
7274 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
7275 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
7276 + u32 ipac ; // use IPAC_
7277 + u32 ipaitcc; // use IPAITCC_
7278 + u32 ipaspare ;
7279 +} volatile * IPARB_t ;
7280 +
7281 +enum
7282 +{
7283 + IPAC_dp_b = 0,
7284 + IPAC_dp_m = 0x00000001,
7285 + IPAC_dep_b = 1,
7286 + IPAC_dep_m = 0x00000002,
7287 + IPAC_drm_b = 2,
7288 + IPAC_drm_m = 0x00000004,
7289 + IPAC_dwm_b = 3,
7290 + IPAC_dwm_m = 0x00000008,
7291 + IPAC_msk_b = 4,
7292 + IPAC_msk_m = 0x00000010,
7293 +
7294 + IPAPC_ptc_b = 0,
7295 + IPAPC_ptc_m = 0x00003fff,
7296 + IPAPC_mf_b = 14,
7297 + IPAPC_mf_m = 0x00004000,
7298 + IPAPC_cptc_b = 16,
7299 + IPAPC_cptc_m = 0x3fff0000,
7300 +
7301 + IPAITCC_itcc = 0,
7302 + IPAITCC_itcc, = 0x000001ff,
7303 +
7304 + IPABMC_mtc_b = 0,
7305 + IPABMC_mtc_m = 0x00000fff,
7306 + IPABMC_p_b = 12,
7307 + IPABMC_p_m = 0x00003000,
7308 + IPABMC_msk_b = 14,
7309 + IPABMC_msk_m = 0x00004000,
7310 + IPABMC_cmtc_b = 16,
7311 + IPABMC_cmtc_m = 0x0fff0000,
7312 +};
7313 +
7314 +#endif // __IDT_IPARB_H__
7315 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7316 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
7317 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-06-18 12:44:28.000000000 +0200
7318 @@ -0,0 +1,695 @@
7319 +/**************************************************************************
7320 + *
7321 + * BRIEF MODULE DESCRIPTION
7322 + * PCI register definitio
7323 + *
7324 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7325 + *
7326 + * This program is free software; you can redistribute it and/or modify it
7327 + * under the terms of the GNU General Public License as published by the
7328 + * Free Software Foundation; either version 2 of the License, or (at your
7329 + * option) any later version.
7330 + *
7331 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7332 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7333 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7334 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7335 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7336 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7337 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7338 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7339 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7340 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7341 + *
7342 + * You should have received a copy of the GNU General Public License along
7343 + * with this program; if not, write to the Free Software Foundation, Inc.,
7344 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7345 + *
7346 + *
7347 + **************************************************************************
7348 + * May 2004 rkt, neb.
7349 + *
7350 + * Initial Release
7351 + *
7352 + *
7353 + *
7354 + **************************************************************************
7355 + */
7356 +
7357 +#ifndef __IDT_PCI_H__
7358 +#define __IDT_PCI_H__
7359 +
7360 +enum
7361 +{
7362 + PCI0_PhysicalAddress = 0x18080000,
7363 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
7364 +
7365 + PCI0_VirtualAddress = 0xB8080000,
7366 + PCI_VirtualAddress = PCI0_VirtualAddress,
7367 +} ;
7368 +
7369 +enum
7370 +{
7371 + PCI_LbaCount = 4, // Local base addresses.
7372 +} ;
7373 +
7374 +typedef struct
7375 +{
7376 + u32 a ; // Address.
7377 + u32 c ; // Control.
7378 + u32 m ; // mapping.
7379 +} PCI_Map_s ;
7380 +
7381 +typedef struct
7382 +{
7383 + u32 pcic ;
7384 + u32 pcis ;
7385 + u32 pcism ;
7386 + u32 pcicfga ;
7387 + u32 pcicfgd ;
7388 + PCI_Map_s pcilba [PCI_LbaCount] ;
7389 + u32 pcidac ;
7390 + u32 pcidas ;
7391 + u32 pcidasm ;
7392 + u32 pcidad ;
7393 + u32 pcidma8c ;
7394 + u32 pcidma9c ;
7395 + u32 pcitc ;
7396 +} volatile *PCI_t ;
7397 +
7398 +// PCI messaging unit.
7399 +enum
7400 +{
7401 + PCIM_Count = 2,
7402 +} ;
7403 +typedef struct
7404 +{
7405 + u32 pciim [PCIM_Count] ;
7406 + u32 pciom [PCIM_Count] ;
7407 + u32 pciid ;
7408 + u32 pciiic ;
7409 + u32 pciiim ;
7410 + u32 pciiod ;
7411 + u32 pciioic ;
7412 + u32 pciioim ;
7413 +} volatile *PCIM_t ;
7414 +
7415 +/*******************************************************************************
7416 + *
7417 + * PCI Control Register
7418 + *
7419 + ******************************************************************************/
7420 +enum
7421 +{
7422 + PCIC_en_b = 0,
7423 + PCIC_en_m = 0x00000001,
7424 + PCIC_tnr_b = 1,
7425 + PCIC_tnr_m = 0x00000002,
7426 + PCIC_sce_b = 2,
7427 + PCIC_sce_m = 0x00000004,
7428 + PCIC_ien_b = 3,
7429 + PCIC_ien_m = 0x00000008,
7430 + PCIC_aaa_b = 4,
7431 + PCIC_aaa_m = 0x00000010,
7432 + PCIC_eap_b = 5,
7433 + PCIC_eap_m = 0x00000020,
7434 + PCIC_pcim_b = 6,
7435 + PCIC_pcim_m = 0x000001c0,
7436 + PCIC_pcim_disabled_v = 0,
7437 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
7438 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
7439 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
7440 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
7441 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
7442 + PCIC_pcim_reserved6_v = 6,
7443 + PCIC_pcim_reserved7_v = 7,
7444 + PCIC_igm_b = 9,
7445 + PCIC_igm_m = 0x00000200,
7446 +} ;
7447 +
7448 +/*******************************************************************************
7449 + *
7450 + * PCI Status Register
7451 + *
7452 + ******************************************************************************/
7453 +enum {
7454 + PCIS_eed_b = 0,
7455 + PCIS_eed_m = 0x00000001,
7456 + PCIS_wr_b = 1,
7457 + PCIS_wr_m = 0x00000002,
7458 + PCIS_nmi_b = 2,
7459 + PCIS_nmi_m = 0x00000004,
7460 + PCIS_ii_b = 3,
7461 + PCIS_ii_m = 0x00000008,
7462 + PCIS_cwe_b = 4,
7463 + PCIS_cwe_m = 0x00000010,
7464 + PCIS_cre_b = 5,
7465 + PCIS_cre_m = 0x00000020,
7466 + PCIS_mdpe_b = 6,
7467 + PCIS_mdpe_m = 0x00000040,
7468 + PCIS_sta_b = 7,
7469 + PCIS_sta_m = 0x00000080,
7470 + PCIS_rta_b = 8,
7471 + PCIS_rta_m = 0x00000100,
7472 + PCIS_rma_b = 9,
7473 + PCIS_rma_m = 0x00000200,
7474 + PCIS_sse_b = 10,
7475 + PCIS_sse_m = 0x00000400,
7476 + PCIS_ose_b = 11,
7477 + PCIS_ose_m = 0x00000800,
7478 + PCIS_pe_b = 12,
7479 + PCIS_pe_m = 0x00001000,
7480 + PCIS_tae_b = 13,
7481 + PCIS_tae_m = 0x00002000,
7482 + PCIS_rle_b = 14,
7483 + PCIS_rle_m = 0x00004000,
7484 + PCIS_bme_b = 15,
7485 + PCIS_bme_m = 0x00008000,
7486 + PCIS_prd_b = 16,
7487 + PCIS_prd_m = 0x00010000,
7488 + PCIS_rip_b = 17,
7489 + PCIS_rip_m = 0x00020000,
7490 +} ;
7491 +
7492 +/*******************************************************************************
7493 + *
7494 + * PCI Status Mask Register
7495 + *
7496 + ******************************************************************************/
7497 +enum {
7498 + PCISM_eed_b = 0,
7499 + PCISM_eed_m = 0x00000001,
7500 + PCISM_wr_b = 1,
7501 + PCISM_wr_m = 0x00000002,
7502 + PCISM_nmi_b = 2,
7503 + PCISM_nmi_m = 0x00000004,
7504 + PCISM_ii_b = 3,
7505 + PCISM_ii_m = 0x00000008,
7506 + PCISM_cwe_b = 4,
7507 + PCISM_cwe_m = 0x00000010,
7508 + PCISM_cre_b = 5,
7509 + PCISM_cre_m = 0x00000020,
7510 + PCISM_mdpe_b = 6,
7511 + PCISM_mdpe_m = 0x00000040,
7512 + PCISM_sta_b = 7,
7513 + PCISM_sta_m = 0x00000080,
7514 + PCISM_rta_b = 8,
7515 + PCISM_rta_m = 0x00000100,
7516 + PCISM_rma_b = 9,
7517 + PCISM_rma_m = 0x00000200,
7518 + PCISM_sse_b = 10,
7519 + PCISM_sse_m = 0x00000400,
7520 + PCISM_ose_b = 11,
7521 + PCISM_ose_m = 0x00000800,
7522 + PCISM_pe_b = 12,
7523 + PCISM_pe_m = 0x00001000,
7524 + PCISM_tae_b = 13,
7525 + PCISM_tae_m = 0x00002000,
7526 + PCISM_rle_b = 14,
7527 + PCISM_rle_m = 0x00004000,
7528 + PCISM_bme_b = 15,
7529 + PCISM_bme_m = 0x00008000,
7530 + PCISM_prd_b = 16,
7531 + PCISM_prd_m = 0x00010000,
7532 + PCISM_rip_b = 17,
7533 + PCISM_rip_m = 0x00020000,
7534 +} ;
7535 +
7536 +/*******************************************************************************
7537 + *
7538 + * PCI Configuration Address Register
7539 + *
7540 + ******************************************************************************/
7541 +enum {
7542 + PCICFGA_reg_b = 2,
7543 + PCICFGA_reg_m = 0x000000fc,
7544 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
7545 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
7546 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
7547 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
7548 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
7549 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
7550 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
7551 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
7552 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7553 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
7554 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
7555 + PCICFGA_reg_pba0m_v = 0x48>>2,
7556 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
7557 + PCICFGA_reg_pba1m_v = 0x50>>2,
7558 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
7559 + PCICFGA_reg_pba2m_v = 0x58>>2,
7560 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
7561 + PCICFGA_reg_pba3m_v = 0x60>>2,
7562 + PCICFGA_reg_pmgt_v = 0x64>>2,
7563 + PCICFGA_func_b = 8,
7564 + PCICFGA_func_m = 0x00000700,
7565 + PCICFGA_dev_b = 11,
7566 + PCICFGA_dev_m = 0x0000f800,
7567 + PCICFGA_dev_internal_v = 0,
7568 + PCICFGA_bus_b = 16,
7569 + PCICFGA_bus_m = 0x00ff0000,
7570 + PCICFGA_bus_type0_v = 0, //local bus
7571 + PCICFGA_en_b = 31, // read only
7572 + PCICFGA_en_m = 0x80000000,
7573 +} ;
7574 +
7575 +enum {
7576 + PCFGID_vendor_b = 0,
7577 + PCFGID_vendor_m = 0x0000ffff,
7578 + PCFGID_vendor_IDT_v = 0x111d,
7579 + PCFGID_device_b = 16,
7580 + PCFGID_device_m = 0xffff0000,
7581 + PCFGID_device_Korinade_v = 0x0214,
7582 +
7583 + PCFG04_command_ioena_b = 1,
7584 + PCFG04_command_ioena_m = 0x00000001,
7585 + PCFG04_command_memena_b = 2,
7586 + PCFG04_command_memena_m = 0x00000002,
7587 + PCFG04_command_bmena_b = 3,
7588 + PCFG04_command_bmena_m = 0x00000004,
7589 + PCFG04_command_mwinv_b = 5,
7590 + PCFG04_command_mwinv_m = 0x00000010,
7591 + PCFG04_command_parena_b = 7,
7592 + PCFG04_command_parena_m = 0x00000040,
7593 + PCFG04_command_serrena_b = 9,
7594 + PCFG04_command_serrena_m = 0x00000100,
7595 + PCFG04_command_fastbbena_b = 10,
7596 + PCFG04_command_fastbbena_m = 0x00000200,
7597 + PCFG04_status_b = 16,
7598 + PCFG04_status_m = 0xffff0000,
7599 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
7600 + PCFG04_status_66MHz_m = 0x00200000,
7601 + PCFG04_status_fbb_b = 23,
7602 + PCFG04_status_fbb_m = 0x00800000,
7603 + PCFG04_status_mdpe_b = 24,
7604 + PCFG04_status_mdpe_m = 0x01000000,
7605 + PCFG04_status_dst_b = 25,
7606 + PCFG04_status_dst_m = 0x06000000,
7607 + PCFG04_status_sta_b = 27,
7608 + PCFG04_status_sta_m = 0x08000000,
7609 + PCFG04_status_rta_b = 28,
7610 + PCFG04_status_rta_m = 0x10000000,
7611 + PCFG04_status_rma_b = 29,
7612 + PCFG04_status_rma_m = 0x20000000,
7613 + PCFG04_status_sse_b = 30,
7614 + PCFG04_status_sse_m = 0x40000000,
7615 + PCFG04_status_pe_b = 31,
7616 + PCFG04_status_pe_m = 0x40000000,
7617 +
7618 + PCFG08_revId_b = 0,
7619 + PCFG08_revId_m = 0x000000ff,
7620 + PCFG08_classCode_b = 0,
7621 + PCFG08_classCode_m = 0xffffff00,
7622 + PCFG08_classCode_bridge_v = 06,
7623 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
7624 + PCFG0C_cacheline_b = 0,
7625 + PCFG0C_cacheline_m = 0x000000ff,
7626 + PCFG0C_masterLatency_b = 8,
7627 + PCFG0C_masterLatency_m = 0x0000ff00,
7628 + PCFG0C_headerType_b = 16,
7629 + PCFG0C_headerType_m = 0x00ff0000,
7630 + PCFG0C_bist_b = 24,
7631 + PCFG0C_bist_m = 0xff000000,
7632 +
7633 + PCIPBA_msi_b = 0,
7634 + PCIPBA_msi_m = 0x00000001,
7635 + PCIPBA_p_b = 3,
7636 + PCIPBA_p_m = 0x00000004,
7637 + PCIPBA_baddr_b = 8,
7638 + PCIPBA_baddr_m = 0xffffff00,
7639 +
7640 + PCFGSS_vendorId_b = 0,
7641 + PCFGSS_vendorId_m = 0x0000ffff,
7642 + PCFGSS_id_b = 16,
7643 + PCFGSS_id_m = 0xffff0000,
7644 +
7645 + PCFG3C_interruptLine_b = 0,
7646 + PCFG3C_interruptLine_m = 0x000000ff,
7647 + PCFG3C_interruptPin_b = 8,
7648 + PCFG3C_interruptPin_m = 0x0000ff00,
7649 + PCFG3C_minGrant_b = 16,
7650 + PCFG3C_minGrant_m = 0x00ff0000,
7651 + PCFG3C_maxLat_b = 24,
7652 + PCFG3C_maxLat_m = 0xff000000,
7653 +
7654 + PCIPBAC_msi_b = 0,
7655 + PCIPBAC_msi_m = 0x00000001,
7656 + PCIPBAC_p_b = 1,
7657 + PCIPBAC_p_m = 0x00000002,
7658 + PCIPBAC_size_b = 2,
7659 + PCIPBAC_size_m = 0x0000007c,
7660 + PCIPBAC_sb_b = 7,
7661 + PCIPBAC_sb_m = 0x00000080,
7662 + PCIPBAC_pp_b = 8,
7663 + PCIPBAC_pp_m = 0x00000100,
7664 + PCIPBAC_mr_b = 9,
7665 + PCIPBAC_mr_m = 0x00000600,
7666 + PCIPBAC_mr_read_v =0, //no prefetching
7667 + PCIPBAC_mr_readLine_v =1,
7668 + PCIPBAC_mr_readMult_v =2,
7669 + PCIPBAC_mrl_b = 11,
7670 + PCIPBAC_mrl_m = 0x00000800,
7671 + PCIPBAC_mrm_b = 12,
7672 + PCIPBAC_mrm_m = 0x00001000,
7673 + PCIPBAC_trp_b = 13,
7674 + PCIPBAC_trp_m = 0x00002000,
7675 +
7676 + PCFG40_trdyTimeout_b = 0,
7677 + PCFG40_trdyTimeout_m = 0x000000ff,
7678 + PCFG40_retryLim_b = 8,
7679 + PCFG40_retryLim_m = 0x0000ff00,
7680 +};
7681 +
7682 +/*******************************************************************************
7683 + *
7684 + * PCI Local Base Address [0|1|2|3] Register
7685 + *
7686 + ******************************************************************************/
7687 +enum {
7688 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
7689 + PCILBA_baddr_m = 0xffffff00,
7690 +} ;
7691 +/*******************************************************************************
7692 + *
7693 + * PCI Local Base Address Control Register
7694 + *
7695 + ******************************************************************************/
7696 +enum {
7697 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
7698 + PCILBAC_msi_m = 0x00000001,
7699 + PCILBAC_msi_mem_v = 0,
7700 + PCILBAC_msi_io_v = 1,
7701 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
7702 + PCILBAC_size_m = 0x0000007c,
7703 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
7704 + PCILBAC_sb_m = 0x00000080,
7705 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
7706 + PCILBAC_rt_m = 0x00000100,
7707 + PCILBAC_rt_noprefetch_v = 0, // mem read
7708 + PCILBAC_rt_prefetch_v = 1, // mem readline
7709 +} ;
7710 +
7711 +/*******************************************************************************
7712 + *
7713 + * PCI Local Base Address [0|1|2|3] Mapping Register
7714 + *
7715 + ******************************************************************************/
7716 +enum {
7717 + PCILBAM_maddr_b = 8,
7718 + PCILBAM_maddr_m = 0xffffff00,
7719 +} ;
7720 +
7721 +/*******************************************************************************
7722 + *
7723 + * PCI Decoupled Access Control Register
7724 + *
7725 + ******************************************************************************/
7726 +enum {
7727 + PCIDAC_den_b = 0,
7728 + PCIDAC_den_m = 0x00000001,
7729 +} ;
7730 +
7731 +/*******************************************************************************
7732 + *
7733 + * PCI Decoupled Access Status Register
7734 + *
7735 + ******************************************************************************/
7736 +enum {
7737 + PCIDAS_d_b = 0,
7738 + PCIDAS_d_m = 0x00000001,
7739 + PCIDAS_b_b = 1,
7740 + PCIDAS_b_m = 0x00000002,
7741 + PCIDAS_e_b = 2,
7742 + PCIDAS_e_m = 0x00000004,
7743 + PCIDAS_ofe_b = 3,
7744 + PCIDAS_ofe_m = 0x00000008,
7745 + PCIDAS_off_b = 4,
7746 + PCIDAS_off_m = 0x00000010,
7747 + PCIDAS_ife_b = 5,
7748 + PCIDAS_ife_m = 0x00000020,
7749 + PCIDAS_iff_b = 6,
7750 + PCIDAS_iff_m = 0x00000040,
7751 +} ;
7752 +
7753 +/*******************************************************************************
7754 + *
7755 + * PCI DMA Channel 8 Configuration Register
7756 + *
7757 + ******************************************************************************/
7758 +enum
7759 +{
7760 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
7761 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
7762 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
7763 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
7764 +} ;
7765 +
7766 +/*******************************************************************************
7767 + *
7768 + * PCI DMA Channel 9 Configuration Register
7769 + *
7770 + ******************************************************************************/
7771 +enum
7772 +{
7773 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
7774 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
7775 +} ;
7776 +
7777 +/*******************************************************************************
7778 + *
7779 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7780 + *
7781 + ******************************************************************************/
7782 +enum {
7783 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
7784 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
7785 + // These are for reads (DMA channel 8)
7786 + PCIDMAD_devcmd_mr_v = 0, //memory read
7787 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
7788 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
7789 + PCIDMAD_devcmd_ior_v = 3, //I/O read
7790 + // These are for writes (DMA channel 9)
7791 + PCIDMAD_devcmd_mw_v = 0, //memory write
7792 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
7793 + PCIDMAD_devcmd_iow_v = 3, //I/O write
7794 +
7795 + // Swap byte field applies to both DMA channel 8 and 9
7796 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
7797 + PCIDMAD_sb_m = 0x01000000, // swap byte field
7798 +} ;
7799 +
7800 +
7801 +/*******************************************************************************
7802 + *
7803 + * PCI Target Control Register
7804 + *
7805 + ******************************************************************************/
7806 +enum
7807 +{
7808 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
7809 + PCITC_rtimer_m = 0x000000ff,
7810 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
7811 + PCITC_dtimer_m = 0x0000ff00,
7812 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
7813 + PCITC_rdr_m = 0x00040000,
7814 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
7815 + PCITC_ddt_m = 0x00080000,
7816 +} ;
7817 +/*******************************************************************************
7818 + *
7819 + * PCI messaging unit [applies to both inbound and outbound registers ]
7820 + *
7821 + ******************************************************************************/
7822 +enum
7823 +{
7824 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7825 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
7826 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7827 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
7828 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7829 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
7830 +};
7831 +
7832 +
7833 +
7834 +
7835 +
7836 +
7837 +#define PCI_MSG_VirtualAddress 0xB8088010
7838 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7839 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7840 +
7841 +#define PCIM_SHFT 0x6
7842 +#define PCIM_BIT_LEN 0x7
7843 +#define PCIM_H_EA 0x3
7844 +#define PCIM_H_IA_FIX 0x4
7845 +#define PCIM_H_IA_RR 0x5
7846 +#if 0
7847 +#define PCI_ADDR_START 0x13000000
7848 +#endif
7849 +
7850 +#define PCI_ADDR_START 0x50000000
7851 +
7852 +#define CPUTOPCI_MEM_WIN 0x02000000
7853 +#define CPUTOPCI_IO_WIN 0x00100000
7854 +#define PCILBA_SIZE_SHFT 2
7855 +#define PCILBA_SIZE_MASK 0x1F
7856 +#define SIZE_256MB 0x1C
7857 +#define SIZE_128MB 0x1B
7858 +#define SIZE_64MB 0x1A
7859 +#define SIZE_32MB 0x19
7860 +#define SIZE_16MB 0x18
7861 +#define SIZE_4MB 0x16
7862 +#define SIZE_2MB 0x15
7863 +#define SIZE_1MB 0x14
7864 +#define KORINA_CONFIG0_ADDR 0x80000000
7865 +#define KORINA_CONFIG1_ADDR 0x80000004
7866 +#define KORINA_CONFIG2_ADDR 0x80000008
7867 +#define KORINA_CONFIG3_ADDR 0x8000000C
7868 +#define KORINA_CONFIG4_ADDR 0x80000010
7869 +#define KORINA_CONFIG5_ADDR 0x80000014
7870 +#define KORINA_CONFIG6_ADDR 0x80000018
7871 +#define KORINA_CONFIG7_ADDR 0x8000001C
7872 +#define KORINA_CONFIG8_ADDR 0x80000020
7873 +#define KORINA_CONFIG9_ADDR 0x80000024
7874 +#define KORINA_CONFIG10_ADDR 0x80000028
7875 +#define KORINA_CONFIG11_ADDR 0x8000002C
7876 +#define KORINA_CONFIG12_ADDR 0x80000030
7877 +#define KORINA_CONFIG13_ADDR 0x80000034
7878 +#define KORINA_CONFIG14_ADDR 0x80000038
7879 +#define KORINA_CONFIG15_ADDR 0x8000003C
7880 +#define KORINA_CONFIG16_ADDR 0x80000040
7881 +#define KORINA_CONFIG17_ADDR 0x80000044
7882 +#define KORINA_CONFIG18_ADDR 0x80000048
7883 +#define KORINA_CONFIG19_ADDR 0x8000004C
7884 +#define KORINA_CONFIG20_ADDR 0x80000050
7885 +#define KORINA_CONFIG21_ADDR 0x80000054
7886 +#define KORINA_CONFIG22_ADDR 0x80000058
7887 +#define KORINA_CONFIG23_ADDR 0x8000005C
7888 +#define KORINA_CONFIG24_ADDR 0x80000060
7889 +#define KORINA_CONFIG25_ADDR 0x80000064
7890 +#define KORINA_CMD (PCFG04_command_ioena_m | \
7891 + PCFG04_command_memena_m | \
7892 + PCFG04_command_bmena_m | \
7893 + PCFG04_command_mwinv_m | \
7894 + PCFG04_command_parena_m | \
7895 + PCFG04_command_serrena_m )
7896 +
7897 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
7898 + PCFG04_status_sta_m | \
7899 + PCFG04_status_rta_m | \
7900 + PCFG04_status_rma_m | \
7901 + PCFG04_status_sse_m | \
7902 + PCFG04_status_pe_m)
7903 +
7904 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
7905 +
7906 +#define KORINA_REVID 0
7907 +#define KORINA_CLASS_CODE 0
7908 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
7909 + KORINA_REVID)
7910 +
7911 +#define KORINA_CACHE_LINE_SIZE 4
7912 +#define KORINA_MASTER_LAT 0x3c
7913 +#define KORINA_HEADER_TYPE 0
7914 +#define KORINA_BIST 0
7915 +
7916 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7917 + (KORINA_HEADER_TYPE<<16) | \
7918 + (KORINA_MASTER_LAT<<8) | \
7919 + KORINA_CACHE_LINE_SIZE )
7920 +
7921 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
7922 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
7923 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
7924 + internal Registers */
7925 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
7926 +
7927 +#define KORINA_CNFG4 KORINA_BAR0
7928 +#define KORINA_CNFG5 KORINA_BAR1
7929 +#define KORINA_CNFG6 KORINA_BAR2
7930 +#define KORINA_CNFG7 KORINA_BAR3
7931 +
7932 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7933 +#define KORINA_SUBSYSTEM_ID 0x0214
7934 +#define KORINA_CNFG8 0
7935 +#define KORINA_CNFG9 0
7936 +#define KORINA_CNFG10 0
7937 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7938 + KORINA_SUBSYSTEM_ID)
7939 +#define KORINA_INT_LINE 1
7940 +#define KORINA_INT_PIN 1
7941 +#define KORINA_MIN_GNT 8
7942 +#define KORINA_MAX_LAT 0x38
7943 +#define KORINA_CNFG12 0
7944 +#define KORINA_CNFG13 0
7945 +#define KORINA_CNFG14 0
7946 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
7947 + (KORINA_MIN_GNT<<16) | \
7948 + (KORINA_INT_PIN<<8) | \
7949 + KORINA_INT_LINE)
7950 +#define KORINA_RETRY_LIMIT 0x80
7951 +#define KORINA_TRDY_LIMIT 0x80
7952 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7953 + KORINA_TRDY_LIMIT)
7954 +#define PCI_PBAxC_R 0x0
7955 +#define PCI_PBAxC_RL 0x1
7956 +#define PCI_PBAxC_RM 0x2
7957 +#define SIZE_SHFT 2
7958 +
7959 +#if defined(__MIPSEB__)
7960 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7961 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7962 + PCIPBAC_pp_m | \
7963 + (SIZE_128MB<<SIZE_SHFT) | \
7964 + PCIPBAC_p_m)
7965 +#else
7966 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
7967 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7968 + PCIPBAC_pp_m | \
7969 + (SIZE_128MB<<SIZE_SHFT) | \
7970 + PCIPBAC_p_m)
7971 +#endif
7972 +#define KORINA_CNFG17 KORINA_PBA0C
7973 +#define KORINA_PBA0M 0x0
7974 +#define KORINA_CNFG18 KORINA_PBA0M
7975 +
7976 +#if defined(__MIPSEB__)
7977 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7978 + PCIPBAC_msi_m)
7979 +#else
7980 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
7981 + PCIPBAC_msi_m)
7982 +#endif
7983 +#define KORINA_CNFG19 KORINA_PBA1C
7984 +#define KORINA_PBA1M 0x0
7985 +#define KORINA_CNFG20 KORINA_PBA1M
7986 +
7987 +#if defined(__MIPSEB__)
7988 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7989 + PCIPBAC_msi_m)
7990 +#else
7991 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
7992 + PCIPBAC_msi_m)
7993 +#endif
7994 +#define KORINA_CNFG21 KORINA_PBA2C
7995 +#define KORINA_PBA2M 0x18000000
7996 +#define KORINA_CNFG22 KORINA_PBA2M
7997 +#define KORINA_PBA3C 0
7998 +#define KORINA_CNFG23 KORINA_PBA3C
7999 +#define KORINA_PBA3M 0
8000 +#define KORINA_CNFG24 KORINA_PBA3M
8001 +
8002 +
8003 +
8004 +#define PCITC_DTIMER_VAL 8
8005 +#define PCITC_RTIMER_VAL 0x10
8006 +
8007 +
8008 +
8009 +
8010 +#endif // __IDT_PCI_H__
8011 +
8012 +
8013 +
8014 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
8015 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
8016 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-06-18 12:44:28.000000000 +0200
8017 @@ -0,0 +1,119 @@
8018 +/**************************************************************************
8019 + *
8020 + * BRIEF MODULE DESCRIPTION
8021 + * Reset register definitions.
8022 + *
8023 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8024 + *
8025 + * This program is free software; you can redistribute it and/or modify it
8026 + * under the terms of the GNU General Public License as published by the
8027 + * Free Software Foundation; either version 2 of the License, or (at your
8028 + * option) any later version.
8029 + *
8030 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8031 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8032 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8033 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8034 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8035 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8036 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8037 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8038 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8039 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8040 + *
8041 + * You should have received a copy of the GNU General Public License along
8042 + * with this program; if not, write to the Free Software Foundation, Inc.,
8043 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8044 + *
8045 + *
8046 + **************************************************************************
8047 + * May 2004 rkt, neb.
8048 + *
8049 + * Initial Release
8050 + *
8051 + *
8052 + *
8053 + **************************************************************************
8054 + */
8055 +
8056 +#ifndef __IDT_RST_H__
8057 +#define __IDT_RST_H__
8058 +
8059 +enum
8060 +{
8061 + RST0_PhysicalAddress = 0x18000000,
8062 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
8063 +
8064 + RST0_VirtualAddress = 0xb8000000,
8065 + RST_VirtualAddress = RST0_VirtualAddress, // Default
8066 +} ;
8067 +
8068 +typedef struct RST_s
8069 +{
8070 + u32 filler [0x0006] ;
8071 + u32 sysid ;
8072 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
8073 + u32 reset ;
8074 + u32 bcv ;
8075 + u32 cea ;
8076 +} volatile * RST_t ;
8077 +
8078 +enum
8079 +{
8080 + SYSID_rev_b = 0,
8081 + SYSID_rev_m = 0x000000ff,
8082 + SYSID_imp_b = 8,
8083 + SYSID_imp_m = 0x000fff00,
8084 + SYSID_vendor_b = 8,
8085 + SYSID_vendor_m = 0xfff00000,
8086 +
8087 + BCV_pll_b = 0,
8088 + BCV_pll_m = 0x0000000f,
8089 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
8090 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
8091 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
8092 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
8093 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
8094 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
8095 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
8096 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
8097 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
8098 + BCV_pll_Res9_v = 0x9,
8099 + BCV_pll_Res10_v = 0xa,
8100 + BCV_pll_Res11_v = 0xb,
8101 + BCV_pll_Res12_v = 0xc,
8102 + BCV_pll_Res13_v = 0xd,
8103 + BCV_pll_Res14_v = 0xe,
8104 + BCV_pll_Res15_v = 0xf,
8105 + BCV_clkDiv_b = 4,
8106 + BCV_clkDiv_m = 0x00000030,
8107 + BCV_clkDiv_Div1_v = 0x0,
8108 + BCV_clkDiv_Div2_v = 0x1,
8109 + BCV_clkDiv_Div4_v = 0x2,
8110 + BCV_clkDiv_Res3_v = 0x3,
8111 + BCV_bigEndian_b = 6,
8112 + BCV_bigEndian_m = 0x00000040,
8113 + BCV_resetFast_b = 7,
8114 + BCV_resetFast_m = 0x00000080,
8115 + BCV_pciMode_b = 8,
8116 + BCV_pciMode_m = 0x00000700,
8117 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
8118 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
8119 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
8120 + BCV_pciMode_external_v = 3, // host, external arbiter.
8121 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
8122 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
8123 + BCV_pciMode_res6_v = 6,
8124 + BCV_pciMode_res7_v = 7,
8125 + BCV_watchDisable_b = 11,
8126 + BCV_watchDisable_m = 0x00000800,
8127 + BCV_res12_b = 12,
8128 + BCV_res12_m = 0x00001000,
8129 + BCV_res13_b = 13,
8130 + BCV_res13_m = 0x00002000,
8131 + BCV_res14_b = 14,
8132 + BCV_res14_m = 0x00004000,
8133 + BCV_res15_b = 15,
8134 + BCV_res15_m = 0x00008000,
8135 +} ;
8136 +#endif // __IDT_RST_H__
8137 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8138 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
8139 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-06-18 12:44:28.000000000 +0200
8140 @@ -0,0 +1,120 @@
8141 +/**************************************************************************
8142 + *
8143 + * BRIEF MODULE DESCRIPTION
8144 + * Serial Peripheral Interface register definitions.
8145 + *
8146 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8147 + *
8148 + * This program is free software; you can redistribute it and/or modify it
8149 + * under the terms of the GNU General Public License as published by the
8150 + * Free Software Foundation; either version 2 of the License, or (at your
8151 + * option) any later version.
8152 + *
8153 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8154 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8155 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8156 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8157 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8158 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8159 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8160 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8161 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8162 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8163 + *
8164 + * You should have received a copy of the GNU General Public License along
8165 + * with this program; if not, write to the Free Software Foundation, Inc.,
8166 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8167 + *
8168 + *
8169 + **************************************************************************
8170 + * May 2004 rkt, neb.
8171 + *
8172 + * Initial Release
8173 + *
8174 + *
8175 + *
8176 + **************************************************************************
8177 + */
8178 +
8179 +#ifndef __IDT_SPI_H__
8180 +#define __IDT_SPI_H__
8181 +
8182 +enum
8183 +{
8184 + SPI0_PhysicalAddress = 0x18070000,
8185 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
8186 +
8187 + SPI0_VirtualAddress = 0xB8070000,
8188 + SPI_VirtualAddress = SPI0_VirtualAddress,
8189 +} ;
8190 +
8191 +typedef struct
8192 +{
8193 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8194 + u32 spc ; // spi control reg use SPC_
8195 + u32 sps ; // spi status reg use SPS_
8196 + u32 spd ; // spi data reg use SPD_
8197 + u32 siofunc ; // serial IO function use SIOFUNC_
8198 + u32 siocfg ; // serial IO config use SIOCFG_
8199 + u32 siod; // serial IO data use SIOD_
8200 +} volatile *SPI_t ;
8201 +
8202 +enum
8203 +{
8204 + SPCP_div_b = 0,
8205 + SPCP_div_m = 0x000000ff,
8206 + SPC_spr_b = 0,
8207 + SPC_spr_m = 0x00000003,
8208 + SPC_spr_div2_v = 0,
8209 + SPC_spr_div4_v = 1,
8210 + SPC_spr_div16_v = 2,
8211 + SPC_spr_div32_v = 3,
8212 + SPC_cpha_b = 2,
8213 + SPC_cpha_m = 0x00000004,
8214 + SPC_cpol_b = 3,
8215 + SPC_cpol_m = 0x00000008,
8216 + SPC_mstr_b = 4,
8217 + SPC_mstr_m = 0x00000010,
8218 + SPC_spe_b = 6,
8219 + SPC_spe_m = 0x00000040,
8220 + SPC_spie_b = 7,
8221 + SPC_spie_m = 0x00000080,
8222 +
8223 + SPS_modf_b = 4,
8224 + SPS_modf_m = 0x00000010,
8225 + SPS_wcol_b = 6,
8226 + SPS_wcol_m = 0x00000040,
8227 + SPS_spif_b = 7,
8228 + SPS_spif_m = 0x00000070,
8229 +
8230 + SPD_data_b = 0,
8231 + SPD_data_m = 0x000000ff,
8232 +
8233 + SIOFUNC_sdo_b = 0,
8234 + SIOFUNC_sdo_m = 0x00000001,
8235 + SIOFUNC_sdi_b = 1,
8236 + SIOFUNC_sdi_m = 0x00000002,
8237 + SIOFUNC_sck_b = 2,
8238 + SIOFUNC_sck_m = 0x00000004,
8239 + SIOFUNC_pci_b = 3,
8240 + SIOFUNC_pci_m = 0x00000008,
8241 +
8242 + SIOCFG_sdo_b = 0,
8243 + SIOCFG_sdo_m = 0x00000001,
8244 + SIOCFG_sdi_b = 1,
8245 + SIOCFG_sdi_m = 0x00000002,
8246 + SIOCFG_sck_b = 2,
8247 + SIOCFG_sck_m = 0x00000004,
8248 + SIOCFG_pci_b = 3,
8249 + SIOCFG_pci_m = 0x00000008,
8250 +
8251 + SIOD_sdo_b = 0,
8252 + SIOD_sdo_m = 0x00000001,
8253 + SIOD_sdi_b = 1,
8254 + SIOD_sdi_m = 0x00000002,
8255 + SIOD_sck_b = 2,
8256 + SIOD_sck_m = 0x00000004,
8257 + SIOD_pci_b = 3,
8258 + SIOD_pci_m = 0x00000008,
8259 +} ;
8260 +#endif // __IDT_SPI_H__
8261 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8262 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
8263 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-06-18 12:44:28.000000000 +0200
8264 @@ -0,0 +1,91 @@
8265 +/**************************************************************************
8266 + *
8267 + * BRIEF MODULE DESCRIPTION
8268 + * Definitions for timer registers
8269 + *
8270 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8271 + *
8272 + * This program is free software; you can redistribute it and/or modify it
8273 + * under the terms of the GNU General Public License as published by the
8274 + * Free Software Foundation; either version 2 of the License, or (at your
8275 + * option) any later version.
8276 + *
8277 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8278 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8279 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8280 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8281 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8282 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8283 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8284 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8285 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8286 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8287 + *
8288 + * You should have received a copy of the GNU General Public License along
8289 + * with this program; if not, write to the Free Software Foundation, Inc.,
8290 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8291 + *
8292 + *
8293 + **************************************************************************
8294 + * May 2004 rkt,neb.
8295 + *
8296 + * Initial Release
8297 + *
8298 + *
8299 + *
8300 + **************************************************************************
8301 + */
8302 +
8303 +#ifndef __IDT_TIM_H__
8304 +#define __IDT_TIM_H__
8305 +
8306 +enum
8307 +{
8308 + TIM0_PhysicalAddress = 0x18028000,
8309 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
8310 +
8311 + TIM0_VirtualAddress = 0xb8028000,
8312 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
8313 +} ;
8314 +
8315 +enum
8316 +{
8317 + TIM_Count = 3,
8318 +} ;
8319 +
8320 +struct TIM_CNTR_s
8321 +{
8322 + u32 count ;
8323 + u32 compare ;
8324 + u32 ctc ; //use CTC_
8325 +} ;
8326 +
8327 +typedef struct TIM_s
8328 +{
8329 + struct TIM_CNTR_s tim [TIM_Count] ;
8330 + u32 rcount ; //use RCOUNT_
8331 + u32 rcompare ; //use RCOMPARE_
8332 + u32 rtc ; //use RTC_
8333 +} volatile * TIM_t ;
8334 +
8335 +enum
8336 +{
8337 + CTC_en_b = 0,
8338 + CTC_en_m = 0x00000001,
8339 + CTC_to_b = 1,
8340 + CTC_to_m = 0x00000002,
8341 +
8342 + RCOUNT_count_b = 0,
8343 + RCOUNT_count_m = 0x0000ffff,
8344 + RCOMPARE_compare_b = 0,
8345 + RCOMPARE_compare_m = 0x0000ffff,
8346 + RTC_ce_b = 0,
8347 + RTC_ce_m = 0x00000001,
8348 + RTC_to_b = 1,
8349 + RTC_to_m = 0x00000002,
8350 + RTC_rqe_b = 2,
8351 + RTC_rqe_m = 0x00000004,
8352 +
8353 +} ;
8354 +#endif // __IDT_TIM_H__
8355 +
8356 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8357 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
8358 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-06-18 12:44:28.000000000 +0200
8359 @@ -0,0 +1,189 @@
8360 +/**************************************************************************
8361 + *
8362 + * BRIEF MODULE DESCRIPTION
8363 + * UART register definitions
8364 + *
8365 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8366 + *
8367 + * This program is free software; you can redistribute it and/or modify it
8368 + * under the terms of the GNU General Public License as published by the
8369 + * Free Software Foundation; either version 2 of the License, or (at your
8370 + * option) any later version.
8371 + *
8372 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8373 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8374 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8375 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8376 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8377 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8378 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8379 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8380 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8381 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8382 + *
8383 + * You should have received a copy of the GNU General Public License along
8384 + * with this program; if not, write to the Free Software Foundation, Inc.,
8385 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8386 + *
8387 + *
8388 + **************************************************************************
8389 + * May 2004 rkt, neb.
8390 + *
8391 + * Initial Release
8392 + *
8393 + *
8394 + *
8395 + **************************************************************************
8396 + */
8397 +
8398 +#ifndef __IDT_UART_H__
8399 +#define __IDT_UART_H__
8400 +
8401 +enum
8402 +{
8403 + UART0_PhysicalAddress = 0x1c000000,
8404 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
8405 +
8406 + UART0_VirtualAddress = 0xbc000000,
8407 + UART_VirtualAddress = UART0_VirtualAddress, // Default
8408 +} ;
8409 +
8410 +/*
8411 + * Register definitions are in bytes so we can handle endian problems.
8412 + */
8413 +
8414 +typedef struct UART_s
8415 +{
8416 + union
8417 + {
8418 + u32 const uartrb ; // 0x00 - DLAB=0, read.
8419 + u32 uartth ; // 0x00 - DLAB=0, write.
8420 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
8421 + } ;
8422 +
8423 + union
8424 + {
8425 + u32 uartie ; // 0x04 - DLAB=0, read/write.
8426 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
8427 + } ;
8428 + union
8429 + {
8430 + u32 const uartii ; // 0x08 - DLAB=0, read.
8431 + u32 uartfc ; // 0x08 - DLAB=0, write.
8432 + } ;
8433 +
8434 + u32 uartlc ; // 0x0c
8435 + u32 uartmc ; // 0x10
8436 + u32 uartls ; // 0x14
8437 + u32 uartms ; // 0x18
8438 + u32 uarts ; // 0x1c
8439 +} volatile *UART_t ;
8440 +
8441 +// Reset registers.
8442 +typedef u32 volatile *UARTRR_t ;
8443 +
8444 +enum
8445 +{
8446 + UARTIE_rda_b = 0,
8447 + UARTIE_rda_m = 0x00000001,
8448 + UARTIE_the_b = 1,
8449 + UARTIE_the_m = 0x00000002,
8450 + UARTIE_rls_b = 2,
8451 + UARTIE_rls_m = 0x00000004,
8452 + UARTIE_ems_b = 3,
8453 + UARTIE_ems_m = 0x00000008,
8454 +
8455 + UARTII_pi_b = 0,
8456 + UARTII_pi_m = 0x00000001,
8457 + UARTII_iid_b = 1,
8458 + UARTII_iid_m = 0x0000000e,
8459 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
8460 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
8461 + UARTII_iid_rda_v = 2, // Receive data available
8462 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
8463 + UARTII_iid_res4_v = 4, // reserved.
8464 + UARTII_iid_res5_v = 5, // reserved.
8465 + UARTII_iid_cto_v = 6, // Character timeout.
8466 + UARTII_iid_res7_v = 7, // reserved.
8467 +
8468 + UARTFC_en_b = 0,
8469 + UARTFC_en_m = 0x00000001,
8470 + UARTFC_rr_b = 1,
8471 + UARTFC_rr_m = 0x00000002,
8472 + UARTFC_tr_b = 2,
8473 + UARTFC_tr_m = 0x00000004,
8474 + UARTFC_dms_b = 3,
8475 + UARTFC_dms_m = 0x00000008,
8476 + UARTFC_rt_b = 6,
8477 + UARTFC_rt_m = 0x000000c0,
8478 + UARTFC_rt_1Byte_v = 0,
8479 + UARTFC_rt_4Byte_v = 1,
8480 + UARTFC_rt_8Byte_v = 2,
8481 + UARTFC_rt_14Byte_v = 3,
8482 +
8483 + UARTLC_wls_b = 0,
8484 + UARTLC_wls_m = 0x00000003,
8485 + UARTLC_wls_5Bits_v = 0,
8486 + UARTLC_wls_6Bits_v = 1,
8487 + UARTLC_wls_7Bits_v = 2,
8488 + UARTLC_wls_8Bits_v = 3,
8489 + UARTLC_stb_b = 2,
8490 + UARTLC_stb_m = 0x00000004,
8491 + UARTLC_pen_b = 3,
8492 + UARTLC_pen_m = 0x00000008,
8493 + UARTLC_eps_b = 4,
8494 + UARTLC_eps_m = 0x00000010,
8495 + UARTLC_sp_b = 5,
8496 + UARTLC_sp_m = 0x00000020,
8497 + UARTLC_sb_b = 6,
8498 + UARTLC_sb_m = 0x00000040,
8499 + UARTLC_dlab_b = 7,
8500 + UARTLC_dlab_m = 0x00000080,
8501 +
8502 + UARTMC_dtr_b = 0,
8503 + UARTMC_dtr_m = 0x00000001,
8504 + UARTMC_rts_b = 1,
8505 + UARTMC_rts_m = 0x00000002,
8506 + UARTMC_o1_b = 2,
8507 + UARTMC_o1_m = 0x00000004,
8508 + UARTMC_o2_b = 3,
8509 + UARTMC_o2_m = 0x00000008,
8510 + UARTMC_lp_b = 4,
8511 + UARTMC_lp_m = 0x00000010,
8512 +
8513 + UARTLS_dr_b = 0,
8514 + UARTLS_dr_m = 0x00000001,
8515 + UARTLS_oe_b = 1,
8516 + UARTLS_oe_m = 0x00000002,
8517 + UARTLS_pe_b = 2,
8518 + UARTLS_pe_m = 0x00000004,
8519 + UARTLS_fe_b = 3,
8520 + UARTLS_fe_m = 0x00000008,
8521 + UARTLS_bi_b = 4,
8522 + UARTLS_bi_m = 0x00000010,
8523 + UARTLS_thr_b = 5,
8524 + UARTLS_thr_m = 0x00000020,
8525 + UARTLS_te_b = 6,
8526 + UARTLS_te_m = 0x00000040,
8527 + UARTLS_rfe_b = 7,
8528 + UARTLS_rfe_m = 0x00000080,
8529 +
8530 + UARTMS_dcts_b = 0,
8531 + UARTMS_dcts_m = 0x00000001,
8532 + UARTMS_ddsr_b = 1,
8533 + UARTMS_ddsr_m = 0x00000002,
8534 + UARTMS_teri_b = 2,
8535 + UARTMS_teri_m = 0x00000004,
8536 + UARTMS_ddcd_b = 3,
8537 + UARTMS_ddcd_m = 0x00000008,
8538 + UARTMS_cts_b = 4,
8539 + UARTMS_cts_m = 0x00000010,
8540 + UARTMS_dsr_b = 5,
8541 + UARTMS_dsr_m = 0x00000020,
8542 + UARTMS_ri_b = 6,
8543 + UARTMS_ri_m = 0x00000040,
8544 + UARTMS_dcd_b = 7,
8545 + UARTMS_dcd_m = 0x00000080,
8546 +} ;
8547 +
8548 +#endif // __IDT_UART_H__
8549 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8550 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
8551 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-06-18 12:44:28.000000000 +0200
8552 @@ -0,0 +1,231 @@
8553 +/**************************************************************************
8554 + *
8555 + * BRIEF MODULE DESCRIPTION
8556 + * Register definitions for IDT RC32438 DMA.
8557 + *
8558 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8559 + *
8560 + * This program is free software; you can redistribute it and/or modify it
8561 + * under the terms of the GNU General Public License as published by the
8562 + * Free Software Foundation; either version 2 of the License, or (at your
8563 + * option) any later version.
8564 + *
8565 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8566 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8567 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8568 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8569 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8570 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8571 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8572 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8573 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8574 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8575 + *
8576 + * You should have received a copy of the GNU General Public License along
8577 + * with this program; if not, write to the Free Software Foundation, Inc.,
8578 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8579 + *
8580 + *
8581 + **************************************************************************
8582 + * May 2004 P. Sadik.
8583 + *
8584 + * Initial Release
8585 + *
8586 + *
8587 + *
8588 + **************************************************************************
8589 + */
8590 +#ifndef __IDT_RC32438_DMA_H__
8591 +#define __IDT_RC32438_DMA_H__
8592 +enum
8593 +{
8594 + DMA0_PhysicalAddress = 0x18040000,
8595 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
8596 +
8597 + DMA0_VirtualAddress = 0xb8040000,
8598 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
8599 +} ;
8600 +
8601 +/*
8602 + * DMA descriptor (in physical memory).
8603 + */
8604 +
8605 +typedef struct DMAD_s
8606 +{
8607 + u32 control ; // Control. use DMAD_*
8608 + u32 ca ; // Current Address.
8609 + u32 devcs ; // Device control and status.
8610 + u32 link ; // Next descriptor in chain.
8611 +} volatile *DMAD_t ;
8612 +
8613 +enum
8614 +{
8615 + DMAD_size = sizeof (struct DMAD_s),
8616 + DMAD_count_b = 0, // in DMAD_t -> control
8617 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
8618 + DMAD_ds_b = 20, // in DMAD_t -> control
8619 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
8620 + DMAD_ds_extToMem0_v = 0,
8621 + DMAD_ds_memToExt0_v = 1,
8622 + DMAD_ds_extToMem1_v = 0,
8623 + DMAD_ds_memToExt1_v = 1,
8624 + DMAD_ds_ethRcv0_v = 0,
8625 + DMAD_ds_ethXmt0_v = 0,
8626 + DMAD_ds_ethRcv1_v = 0,
8627 + DMAD_ds_ethXmt2_v = 0,
8628 + DMAD_ds_memToFifo_v = 0,
8629 + DMAD_ds_fifoToMem_v = 0,
8630 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
8631 + DMAD_ds_pciToMem_v = 0,
8632 + DMAD_ds_memToPci_v = 0,
8633 + DMAD_ds_securityInput_v = 0,
8634 + DMAD_ds_securityOutput_v = 0,
8635 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
8636 +
8637 + DMAD_devcmd_b = 22, // in DMAD_t -> control
8638 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
8639 + DMAD_devcmd_byte_v = 0, //memory-to-memory
8640 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
8641 + DMAD_devcmd_word_v = 2, //memory-to-memory
8642 + DMAD_devcmd_2words_v = 3, //memory-to-memory
8643 + DMAD_devcmd_4words_v = 4, //memory-to-memory
8644 + DMAD_devcmd_6words_v = 5, //memory-to-memory
8645 + DMAD_devcmd_8words_v = 6, //memory-to-memory
8646 + DMAD_devcmd_16words_v = 7, //memory-to-memory
8647 + DMAD_cof_b = 25, // chain on finished
8648 + DMAD_cof_m = 0x02000000, //
8649 + DMAD_cod_b = 26, // chain on done
8650 + DMAD_cod_m = 0x04000000, //
8651 + DMAD_iof_b = 27, // interrupt on finished
8652 + DMAD_iof_m = 0x08000000, //
8653 + DMAD_iod_b = 28, // interrupt on done
8654 + DMAD_iod_m = 0x10000000, //
8655 + DMAD_t_b = 29, // terminated
8656 + DMAD_t_m = 0x20000000, //
8657 + DMAD_d_b = 30, // done
8658 + DMAD_d_m = 0x40000000, //
8659 + DMAD_f_b = 31, // finished
8660 + DMAD_f_m = 0x80000000, //
8661 +} ;
8662 +
8663 +/*
8664 + * DMA register (within Internal Register Map).
8665 + */
8666 +
8667 +struct DMA_Chan_s
8668 +{
8669 + u32 dmac ; // Control.
8670 + u32 dmas ; // Status.
8671 + u32 dmasm ; // Mask.
8672 + u32 dmadptr ; // Descriptor pointer.
8673 + u32 dmandptr ; // Next descriptor pointer.
8674 +};
8675 +
8676 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8677 +
8678 +//DMA_Channels use DMACH_count instead
8679 +
8680 +enum
8681 +{
8682 + DMAC_run_b = 0, //
8683 + DMAC_run_m = 0x00000001, //
8684 + DMAC_dm_b = 1, // done mask
8685 + DMAC_dm_m = 0x00000002, //
8686 + DMAC_mode_b = 2, //
8687 + DMAC_mode_m = 0x0000000c, //
8688 + DMAC_mode_auto_v = 0,
8689 + DMAC_mode_burst_v = 1,
8690 + DMAC_mode_transfer_v = 2, //usually used
8691 + DMAC_mode_reserved_v = 3,
8692 + DMAC_a_b = 4, //
8693 + DMAC_a_m = 0x00000010, //
8694 +
8695 + DMAS_f_b = 0, // finished (sticky)
8696 + DMAS_f_m = 0x00000001, //
8697 + DMAS_d_b = 1, // done (sticky)
8698 + DMAS_d_m = 0x00000002, //
8699 + DMAS_c_b = 2, // chain (sticky)
8700 + DMAS_c_m = 0x00000004, //
8701 + DMAS_e_b = 3, // error (sticky)
8702 + DMAS_e_m = 0x00000008, //
8703 + DMAS_h_b = 4, // halt (sticky)
8704 + DMAS_h_m = 0x00000010, //
8705 +
8706 + DMASM_f_b = 0, // finished (1=mask)
8707 + DMASM_f_m = 0x00000001, //
8708 + DMASM_d_b = 1, // done (1=mask)
8709 + DMASM_d_m = 0x00000002, //
8710 + DMASM_c_b = 2, // chain (1=mask)
8711 + DMASM_c_m = 0x00000004, //
8712 + DMASM_e_b = 3, // error (1=mask)
8713 + DMASM_e_m = 0x00000008, //
8714 + DMASM_h_b = 4, // halt (1=mask)
8715 + DMASM_h_m = 0x00000010, //
8716 +} ;
8717 +
8718 +/*
8719 + * DMA channel definitions
8720 + */
8721 +
8722 +enum
8723 +{
8724 + DMACH_extToMem0 = 0,
8725 + DMACH_memToExt0 = 0,
8726 + DMACH_extToMem1 = 1,
8727 + DMACH_memToExt1 = 1,
8728 + DMACH_ethRcv0 = 2,
8729 + DMACH_ethXmt0 = 3,
8730 + DMACH_ethRcv1 = 4,
8731 + DMACH_ethXmt2 = 5,
8732 + DMACH_memToFifo = 6,
8733 + DMACH_fifoToMem = 7,
8734 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8735 + DMACH_pciToMem = 8,
8736 + DMACH_memToPci = 9,
8737 + DMACH_securityInput = 10,
8738 + DMACH_securityOutput = 11,
8739 + DMACH_rng_se = 12, //randomNumberGenerator on SE
8740 +
8741 + DMACH_count //must be last
8742 +};
8743 +
8744 +
8745 +typedef struct DMAC_s
8746 +{
8747 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8748 +} volatile *DMA_t ;
8749 +
8750 +
8751 +/*
8752 + * External DMA parameters
8753 +*/
8754 +
8755 +enum
8756 +{
8757 + DMADEVCMD_ts_b = 0, // ts field in devcmd
8758 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
8759 + DMADEVCMD_ts_byte_v = 0,
8760 + DMADEVCMD_ts_halfword_v = 1,
8761 + DMADEVCMD_ts_word_v = 2,
8762 + DMADEVCMD_ts_2word_v = 3,
8763 + DMADEVCMD_ts_4word_v = 4,
8764 + DMADEVCMD_ts_6word_v = 5,
8765 + DMADEVCMD_ts_8word_v = 6,
8766 + DMADEVCMD_ts_16word_v = 7
8767 +};
8768 +
8769 +
8770 +#if 1 // aws - Compatibility.
8771 +# define EXTDMA_ts_b DMADEVCMD_ts_b
8772 +# define EXTDMA_ts_m DMADEVCMD_ts_m
8773 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
8774 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
8775 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
8776 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
8777 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
8778 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
8779 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
8780 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
8781 +#endif // aws - Compatibility.
8782 +
8783 +#endif //__IDT_RC32438_DMA_H__
8784 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8785 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
8786 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-06-18 12:44:28.000000000 +0200
8787 @@ -0,0 +1,82 @@
8788 +/**************************************************************************
8789 + *
8790 + * BRIEF MODULE DESCRIPTION
8791 + * DMA operations for IDT RC32438.
8792 + *
8793 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8794 + *
8795 + * This program is free software; you can redistribute it and/or modify it
8796 + * under the terms of the GNU General Public License as published by the
8797 + * Free Software Foundation; either version 2 of the License, or (at your
8798 + * option) any later version.
8799 + *
8800 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8801 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8802 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8803 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8804 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8805 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8806 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8807 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8808 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8809 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8810 + *
8811 + * You should have received a copy of the GNU General Public License along
8812 + * with this program; if not, write to the Free Software Foundation, Inc.,
8813 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8814 + *
8815 + *
8816 + **************************************************************************
8817 + * May 2004 P. Sadik.
8818 + *
8819 + * Initial Release
8820 + *
8821 + *
8822 + *
8823 + **************************************************************************
8824 + */
8825 +
8826 +#ifndef __IDT_RC32438_DMA_V_H__
8827 +#define __IDT_RC32438_DMA_V_H__
8828 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
8829 +
8830 +#define DMA_CHAN_OFFSET 0x14
8831 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8832 +#define DMA_COUNT(count) \
8833 + ((count) & DMAD_count_m)
8834 +
8835 +#define DMA_HALT_TIMEOUT 500
8836 +
8837 +
8838 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8839 +{
8840 + int timeout=1;
8841 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8842 + rc32438_writel(0, &ch->dmac);
8843 +
8844 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8845 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8846 + rc32438_writel(0, &ch->dmas);
8847 + break;
8848 + }
8849 + }
8850 +
8851 + }
8852 +
8853 + return timeout ? 0 : 1;
8854 +}
8855 +
8856 +
8857 +
8858 +
8859 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8860 +{
8861 + rc32438_writel(0, &ch->dmandptr);
8862 + rc32438_writel(dma_addr, &ch->dmadptr);
8863 +}
8864 +
8865 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8866 +{
8867 + rc32438_writel(dma_addr, &ch->dmandptr);
8868 +}
8869 +#endif //__IDT_RC32438_DMA_V_H__
8870 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8871 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
8872 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-06-18 12:44:28.000000000 +0200
8873 @@ -0,0 +1,328 @@
8874 +/**************************************************************************
8875 + *
8876 + * BRIEF MODULE DESCRIPTION
8877 + * Definitions for IDT EB438 ethernet
8878 + *
8879 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8880 + *
8881 + * This program is free software; you can redistribute it and/or modify it
8882 + * under the terms of the GNU General Public License as published by the
8883 + * Free Software Foundation; either version 2 of the License, or (at your
8884 + * option) any later version.
8885 + *
8886 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8887 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8888 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8889 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8890 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8891 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8892 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8893 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8894 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8895 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8896 + *
8897 + * You should have received a copy of the GNU General Public License along
8898 + * with this program; if not, write to the Free Software Foundation, Inc.,
8899 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8900 + *
8901 + *
8902 + **************************************************************************
8903 + * May 2004 P. Sadik.
8904 + *
8905 + * Initial Release
8906 + *
8907 + *
8908 + *
8909 + **************************************************************************
8910 + */
8911 +
8912 +#ifndef __IDT_RC32438_ETH_H__
8913 +#define __IDT_RC32438_ETH_H__
8914 +enum
8915 +{
8916 + ETH0_PhysicalAddress = 0x18058000,
8917 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
8918 +
8919 + ETH0_VirtualAddress = 0xb8058000,
8920 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
8921 + ETH1_PhysicalAddress = 0x18060000,
8922 + ETH1_VirtualAddress = 0xb8060000, // Default
8923 +} ;
8924 +
8925 +typedef struct
8926 +{
8927 + u32 ethintfc ;
8928 + u32 ethfifott ;
8929 + u32 etharc ;
8930 + u32 ethhash0 ;
8931 + u32 ethhash1 ;
8932 + u32 ethu0 [4] ; // Reserved.
8933 + u32 ethpfs ;
8934 + u32 ethmcp ;
8935 + u32 eth_u1 [10] ; // Reserved.
8936 + u32 ethspare ;
8937 + u32 eth_u2 [42] ; // Reserved.
8938 + u32 ethsal0 ;
8939 + u32 ethsah0 ;
8940 + u32 ethsal1 ;
8941 + u32 ethsah1 ;
8942 + u32 ethsal2 ;
8943 + u32 ethsah2 ;
8944 + u32 ethsal3 ;
8945 + u32 ethsah3 ;
8946 + u32 ethrbc ;
8947 + u32 ethrpc ;
8948 + u32 ethrupc ;
8949 + u32 ethrfc ;
8950 + u32 ethtbc ;
8951 + u32 ethgpf ;
8952 + u32 eth_u9 [50] ; // Reserved.
8953 + u32 ethmac1 ;
8954 + u32 ethmac2 ;
8955 + u32 ethipgt ;
8956 + u32 ethipgr ;
8957 + u32 ethclrt ;
8958 + u32 ethmaxf ;
8959 + u32 eth_u10 ; // Reserved.
8960 + u32 ethmtest ;
8961 + u32 miimcfg ;
8962 + u32 miimcmd ;
8963 + u32 miimaddr ;
8964 + u32 miimwtd ;
8965 + u32 miimrdd ;
8966 + u32 miimind ;
8967 + u32 eth_u11 ; // Reserved.
8968 + u32 eth_u12 ; // Reserved.
8969 + u32 ethcfsa0 ;
8970 + u32 ethcfsa1 ;
8971 + u32 ethcfsa2 ;
8972 +} volatile *ETH_t;
8973 +
8974 +enum
8975 +{
8976 + ETHINTFC_en_b = 0,
8977 + ETHINTFC_en_m = 0x00000001,
8978 + ETHINTFC_its_b = 1,
8979 + ETHINTFC_its_m = 0x00000002,
8980 + ETHINTFC_rip_b = 2,
8981 + ETHINTFC_rip_m = 0x00000004,
8982 + ETHINTFC_jam_b = 3,
8983 + ETHINTFC_jam_m = 0x00000008,
8984 + ETHINTFC_ovr_b = 4,
8985 + ETHINTFC_ovr_m = 0x00000010,
8986 + ETHINTFC_und_b = 5,
8987 + ETHINTFC_und_m = 0x00000020,
8988 +
8989 + ETHFIFOTT_tth_b = 0,
8990 + ETHFIFOTT_tth_m = 0x0000007f,
8991 +
8992 + ETHARC_pro_b = 0,
8993 + ETHARC_pro_m = 0x00000001,
8994 + ETHARC_am_b = 1,
8995 + ETHARC_am_m = 0x00000002,
8996 + ETHARC_afm_b = 2,
8997 + ETHARC_afm_m = 0x00000004,
8998 + ETHARC_ab_b = 3,
8999 + ETHARC_ab_m = 0x00000008,
9000 +
9001 + ETHSAL_byte5_b = 0,
9002 + ETHSAL_byte5_m = 0x000000ff,
9003 + ETHSAL_byte4_b = 8,
9004 + ETHSAL_byte4_m = 0x0000ff00,
9005 + ETHSAL_byte3_b = 16,
9006 + ETHSAL_byte3_m = 0x00ff0000,
9007 + ETHSAL_byte2_b = 24,
9008 + ETHSAL_byte2_m = 0xff000000,
9009 +
9010 + ETHSAH_byte1_b = 0,
9011 + ETHSAH_byte1_m = 0x000000ff,
9012 + ETHSAH_byte0_b = 8,
9013 + ETHSAH_byte0_m = 0x0000ff00,
9014 +
9015 + ETHGPF_ptv_b = 0,
9016 + ETHGPF_ptv_m = 0x0000ffff,
9017 +
9018 + ETHPFS_pfd_b = 0,
9019 + ETHPFS_pfd_m = 0x00000001,
9020 +
9021 + ETHCFSA0_cfsa4_b = 0,
9022 + ETHCFSA0_cfsa4_m = 0x000000ff,
9023 + ETHCFSA0_cfsa5_b = 8,
9024 + ETHCFSA0_cfsa5_m = 0x0000ff00,
9025 +
9026 + ETHCFSA1_cfsa2_b = 0,
9027 + ETHCFSA1_cfsa2_m = 0x000000ff,
9028 + ETHCFSA1_cfsa3_b = 8,
9029 + ETHCFSA1_cfsa3_m = 0x0000ff00,
9030 +
9031 + ETHCFSA2_cfsa0_b = 0,
9032 + ETHCFSA2_cfsa0_m = 0x000000ff,
9033 + ETHCFSA2_cfsa1_b = 8,
9034 + ETHCFSA2_cfsa1_m = 0x0000ff00,
9035 +
9036 + ETHMAC1_re_b = 0,
9037 + ETHMAC1_re_m = 0x00000001,
9038 + ETHMAC1_paf_b = 1,
9039 + ETHMAC1_paf_m = 0x00000002,
9040 + ETHMAC1_rfc_b = 2,
9041 + ETHMAC1_rfc_m = 0x00000004,
9042 + ETHMAC1_tfc_b = 3,
9043 + ETHMAC1_tfc_m = 0x00000008,
9044 + ETHMAC1_lb_b = 4,
9045 + ETHMAC1_lb_m = 0x00000010,
9046 + ETHMAC1_mr_b = 31,
9047 + ETHMAC1_mr_m = 0x80000000,
9048 +
9049 + ETHMAC2_fd_b = 0,
9050 + ETHMAC2_fd_m = 0x00000001,
9051 + ETHMAC2_flc_b = 1,
9052 + ETHMAC2_flc_m = 0x00000002,
9053 + ETHMAC2_hfe_b = 2,
9054 + ETHMAC2_hfe_m = 0x00000004,
9055 + ETHMAC2_dc_b = 3,
9056 + ETHMAC2_dc_m = 0x00000008,
9057 + ETHMAC2_cen_b = 4,
9058 + ETHMAC2_cen_m = 0x00000010,
9059 + ETHMAC2_pe_b = 5,
9060 + ETHMAC2_pe_m = 0x00000020,
9061 + ETHMAC2_vpe_b = 6,
9062 + ETHMAC2_vpe_m = 0x00000040,
9063 + ETHMAC2_ape_b = 7,
9064 + ETHMAC2_ape_m = 0x00000080,
9065 + ETHMAC2_ppe_b = 8,
9066 + ETHMAC2_ppe_m = 0x00000100,
9067 + ETHMAC2_lpe_b = 9,
9068 + ETHMAC2_lpe_m = 0x00000200,
9069 + ETHMAC2_nb_b = 12,
9070 + ETHMAC2_nb_m = 0x00001000,
9071 + ETHMAC2_bp_b = 13,
9072 + ETHMAC2_bp_m = 0x00002000,
9073 + ETHMAC2_ed_b = 14,
9074 + ETHMAC2_ed_m = 0x00004000,
9075 +
9076 + ETHIPGT_ipgt_b = 0,
9077 + ETHIPGT_ipgt_m = 0x0000007f,
9078 +
9079 + ETHIPGR_ipgr2_b = 0,
9080 + ETHIPGR_ipgr2_m = 0x0000007f,
9081 + ETHIPGR_ipgr1_b = 8,
9082 + ETHIPGR_ipgr1_m = 0x00007f00,
9083 +
9084 + ETHCLRT_maxret_b = 0,
9085 + ETHCLRT_maxret_m = 0x0000000f,
9086 + ETHCLRT_colwin_b = 8,
9087 + ETHCLRT_colwin_m = 0x00003f00,
9088 +
9089 + ETHMAXF_maxf_b = 0,
9090 + ETHMAXF_maxf_m = 0x0000ffff,
9091 +
9092 + ETHMTEST_tb_b = 2,
9093 + ETHMTEST_tb_m = 0x00000004,
9094 +
9095 + ETHMCP_div_b = 0,
9096 + ETHMCP_div_m = 0x000000ff,
9097 +
9098 + MIIMCFG_rsv_b = 0,
9099 + MIIMCFG_rsv_m = 0x0000000c,
9100 +
9101 + MIIMCMD_rd_b = 0,
9102 + MIIMCMD_rd_m = 0x00000001,
9103 + MIIMCMD_scn_b = 1,
9104 + MIIMCMD_scn_m = 0x00000002,
9105 +
9106 + MIIMADDR_regaddr_b = 0,
9107 + MIIMADDR_regaddr_m = 0x0000001f,
9108 + MIIMADDR_phyaddr_b = 8,
9109 + MIIMADDR_phyaddr_m = 0x00001f00,
9110 +
9111 + MIIMWTD_wdata_b = 0,
9112 + MIIMWTD_wdata_m = 0x0000ffff,
9113 +
9114 + MIIMRDD_rdata_b = 0,
9115 + MIIMRDD_rdata_m = 0x0000ffff,
9116 +
9117 + MIIMIND_bsy_b = 0,
9118 + MIIMIND_bsy_m = 0x00000001,
9119 + MIIMIND_scn_b = 1,
9120 + MIIMIND_scn_m = 0x00000002,
9121 + MIIMIND_nv_b = 2,
9122 + MIIMIND_nv_m = 0x00000004,
9123 +
9124 +} ;
9125 +
9126 +/*
9127 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9128 + */
9129 +enum
9130 +{
9131 + ETHRX_fd_b = 0,
9132 + ETHRX_fd_m = 0x00000001,
9133 + ETHRX_ld_b = 1,
9134 + ETHRX_ld_m = 0x00000002,
9135 + ETHRX_rok_b = 2,
9136 + ETHRX_rok_m = 0x00000004,
9137 + ETHRX_fm_b = 3,
9138 + ETHRX_fm_m = 0x00000008,
9139 + ETHRX_mp_b = 4,
9140 + ETHRX_mp_m = 0x00000010,
9141 + ETHRX_bp_b = 5,
9142 + ETHRX_bp_m = 0x00000020,
9143 + ETHRX_vlt_b = 6,
9144 + ETHRX_vlt_m = 0x00000040,
9145 + ETHRX_cf_b = 7,
9146 + ETHRX_cf_m = 0x00000080,
9147 + ETHRX_ovr_b = 8,
9148 + ETHRX_ovr_m = 0x00000100,
9149 + ETHRX_crc_b = 9,
9150 + ETHRX_crc_m = 0x00000200,
9151 + ETHRX_cv_b = 10,
9152 + ETHRX_cv_m = 0x00000400,
9153 + ETHRX_db_b = 11,
9154 + ETHRX_db_m = 0x00000800,
9155 + ETHRX_le_b = 12,
9156 + ETHRX_le_m = 0x00001000,
9157 + ETHRX_lor_b = 13,
9158 + ETHRX_lor_m = 0x00002000,
9159 + ETHRX_ces_b = 14,
9160 + ETHRX_ces_m = 0x00004000,
9161 + ETHRX_length_b = 16,
9162 + ETHRX_length_m = 0xffff0000,
9163 +
9164 + ETHTX_fd_b = 0,
9165 + ETHTX_fd_m = 0x00000001,
9166 + ETHTX_ld_b = 1,
9167 + ETHTX_ld_m = 0x00000002,
9168 + ETHTX_oen_b = 2,
9169 + ETHTX_oen_m = 0x00000004,
9170 + ETHTX_pen_b = 3,
9171 + ETHTX_pen_m = 0x00000008,
9172 + ETHTX_cen_b = 4,
9173 + ETHTX_cen_m = 0x00000010,
9174 + ETHTX_hen_b = 5,
9175 + ETHTX_hen_m = 0x00000020,
9176 + ETHTX_tok_b = 6,
9177 + ETHTX_tok_m = 0x00000040,
9178 + ETHTX_mp_b = 7,
9179 + ETHTX_mp_m = 0x00000080,
9180 + ETHTX_bp_b = 8,
9181 + ETHTX_bp_m = 0x00000100,
9182 + ETHTX_und_b = 9,
9183 + ETHTX_und_m = 0x00000200,
9184 + ETHTX_of_b = 10,
9185 + ETHTX_of_m = 0x00000400,
9186 + ETHTX_ed_b = 11,
9187 + ETHTX_ed_m = 0x00000800,
9188 + ETHTX_ec_b = 12,
9189 + ETHTX_ec_m = 0x00001000,
9190 + ETHTX_lc_b = 13,
9191 + ETHTX_lc_m = 0x00002000,
9192 + ETHTX_td_b = 14,
9193 + ETHTX_td_m = 0x00004000,
9194 + ETHTX_crc_b = 15,
9195 + ETHTX_crc_m = 0x00008000,
9196 + ETHTX_le_b = 16,
9197 + ETHTX_le_m = 0x00010000,
9198 + ETHTX_cc_b = 17,
9199 + ETHTX_cc_m = 0x001E0000,
9200 +} ;
9201 +#endif //__IDT_RC32438_ETH_H__
9202 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9203 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
9204 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-06-18 12:44:28.000000000 +0200
9205 @@ -0,0 +1,72 @@
9206 +/**************************************************************************
9207 + *
9208 + * BRIEF MODULE DESCRIPTION
9209 + * macros for IDT EB438 ethernet
9210 + *
9211 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9212 + *
9213 + * This program is free software; you can redistribute it and/or modify it
9214 + * under the terms of the GNU General Public License as published by the
9215 + * Free Software Foundation; either version 2 of the License, or (at your
9216 + * option) any later version.
9217 + *
9218 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9219 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9220 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9221 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9222 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9223 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9224 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9225 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9226 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9227 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9228 + *
9229 + * You should have received a copy of the GNU General Public License along
9230 + * with this program; if not, write to the Free Software Foundation, Inc.,
9231 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9232 + *
9233 + *
9234 + **************************************************************************
9235 + * May 2004 P. Sadik.
9236 + *
9237 + * Initial Release
9238 + *
9239 + *
9240 + *
9241 + **************************************************************************
9242 + */
9243 +
9244 +#ifndef __IDT_RC32438_ETH_V_H__
9245 +#define __IDT_RC32438_ETH_V_H__
9246 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
9247 +
9248 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
9249 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
9250 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
9251 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
9252 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
9253 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
9254 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
9255 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
9256 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
9257 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
9258 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
9259 +
9260 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
9261 +
9262 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
9263 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
9264 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
9265 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
9266 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
9267 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
9268 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
9269 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
9270 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
9271 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
9272 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
9273 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
9274 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
9275 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
9276 +
9277 +#endif //__IDT_RC32438_ETH_V_H__
9278 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9279 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
9280 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-06-18 12:44:28.000000000 +0200
9281 @@ -0,0 +1,257 @@
9282 +/**************************************************************************
9283 + *
9284 + * BRIEF MODULE DESCRIPTION
9285 + * Definitions for IDT RC32438 GPIO.
9286 + *
9287 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9288 + *
9289 + * This program is free software; you can redistribute it and/or modify it
9290 + * under the terms of the GNU General Public License as published by the
9291 + * Free Software Foundation; either version 2 of the License, or (at your
9292 + * option) any later version.
9293 + *
9294 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9295 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9296 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9297 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9298 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9299 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9300 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9301 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9302 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9303 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9304 + *
9305 + * You should have received a copy of the GNU General Public License along
9306 + * with this program; if not, write to the Free Software Foundation, Inc.,
9307 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9308 + *
9309 + *
9310 + **************************************************************************
9311 + * May 2004 P. Sadik.
9312 + *
9313 + * Initial Release
9314 + *
9315 + *
9316 + *
9317 + **************************************************************************
9318 + */
9319 +#ifndef __IDT_RC32438_GPIO_H__
9320 +#define __IDT_RC32438_GPIO_H__
9321 +enum
9322 +{
9323 + GPIO0_PhysicalAddress = 0x18048000,
9324 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
9325 +
9326 + GPIO0_VirtualAddress = 0xb8048000,
9327 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
9328 +} ;
9329 +
9330 +typedef struct
9331 +{
9332 + u32 gpiofunc; /* GPIO Function Register
9333 + * gpiofunc[x]==0 bit = gpio
9334 + * func[x]==1 bit = altfunc
9335 + */
9336 + u32 gpiocfg; /* GPIO Configuration Register
9337 + * gpiocfg[x]==0 bit = input
9338 + * gpiocfg[x]==1 bit = output
9339 + */
9340 + u32 gpiod; /* GPIO Data Register
9341 + * gpiod[x] read/write gpio pinX status
9342 + */
9343 + u32 gpioilevel; /* GPIO Interrupt Status Register
9344 + * interrupt level (see gpioistat)
9345 + */
9346 + u32 gpioistat; /* Gpio Interrupt Status Register
9347 + * istat[x] = (gpiod[x] == level[x])
9348 + * cleared in ISR (STICKY bits)
9349 + */
9350 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
9351 +} volatile * GPIO_t ;
9352 +
9353 +typedef enum
9354 +{
9355 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
9356 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
9357 + GPIO_input_v = 0, // gpiocfg use pin as input.
9358 + GPIO_output_v = 1, // gpiocfg use pin as output.
9359 + GPIO_pin0_b = 0,
9360 + GPIO_pin0_m = 0x00000001,
9361 + GPIO_pin1_b = 1,
9362 + GPIO_pin1_m = 0x00000002,
9363 + GPIO_pin2_b = 2,
9364 + GPIO_pin2_m = 0x00000004,
9365 + GPIO_pin3_b = 3,
9366 + GPIO_pin3_m = 0x00000008,
9367 + GPIO_pin4_b = 4,
9368 + GPIO_pin4_m = 0x00000010,
9369 + GPIO_pin5_b = 5,
9370 + GPIO_pin5_m = 0x00000020,
9371 + GPIO_pin6_b = 6,
9372 + GPIO_pin6_m = 0x00000040,
9373 + GPIO_pin7_b = 7,
9374 + GPIO_pin7_m = 0x00000080,
9375 + GPIO_pin8_b = 8,
9376 + GPIO_pin8_m = 0x00000100,
9377 + GPIO_pin9_b = 9,
9378 + GPIO_pin9_m = 0x00000200,
9379 + GPIO_pin10_b = 10,
9380 + GPIO_pin10_m = 0x00000400,
9381 + GPIO_pin11_b = 11,
9382 + GPIO_pin11_m = 0x00000800,
9383 + GPIO_pin12_b = 12,
9384 + GPIO_pin12_m = 0x00001000,
9385 + GPIO_pin13_b = 13,
9386 + GPIO_pin13_m = 0x00002000,
9387 + GPIO_pin14_b = 14,
9388 + GPIO_pin14_m = 0x00004000,
9389 + GPIO_pin15_b = 15,
9390 + GPIO_pin15_m = 0x00008000,
9391 + GPIO_pin16_b = 16,
9392 + GPIO_pin16_m = 0x00010000,
9393 + GPIO_pin17_b = 17,
9394 + GPIO_pin17_m = 0x00020000,
9395 + GPIO_pin18_b = 18,
9396 + GPIO_pin18_m = 0x00040000,
9397 + GPIO_pin19_b = 19,
9398 + GPIO_pin19_m = 0x00080000,
9399 + GPIO_pin20_b = 20,
9400 + GPIO_pin20_m = 0x00100000,
9401 + GPIO_pin21_b = 21,
9402 + GPIO_pin21_m = 0x00200000,
9403 + GPIO_pin22_b = 22,
9404 + GPIO_pin22_m = 0x00400000,
9405 + GPIO_pin23_b = 23,
9406 + GPIO_pin23_m = 0x00800000,
9407 + GPIO_pin24_b = 24,
9408 + GPIO_pin24_m = 0x01000000,
9409 + GPIO_pin25_b = 25,
9410 + GPIO_pin25_m = 0x02000000,
9411 + GPIO_pin26_b = 26,
9412 + GPIO_pin26_m = 0x04000000,
9413 + GPIO_pin27_b = 27,
9414 + GPIO_pin27_m = 0x08000000,
9415 + GPIO_pin28_b = 28,
9416 + GPIO_pin28_m = 0x10000000,
9417 + GPIO_pin29_b = 29,
9418 + GPIO_pin29_m = 0x20000000,
9419 + GPIO_pin30_b = 30,
9420 + GPIO_pin30_m = 0x40000000,
9421 + GPIO_pin31_b = 31,
9422 + GPIO_pin31_m = 0x80000000,
9423 +
9424 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
9425 +
9426 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
9427 + GPIO_u0sout_m = GPIO_pin0_m,
9428 + GPIO_u0sout_cfg_v = GPIO_output_v,
9429 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
9430 + GPIO_u0sinp_m = GPIO_pin1_m,
9431 + GPIO_u0sinp_cfg_v = GPIO_input_v,
9432 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
9433 + GPIO_u0rin_m = GPIO_pin2_m,
9434 + GPIO_u0rin_cfg_v = GPIO_input_v,
9435 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
9436 + GPIO_u0dcdn_m = GPIO_pin3_m,
9437 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
9438 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
9439 + GPIO_u0dtrn_m = GPIO_pin4_m,
9440 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
9441 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
9442 + GPIO_u0dsrn_m = GPIO_pin5_m,
9443 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
9444 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
9445 + GPIO_u0rtsn_m = GPIO_pin6_m,
9446 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
9447 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
9448 + GPIO_u0ctsn_m = GPIO_pin7_m,
9449 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
9450 +
9451 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
9452 + GPIO_u1sout_m = GPIO_pin8_m,
9453 + GPIO_u1sout_cfg_v = GPIO_output_v,
9454 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
9455 + GPIO_u1sinp_m = GPIO_pin9_m,
9456 + GPIO_u1sinp_cfg_v = GPIO_input_v,
9457 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
9458 + GPIO_u1dtrn_m = GPIO_pin10_m,
9459 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
9460 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
9461 + GPIO_u1dsrn_m = GPIO_pin11_m,
9462 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
9463 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
9464 + GPIO_u1rtsn_m = GPIO_pin12_m,
9465 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
9466 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
9467 + GPIO_u1ctsn_m = GPIO_pin13_m,
9468 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
9469 +
9470 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
9471 + GPIO_dmareqn0_m = GPIO_pin14_m,
9472 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
9473 +
9474 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
9475 + GPIO_dmareqn1_m = GPIO_pin15_m,
9476 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
9477 +
9478 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
9479 + GPIO_dmadonen0_m = GPIO_pin16_m,
9480 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
9481 +
9482 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
9483 + GPIO_dmadonen1_m = GPIO_pin17_m,
9484 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
9485 +
9486 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
9487 + GPIO_dmafinn0_m = GPIO_pin18_m,
9488 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
9489 +
9490 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
9491 + GPIO_dmafinn1_m = GPIO_pin19_m,
9492 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
9493 +
9494 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
9495 + GPIO_maddr22_m = GPIO_pin20_m,
9496 + GPIO_maddr22_cfg_v = GPIO_output_v,
9497 +
9498 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
9499 + GPIO_maddr23_m = GPIO_pin21_m,
9500 + GPIO_maddr23_cfg_v = GPIO_output_v,
9501 +
9502 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
9503 + GPIO_maddr24_m = GPIO_pin22_m,
9504 + GPIO_maddr24_cfg_v = GPIO_output_v,
9505 +
9506 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
9507 + GPIO_maddr25_m = GPIO_pin23_m,
9508 + GPIO_maddr25_cfg_v = GPIO_output_v,
9509 +
9510 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
9511 + GPIO_afspare6_m = GPIO_pin24_m,
9512 + GPIO_afspare6_cfg_v = GPIO_input_v,
9513 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
9514 + GPIO_afspare5_m = GPIO_pin25_m,
9515 + GPIO_afspare5_cfg_v = GPIO_input_v,
9516 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
9517 + GPIO_afspare4_m = GPIO_pin26_m,
9518 + GPIO_afspare4_cfg_v = GPIO_input_v,
9519 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
9520 + GPIO_afspare3_m = GPIO_pin27_m,
9521 + GPIO_afspare3_cfg_v = GPIO_input_v,
9522 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
9523 + GPIO_afspare2_m = GPIO_pin28_m,
9524 + GPIO_afspare2_cfg_v = GPIO_input_v,
9525 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
9526 + GPIO_afspare1_m = GPIO_pin29_m,
9527 + GPIO_afspare1_cfg_v = GPIO_input_v,
9528 +
9529 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
9530 + GPIO_pcimuintn_m = GPIO_pin30_m,
9531 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
9532 +
9533 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
9534 + GPIO_rngclk_m = GPIO_pin31_m,
9535 + GPIO_rncclk_cfg_v = GPIO_input_v,
9536 +} GPIO_DEFS_t;
9537 +
9538 +#endif //__IDT_RC32438_GPIO_H__
9539 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9540 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
9541 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-06-18 12:44:28.000000000 +0200
9542 @@ -0,0 +1,152 @@
9543 +/**************************************************************************
9544 + *
9545 + * BRIEF MODULE DESCRIPTION
9546 + * Definitions for IDT RC32438 CPU.
9547 + *
9548 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9549 + *
9550 + * This program is free software; you can redistribute it and/or modify it
9551 + * under the terms of the GNU General Public License as published by the
9552 + * Free Software Foundation; either version 2 of the License, or (at your
9553 + * option) any later version.
9554 + *
9555 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9556 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9557 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9558 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9559 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9560 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9561 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9562 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9563 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9564 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9565 + *
9566 + * You should have received a copy of the GNU General Public License along
9567 + * with this program; if not, write to the Free Software Foundation, Inc.,
9568 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9569 + *
9570 + *
9571 + **************************************************************************
9572 + * May 2004 P. Sadik.
9573 + *
9574 + * Initial Release
9575 + *
9576 + *
9577 + *
9578 + **************************************************************************
9579 + */
9580 +
9581 +#ifndef __IDT_RC32438_H__
9582 +#define __IDT_RC32438_H__
9583 +#include <linux/config.h>
9584 +#include <linux/delay.h>
9585 +#include <asm/io.h>
9586 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9587 +
9588 +#define RC32438_REG_BASE 0x18000000
9589 +
9590 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9591 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
9592 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
9593 +
9594 +#define IDT_CLOCK_MULT 2
9595 +#define MIPS_CPU_TIMER_IRQ 7
9596 +/* Interrupt Controller */
9597 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
9598 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
9599 +#define IC_GROUP_OFFSET 0x0C
9600 +#define RTC_BASE 0xAC0801FF0
9601 +
9602 +#define NUM_INTR_GROUPS 5
9603 +/* 16550 UARTs */
9604 +
9605 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
9606 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9607 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9608 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9609 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9610 +
9611 +#ifdef __MIPSEB__
9612 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9613 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9614 +#else
9615 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9616 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9617 +#endif
9618 +
9619 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
9620 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
9621 +
9622 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
9623 +
9624 +
9625 +
9626 +/* cpu pipeline flush */
9627 +static inline void rc32438_sync(void)
9628 +{
9629 + __asm__ volatile ("sync");
9630 +}
9631 +
9632 +static inline void rc32438_sync_udelay(int us)
9633 +{
9634 + __asm__ volatile ("sync");
9635 + udelay(us);
9636 +}
9637 +
9638 +static inline void rc32438_sync_delay(int ms)
9639 +{
9640 + __asm__ volatile ("sync");
9641 + mdelay(ms);
9642 +}
9643 +
9644 +/*
9645 + * Macros to access internal RC32438 registers. No byte
9646 + * swapping should be done when accessing the internal
9647 + * registers.
9648 + */
9649 +
9650 +#define rc32438_readb __raw_readb
9651 +#define rc32438_readw __raw_readw
9652 +#define rc32438_readl __raw_readl
9653 +
9654 +#define rc32438_writeb __raw_writeb
9655 +#define rc32438_writew __raw_writew
9656 +#define rc32438_writel __raw_writel
9657 +
9658 +/*
9659 + * C access to CLZ and CLO instructions
9660 + * (count leading zeroes/ones).
9661 + */
9662 +static inline int rc32438_clz(unsigned long val)
9663 +{
9664 + int ret;
9665 + __asm__ volatile (
9666 + ".set\tnoreorder\n\t"
9667 + ".set\tnoat\n\t"
9668 + ".set\tmips32\n\t"
9669 + "clz\t%0,%1\n\t"
9670 + ".set\tmips0\n\t"
9671 + ".set\tat\n\t"
9672 + ".set\treorder"
9673 + : "=r" (ret)
9674 + : "r" (val));
9675 +
9676 + return ret;
9677 +}
9678 +static inline int rc32438_clo(unsigned long val)
9679 +{
9680 + int ret;
9681 + __asm__ volatile (
9682 + ".set\tnoreorder\n\t"
9683 + ".set\tnoat\n\t"
9684 + ".set\tmips32\n\t"
9685 + "clo\t%0,%1\n\t"
9686 + ".set\tmips0\n\t"
9687 + ".set\tat\n\t"
9688 + ".set\treorder"
9689 + : "=r" (ret)
9690 + : "r" (val));
9691 +
9692 + return ret;
9693 +}
9694 +#endif //__IDT_RC32438_H__
9695 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9696 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
9697 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-06-18 12:44:28.000000000 +0200
9698 @@ -0,0 +1,510 @@
9699 +/**************************************************************************
9700 + *
9701 + * BRIEF MODULE DESCRIPTION
9702 + * Definitions for IDT RC32438 PCI.
9703 + *
9704 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9705 + *
9706 + * This program is free software; you can redistribute it and/or modify it
9707 + * under the terms of the GNU General Public License as published by the
9708 + * Free Software Foundation; either version 2 of the License, or (at your
9709 + * option) any later version.
9710 + *
9711 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9712 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9713 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9714 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9715 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9716 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9717 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9718 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9719 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9720 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9721 + *
9722 + * You should have received a copy of the GNU General Public License along
9723 + * with this program; if not, write to the Free Software Foundation, Inc.,
9724 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9725 + *
9726 + *
9727 + **************************************************************************
9728 + * May 2004 P. Sadik
9729 + *
9730 + * Initial Release
9731 + *
9732 + *
9733 + *
9734 + **************************************************************************
9735 + */
9736 +
9737 +enum
9738 +{
9739 + PCI0_PhysicalAddress = 0x18080000,
9740 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
9741 +
9742 + PCI0_VirtualAddress = 0xb8080000,
9743 + PCI_VirtualAddress = PCI0_VirtualAddress,
9744 +} ;
9745 +
9746 +enum
9747 +{
9748 + PCI_LbaCount = 4, // Local base addresses.
9749 +} ;
9750 +
9751 +typedef struct
9752 +{
9753 + u32 a ; // Address.
9754 + u32 c ; // Control.
9755 + u32 m ; // mapping.
9756 +} PCI_Map_s ;
9757 +
9758 +typedef struct
9759 +{
9760 + u32 pcic ;
9761 + u32 pcis ;
9762 + u32 pcism ;
9763 + u32 pcicfga ;
9764 + u32 pcicfgd ;
9765 + PCI_Map_s pcilba [PCI_LbaCount] ;
9766 + u32 pcidac ;
9767 + u32 pcidas ;
9768 + u32 pcidasm ;
9769 + u32 pcidad ;
9770 + u32 pcidma8c ;
9771 + u32 pcidma9c ;
9772 + u32 pcitc ;
9773 +} volatile *PCI_t ;
9774 +
9775 +// PCI messaging unit.
9776 +enum
9777 +{
9778 + PCIM_Count = 2,
9779 +} ;
9780 +typedef struct
9781 +{
9782 + u32 pciim [PCIM_Count] ;
9783 + u32 pciom [PCIM_Count] ;
9784 + u32 pciid ;
9785 + u32 pciiic ;
9786 + u32 pciiim ;
9787 + u32 pciiod ;
9788 + u32 pciioic ;
9789 + u32 pciioim ;
9790 +} volatile *PCIM_t ;
9791 +
9792 +/*******************************************************************************
9793 + *
9794 + * PCI Control Register
9795 + *
9796 + ******************************************************************************/
9797 +enum
9798 +{
9799 + PCIC_en_b = 0,
9800 + PCIC_en_m = 0x00000001,
9801 + PCIC_tnr_b = 1,
9802 + PCIC_tnr_m = 0x00000002,
9803 + PCIC_sce_b = 2,
9804 + PCIC_sce_m = 0x00000004,
9805 + PCIC_ien_b = 3,
9806 + PCIC_ien_m = 0x00000008,
9807 + PCIC_aaa_b = 4,
9808 + PCIC_aaa_m = 0x00000010,
9809 + PCIC_eap_b = 5,
9810 + PCIC_eap_m = 0x00000020,
9811 + PCIC_pcim_b = 6,
9812 + PCIC_pcim_m = 0x000001c0,
9813 + PCIC_pcim_disabled_v = 0,
9814 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
9815 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
9816 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
9817 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
9818 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
9819 + PCIC_pcim_reserved6_v = 6,
9820 + PCIC_pcim_reserved7_v = 7,
9821 + PCIC_igm_b = 9,
9822 + PCIC_igm_m = 0x00000200,
9823 +} ;
9824 +
9825 +/*******************************************************************************
9826 + *
9827 + * PCI Status Register
9828 + *
9829 + ******************************************************************************/
9830 +enum {
9831 + PCIS_eed_b = 0,
9832 + PCIS_eed_m = 0x00000001,
9833 + PCIS_wr_b = 1,
9834 + PCIS_wr_m = 0x00000002,
9835 + PCIS_nmi_b = 2,
9836 + PCIS_nmi_m = 0x00000004,
9837 + PCIS_ii_b = 3,
9838 + PCIS_ii_m = 0x00000008,
9839 + PCIS_cwe_b = 4,
9840 + PCIS_cwe_m = 0x00000010,
9841 + PCIS_cre_b = 5,
9842 + PCIS_cre_m = 0x00000020,
9843 + PCIS_mdpe_b = 6,
9844 + PCIS_mdpe_m = 0x00000040,
9845 + PCIS_sta_b = 7,
9846 + PCIS_sta_m = 0x00000080,
9847 + PCIS_rta_b = 8,
9848 + PCIS_rta_m = 0x00000100,
9849 + PCIS_rma_b = 9,
9850 + PCIS_rma_m = 0x00000200,
9851 + PCIS_sse_b = 10,
9852 + PCIS_sse_m = 0x00000400,
9853 + PCIS_ose_b = 11,
9854 + PCIS_ose_m = 0x00000800,
9855 + PCIS_pe_b = 12,
9856 + PCIS_pe_m = 0x00001000,
9857 + PCIS_tae_b = 13,
9858 + PCIS_tae_m = 0x00002000,
9859 + PCIS_rle_b = 14,
9860 + PCIS_rle_m = 0x00004000,
9861 + PCIS_bme_b = 15,
9862 + PCIS_bme_m = 0x00008000,
9863 + PCIS_prd_b = 16,
9864 + PCIS_prd_m = 0x00010000,
9865 + PCIS_rip_b = 17,
9866 + PCIS_rip_m = 0x00020000,
9867 +} ;
9868 +
9869 +/*******************************************************************************
9870 + *
9871 + * PCI Status Mask Register
9872 + *
9873 + ******************************************************************************/
9874 +enum {
9875 + PCISM_eed_b = 0,
9876 + PCISM_eed_m = 0x00000001,
9877 + PCISM_wr_b = 1,
9878 + PCISM_wr_m = 0x00000002,
9879 + PCISM_nmi_b = 2,
9880 + PCISM_nmi_m = 0x00000004,
9881 + PCISM_ii_b = 3,
9882 + PCISM_ii_m = 0x00000008,
9883 + PCISM_cwe_b = 4,
9884 + PCISM_cwe_m = 0x00000010,
9885 + PCISM_cre_b = 5,
9886 + PCISM_cre_m = 0x00000020,
9887 + PCISM_mdpe_b = 6,
9888 + PCISM_mdpe_m = 0x00000040,
9889 + PCISM_sta_b = 7,
9890 + PCISM_sta_m = 0x00000080,
9891 + PCISM_rta_b = 8,
9892 + PCISM_rta_m = 0x00000100,
9893 + PCISM_rma_b = 9,
9894 + PCISM_rma_m = 0x00000200,
9895 + PCISM_sse_b = 10,
9896 + PCISM_sse_m = 0x00000400,
9897 + PCISM_ose_b = 11,
9898 + PCISM_ose_m = 0x00000800,
9899 + PCISM_pe_b = 12,
9900 + PCISM_pe_m = 0x00001000,
9901 + PCISM_tae_b = 13,
9902 + PCISM_tae_m = 0x00002000,
9903 + PCISM_rle_b = 14,
9904 + PCISM_rle_m = 0x00004000,
9905 + PCISM_bme_b = 15,
9906 + PCISM_bme_m = 0x00008000,
9907 + PCISM_prd_b = 16,
9908 + PCISM_prd_m = 0x00010000,
9909 + PCISM_rip_b = 17,
9910 + PCISM_rip_m = 0x00020000,
9911 +} ;
9912 +
9913 +/*******************************************************************************
9914 + *
9915 + * PCI Configuration Address Register
9916 + *
9917 + ******************************************************************************/
9918 +enum {
9919 + PCICFGA_reg_b = 2,
9920 + PCICFGA_reg_m = 0x000000fc,
9921 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
9922 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
9923 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
9924 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
9925 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
9926 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
9927 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
9928 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
9929 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9930 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
9931 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
9932 + PCICFGA_reg_pba0m_v = 0x48>>2,
9933 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
9934 + PCICFGA_reg_pba1m_v = 0x50>>2,
9935 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
9936 + PCICFGA_reg_pba2m_v = 0x58>>2,
9937 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
9938 + PCICFGA_reg_pba3m_v = 0x60>>2,
9939 + PCICFGA_reg_pmgt_v = 0x64>>2,
9940 + PCICFGA_func_b = 8,
9941 + PCICFGA_func_m = 0x00000700,
9942 + PCICFGA_dev_b = 11,
9943 + PCICFGA_dev_m = 0x0000f800,
9944 + PCICFGA_dev_internal_v = 0,
9945 + PCICFGA_bus_b = 16,
9946 + PCICFGA_bus_m = 0x00ff0000,
9947 + PCICFGA_bus_type0_v = 0, //local bus
9948 + PCICFGA_en_b = 31, // read only
9949 + PCICFGA_en_m = 0x80000000,
9950 +} ;
9951 +
9952 +enum {
9953 + PCFGID_vendor_b = 0,
9954 + PCFGID_vendor_m = 0x0000ffff,
9955 + PCFGID_vendor_IDT_v = 0x111d,
9956 + PCFGID_device_b = 16,
9957 + PCFGID_device_m = 0xffff0000,
9958 + PCFGID_device_Acaciade_v = 0x0207,
9959 +
9960 + PCFG04_command_ioena_b = 1,
9961 + PCFG04_command_ioena_m = 0x00000001,
9962 + PCFG04_command_memena_b = 2,
9963 + PCFG04_command_memena_m = 0x00000002,
9964 + PCFG04_command_bmena_b = 3,
9965 + PCFG04_command_bmena_m = 0x00000004,
9966 + PCFG04_command_mwinv_b = 5,
9967 + PCFG04_command_mwinv_m = 0x00000010,
9968 + PCFG04_command_parena_b = 7,
9969 + PCFG04_command_parena_m = 0x00000040,
9970 + PCFG04_command_serrena_b = 9,
9971 + PCFG04_command_serrena_m = 0x00000100,
9972 + PCFG04_command_fastbbena_b = 10,
9973 + PCFG04_command_fastbbena_m = 0x00000200,
9974 + PCFG04_status_b = 16,
9975 + PCFG04_status_m = 0xffff0000,
9976 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
9977 + PCFG04_status_66MHz_m = 0x00200000,
9978 + PCFG04_status_fbb_b = 23,
9979 + PCFG04_status_fbb_m = 0x00800000,
9980 + PCFG04_status_mdpe_b = 24,
9981 + PCFG04_status_mdpe_m = 0x01000000,
9982 + PCFG04_status_dst_b = 25,
9983 + PCFG04_status_dst_m = 0x06000000,
9984 + PCFG04_status_sta_b = 27,
9985 + PCFG04_status_sta_m = 0x08000000,
9986 + PCFG04_status_rta_b = 28,
9987 + PCFG04_status_rta_m = 0x10000000,
9988 + PCFG04_status_rma_b = 29,
9989 + PCFG04_status_rma_m = 0x20000000,
9990 + PCFG04_status_sse_b = 30,
9991 + PCFG04_status_sse_m = 0x40000000,
9992 + PCFG04_status_pe_b = 31,
9993 + PCFG04_status_pe_m = 0x40000000,
9994 +
9995 + PCFG08_revId_b = 0,
9996 + PCFG08_revId_m = 0x000000ff,
9997 + PCFG08_classCode_b = 0,
9998 + PCFG08_classCode_m = 0xffffff00,
9999 + PCFG08_classCode_bridge_v = 06,
10000 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
10001 + PCFG0C_cacheline_b = 0,
10002 + PCFG0C_cacheline_m = 0x000000ff,
10003 + PCFG0C_masterLatency_b = 8,
10004 + PCFG0C_masterLatency_m = 0x0000ff00,
10005 + PCFG0C_headerType_b = 16,
10006 + PCFG0C_headerType_m = 0x00ff0000,
10007 + PCFG0C_bist_b = 24,
10008 + PCFG0C_bist_m = 0xff000000,
10009 +
10010 + PCIPBA_msi_b = 0,
10011 + PCIPBA_msi_m = 0x00000001,
10012 + PCIPBA_p_b = 3,
10013 + PCIPBA_p_m = 0x00000004,
10014 + PCIPBA_baddr_b = 8,
10015 + PCIPBA_baddr_m = 0xffffff00,
10016 +
10017 + PCFGSS_vendorId_b = 0,
10018 + PCFGSS_vendorId_m = 0x0000ffff,
10019 + PCFGSS_id_b = 16,
10020 + PCFGSS_id_m = 0xffff0000,
10021 +
10022 + PCFG3C_interruptLine_b = 0,
10023 + PCFG3C_interruptLine_m = 0x000000ff,
10024 + PCFG3C_interruptPin_b = 8,
10025 + PCFG3C_interruptPin_m = 0x0000ff00,
10026 + PCFG3C_minGrant_b = 16,
10027 + PCFG3C_minGrant_m = 0x00ff0000,
10028 + PCFG3C_maxLat_b = 24,
10029 + PCFG3C_maxLat_m = 0xff000000,
10030 +
10031 + PCIPBAC_msi_b = 0,
10032 + PCIPBAC_msi_m = 0x00000001,
10033 + PCIPBAC_p_b = 1,
10034 + PCIPBAC_p_m = 0x00000002,
10035 + PCIPBAC_size_b = 2,
10036 + PCIPBAC_size_m = 0x0000007c,
10037 + PCIPBAC_sb_b = 7,
10038 + PCIPBAC_sb_m = 0x00000080,
10039 + PCIPBAC_pp_b = 8,
10040 + PCIPBAC_pp_m = 0x00000100,
10041 + PCIPBAC_mr_b = 9,
10042 + PCIPBAC_mr_m = 0x00000600,
10043 + PCIPBAC_mr_read_v =0, //no prefetching
10044 + PCIPBAC_mr_readLine_v =1,
10045 + PCIPBAC_mr_readMult_v =2,
10046 + PCIPBAC_mrl_b = 11,
10047 + PCIPBAC_mrl_m = 0x00000800,
10048 + PCIPBAC_mrm_b = 12,
10049 + PCIPBAC_mrm_m = 0x00001000,
10050 + PCIPBAC_trp_b = 13,
10051 + PCIPBAC_trp_m = 0x00002000,
10052 +
10053 + PCFG40_trdyTimeout_b = 0,
10054 + PCFG40_trdyTimeout_m = 0x000000ff,
10055 + PCFG40_retryLim_b = 8,
10056 + PCFG40_retryLim_m = 0x0000ff00,
10057 +};
10058 +
10059 +/*******************************************************************************
10060 + *
10061 + * PCI Local Base Address [0|1|2|3] Register
10062 + *
10063 + ******************************************************************************/
10064 +enum {
10065 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
10066 + PCILBA_baddr_m = 0xffffff00,
10067 +} ;
10068 +/*******************************************************************************
10069 + *
10070 + * PCI Local Base Address Control Register
10071 + *
10072 + ******************************************************************************/
10073 +enum {
10074 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
10075 + PCILBAC_msi_m = 0x00000001,
10076 + PCILBAC_msi_mem_v = 0,
10077 + PCILBAC_msi_io_v = 1,
10078 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
10079 + PCILBAC_size_m = 0x0000007c,
10080 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
10081 + PCILBAC_sb_m = 0x00000080,
10082 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
10083 + PCILBAC_rt_m = 0x00000100,
10084 + PCILBAC_rt_noprefetch_v = 0, // mem read
10085 + PCILBAC_rt_prefetch_v = 1, // mem readline
10086 +} ;
10087 +
10088 +/*******************************************************************************
10089 + *
10090 + * PCI Local Base Address [0|1|2|3] Mapping Register
10091 + *
10092 + ******************************************************************************/
10093 +enum {
10094 + PCILBAM_maddr_b = 8,
10095 + PCILBAM_maddr_m = 0xffffff00,
10096 +} ;
10097 +
10098 +/*******************************************************************************
10099 + *
10100 + * PCI Decoupled Access Control Register
10101 + *
10102 + ******************************************************************************/
10103 +enum {
10104 + PCIDAC_den_b = 0,
10105 + PCIDAC_den_m = 0x00000001,
10106 +} ;
10107 +
10108 +/*******************************************************************************
10109 + *
10110 + * PCI Decoupled Access Status Register
10111 + *
10112 + ******************************************************************************/
10113 +enum {
10114 + PCIDAS_d_b = 0,
10115 + PCIDAS_d_m = 0x00000001,
10116 + PCIDAS_b_b = 1,
10117 + PCIDAS_b_m = 0x00000002,
10118 + PCIDAS_e_b = 2,
10119 + PCIDAS_e_m = 0x00000004,
10120 + PCIDAS_ofe_b = 3,
10121 + PCIDAS_ofe_m = 0x00000008,
10122 + PCIDAS_off_b = 4,
10123 + PCIDAS_off_m = 0x00000010,
10124 + PCIDAS_ife_b = 5,
10125 + PCIDAS_ife_m = 0x00000020,
10126 + PCIDAS_iff_b = 6,
10127 + PCIDAS_iff_m = 0x00000040,
10128 +} ;
10129 +
10130 +/*******************************************************************************
10131 + *
10132 + * PCI DMA Channel 8 Configuration Register
10133 + *
10134 + ******************************************************************************/
10135 +enum
10136 +{
10137 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
10138 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
10139 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
10140 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
10141 +} ;
10142 +
10143 +/*******************************************************************************
10144 + *
10145 + * PCI DMA Channel 9 Configuration Register
10146 + *
10147 + ******************************************************************************/
10148 +enum
10149 +{
10150 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
10151 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
10152 +} ;
10153 +
10154 +/*******************************************************************************
10155 + *
10156 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10157 + *
10158 + ******************************************************************************/
10159 +enum {
10160 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
10161 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
10162 + // These are for reads (DMA channel 8)
10163 + PCIDMAD_devcmd_mr_v = 0, //memory read
10164 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
10165 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
10166 + PCIDMAD_devcmd_ior_v = 3, //I/O read
10167 + // These are for writes (DMA channel 9)
10168 + PCIDMAD_devcmd_mw_v = 0, //memory write
10169 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
10170 + PCIDMAD_devcmd_iow_v = 3, //I/O write
10171 +
10172 + // Swap byte field applies to both DMA channel 8 and 9
10173 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
10174 + PCIDMAD_sb_m = 0x01000000, // swap byte field
10175 +} ;
10176 +
10177 +
10178 +/*******************************************************************************
10179 + *
10180 + * PCI Target Control Register
10181 + *
10182 + ******************************************************************************/
10183 +enum
10184 +{
10185 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
10186 + PCITC_rtimer_m = 0x000000ff,
10187 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
10188 + PCITC_dtimer_m = 0x0000ff00,
10189 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
10190 + PCITC_rdr_m = 0x00040000,
10191 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
10192 + PCITC_ddt_m = 0x00080000,
10193 +} ;
10194 +/*******************************************************************************
10195 + *
10196 + * PCI messaging unit [applies to both inbound and outbound registers ]
10197 + *
10198 + ******************************************************************************/
10199 +enum
10200 +{
10201 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10202 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
10203 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10204 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
10205 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10206 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
10207 +};
10208 +
10209 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10210 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
10211 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-06-18 12:44:28.000000000 +0200
10212 @@ -0,0 +1,190 @@
10213 +/**************************************************************************
10214 + *
10215 + * BRIEF MODULE DESCRIPTION
10216 + * Definitions for IDT RC32438 PCI setup.
10217 + *
10218 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10219 + *
10220 + * This program is free software; you can redistribute it and/or modify it
10221 + * under the terms of the GNU General Public License as published by the
10222 + * Free Software Foundation; either version 2 of the License, or (at your
10223 + * option) any later version.
10224 + *
10225 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10226 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10227 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10228 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10229 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10230 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10231 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10232 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10233 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10234 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10235 + *
10236 + * You should have received a copy of the GNU General Public License along
10237 + * with this program; if not, write to the Free Software Foundation, Inc.,
10238 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10239 + *
10240 + *
10241 + **************************************************************************
10242 + * May 2004 P. Sadik
10243 + *
10244 + * Initial Release
10245 + *
10246 + *
10247 + *
10248 + **************************************************************************
10249 + */
10250 +
10251 +#define PCI_MSG_VirtualAddress 0xB8088010
10252 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10253 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10254 +
10255 +#define PCIM_SHFT 0x6
10256 +#define PCIM_BIT_LEN 0x7
10257 +#define PCIM_H_EA 0x3
10258 +#define PCIM_H_IA_FIX 0x4
10259 +#define PCIM_H_IA_RR 0x5
10260 +
10261 +#define PCI_ADDR_START 0x50000000
10262 +
10263 +#define CPUTOPCI_MEM_WIN 0x02000000
10264 +#define CPUTOPCI_IO_WIN 0x00100000
10265 +#define PCILBA_SIZE_SHFT 2
10266 +#define PCILBA_SIZE_MASK 0x1F
10267 +#define SIZE_256MB 0x1C
10268 +#define SIZE_128MB 0x1B
10269 +#define SIZE_64MB 0x1A
10270 +#define SIZE_32MB 0x19
10271 +#define SIZE_16MB 0x18
10272 +#define SIZE_4MB 0x16
10273 +#define SIZE_2MB 0x15
10274 +#define SIZE_1MB 0x14
10275 +#define ACACIA_CONFIG0_ADDR 0x80000000
10276 +#define ACACIA_CONFIG1_ADDR 0x80000004
10277 +#define ACACIA_CONFIG2_ADDR 0x80000008
10278 +#define ACACIA_CONFIG3_ADDR 0x8000000C
10279 +#define ACACIA_CONFIG4_ADDR 0x80000010
10280 +#define ACACIA_CONFIG5_ADDR 0x80000014
10281 +#define ACACIA_CONFIG6_ADDR 0x80000018
10282 +#define ACACIA_CONFIG7_ADDR 0x8000001C
10283 +#define ACACIA_CONFIG8_ADDR 0x80000020
10284 +#define ACACIA_CONFIG9_ADDR 0x80000024
10285 +#define ACACIA_CONFIG10_ADDR 0x80000028
10286 +#define ACACIA_CONFIG11_ADDR 0x8000002C
10287 +#define ACACIA_CONFIG12_ADDR 0x80000030
10288 +#define ACACIA_CONFIG13_ADDR 0x80000034
10289 +#define ACACIA_CONFIG14_ADDR 0x80000038
10290 +#define ACACIA_CONFIG15_ADDR 0x8000003C
10291 +#define ACACIA_CONFIG16_ADDR 0x80000040
10292 +#define ACACIA_CONFIG17_ADDR 0x80000044
10293 +#define ACACIA_CONFIG18_ADDR 0x80000048
10294 +#define ACACIA_CONFIG19_ADDR 0x8000004C
10295 +#define ACACIA_CONFIG20_ADDR 0x80000050
10296 +#define ACACIA_CONFIG21_ADDR 0x80000054
10297 +#define ACACIA_CONFIG22_ADDR 0x80000058
10298 +#define ACACIA_CONFIG23_ADDR 0x8000005C
10299 +#define ACACIA_CONFIG24_ADDR 0x80000060
10300 +#define ACACIA_CONFIG25_ADDR 0x80000064
10301 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
10302 + PCFG04_command_memena_m | \
10303 + PCFG04_command_bmena_m | \
10304 + PCFG04_command_mwinv_m | \
10305 + PCFG04_command_parena_m | \
10306 + PCFG04_command_serrena_m )
10307 +
10308 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
10309 + PCFG04_status_sta_m | \
10310 + PCFG04_status_rta_m | \
10311 + PCFG04_status_rma_m | \
10312 + PCFG04_status_sse_m | \
10313 + PCFG04_status_pe_m)
10314 +
10315 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
10316 +
10317 +#define ACACIA_REVID 0
10318 +#define ACACIA_CLASS_CODE 0
10319 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
10320 + ACACIA_REVID)
10321 +
10322 +#define ACACIA_CACHE_LINE_SIZE 4
10323 +#define ACACIA_MASTER_LAT 0x3c
10324 +#define ACACIA_HEADER_TYPE 0
10325 +#define ACACIA_BIST 0
10326 +
10327 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10328 + (ACACIA_HEADER_TYPE<<16) | \
10329 + (ACACIA_MASTER_LAT<<8) | \
10330 + ACACIA_CACHE_LINE_SIZE )
10331 +
10332 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
10333 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
10334 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
10335 + internal Registers */
10336 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
10337 +
10338 +#define ACACIA_CNFG4 ACACIA_BAR0
10339 +#define ACACIA_CNFG5 ACACIA_BAR1
10340 +#define ACACIA_CNFG6 ACACIA_BAR2
10341 +#define ACACIA_CNFG7 ACACIA_BAR3
10342 +
10343 +#define ACACIA_SUBSYS_VENDOR_ID 0
10344 +#define ACACIA_SUBSYSTEM_ID 0
10345 +#define ACACIA_CNFG8 0
10346 +#define ACACIA_CNFG9 0
10347 +#define ACACIA_CNFG10 0
10348 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10349 + ACACIA_SUBSYSTEM_ID)
10350 +#define ACACIA_INT_LINE 1
10351 +#define ACACIA_INT_PIN 1
10352 +#define ACACIA_MIN_GNT 8
10353 +#define ACACIA_MAX_LAT 0x38
10354 +#define ACACIA_CNFG12 0
10355 +#define ACACIA_CNFG13 0
10356 +#define ACACIA_CNFG14 0
10357 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
10358 + (ACACIA_MIN_GNT<<16) | \
10359 + (ACACIA_INT_PIN<<8) | \
10360 + ACACIA_INT_LINE)
10361 +#define ACACIA_RETRY_LIMIT 0x80
10362 +#define ACACIA_TRDY_LIMIT 0x80
10363 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10364 + ACACIA_TRDY_LIMIT)
10365 +#define PCI_PBAxC_R 0x0
10366 +#define PCI_PBAxC_RL 0x1
10367 +#define PCI_PBAxC_RM 0x2
10368 +#define SIZE_SHFT 2
10369 +
10370 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10371 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10372 + PCIPBAC_pp_m | \
10373 + (SIZE_128MB<<SIZE_SHFT) | \
10374 + PCIPBAC_p_m)
10375 +
10376 +#define ACACIA_CNFG17 ACACIA_PBA0C
10377 +#define ACACIA_PBA0M 0x0
10378 +#define ACACIA_CNFG18 ACACIA_PBA0M
10379 +
10380 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10381 + PCIPBAC_msi_m)
10382 +
10383 +#define ACACIA_CNFG19 ACACIA_PBA1C
10384 +#define ACACIA_PBA1M 0x0
10385 +#define ACACIA_CNFG20 ACACIA_PBA1M
10386 +
10387 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10388 + PCIPBAC_msi_m)
10389 +
10390 +#define ACACIA_CNFG21 ACACIA_PBA2C
10391 +#define ACACIA_PBA2M 0x18000000
10392 +#define ACACIA_CNFG22 ACACIA_PBA2M
10393 +#define ACACIA_PBA3C 0
10394 +#define ACACIA_CNFG23 ACACIA_PBA3C
10395 +#define ACACIA_PBA3M 0
10396 +#define ACACIA_CNFG24 ACACIA_PBA3M
10397 +
10398 +
10399 +
10400 +#define PCITC_DTIMER_VAL 8
10401 +#define PCITC_RTIMER_VAL 0x10
10402 +
10403 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10404 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
10405 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-06-18 12:44:28.000000000 +0200
10406 @@ -0,0 +1,91 @@
10407 +/**************************************************************************
10408 + *
10409 + * BRIEF MODULE DESCRIPTION
10410 + * Timer register definition IDT RC32438 CPU.
10411 + *
10412 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10413 + *
10414 + * This program is free software; you can redistribute it and/or modify it
10415 + * under the terms of the GNU General Public License as published by the
10416 + * Free Software Foundation; either version 2 of the License, or (at your
10417 + * option) any later version.
10418 + *
10419 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10420 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10421 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10422 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10423 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10424 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10425 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10426 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10427 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10428 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10429 + *
10430 + * You should have received a copy of the GNU General Public License along
10431 + * with this program; if not, write to the Free Software Foundation, Inc.,
10432 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10433 + *
10434 + *
10435 + **************************************************************************
10436 + * May 2004 P. Sadik.
10437 + *
10438 + * Initial Release
10439 + *
10440 + *
10441 + *
10442 + **************************************************************************
10443 + */
10444 +
10445 +#ifndef __IDT_RC32438_TIM_H__
10446 +#define __IDT_RC32438_TIM_H__
10447 +
10448 +enum
10449 +{
10450 + TIM0_PhysicalAddress = 0x18028000,
10451 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
10452 +
10453 + TIM0_VirtualAddress = 0xb8028000,
10454 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
10455 +} ;
10456 +
10457 +enum
10458 +{
10459 + TIM_Count = 3,
10460 +} ;
10461 +
10462 +struct TIM_CNTR_s
10463 +{
10464 + u32 count ;
10465 + u32 compare ;
10466 + u32 ctc ; //use CTC_
10467 +} ;
10468 +
10469 +typedef struct TIM_s
10470 +{
10471 + struct TIM_CNTR_s tim [TIM_Count] ;
10472 + u32 rcount ; //use RCOUNT_
10473 + u32 rcompare ; //use RCOMPARE_
10474 + u32 rtc ; //use RTC_
10475 +} volatile * TIM_t ;
10476 +
10477 +enum
10478 +{
10479 + CTC_en_b = 0,
10480 + CTC_en_m = 0x00000001,
10481 + CTC_to_b = 1,
10482 + CTC_to_m = 0x00000002,
10483 +
10484 + RCOUNT_count_b = 0,
10485 + RCOUNT_count_m = 0x0000ffff,
10486 + RCOMPARE_compare_b = 0,
10487 + RCOMPARE_compare_m = 0x0000ffff,
10488 + RTC_ce_b = 0,
10489 + RTC_ce_m = 0x00000001,
10490 + RTC_to_b = 1,
10491 + RTC_to_m = 0x00000002,
10492 + RTC_rqe_b = 2,
10493 + RTC_rqe_m = 0x00000004,
10494 +
10495 +} ;
10496 +#endif //__IDT_RC32438_TIM_H__
10497 +
10498 diff -Nur linux-2.6.17/include/asm-mips/mach-generic/irq.h linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h
10499 --- linux-2.6.17/include/asm-mips/mach-generic/irq.h 2006-06-18 03:49:35.000000000 +0200
10500 +++ linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h 2006-06-18 12:44:28.000000000 +0200
10501 @@ -8,6 +8,6 @@
10502 #ifndef __ASM_MACH_GENERIC_IRQ_H
10503 #define __ASM_MACH_GENERIC_IRQ_H
10504
10505 -#define NR_IRQS 128
10506 +#define NR_IRQS 256
10507
10508 #endif /* __ASM_MACH_GENERIC_IRQ_H */
10509 diff -Nur linux-2.6.17/include/linux/kernel.h linux-2.6.17-owrt/include/linux/kernel.h
10510 --- linux-2.6.17/include/linux/kernel.h 2006-06-18 03:49:35.000000000 +0200
10511 +++ linux-2.6.17-owrt/include/linux/kernel.h 2006-06-18 12:44:28.000000000 +0200
10512 @@ -329,6 +329,7 @@
10513 };
10514
10515 /* Force a compilation error if condition is true */
10516 +extern void BUILD_BUG(void);
10517 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10518
10519 /* Trap pasters of __FUNCTION__ at compile-time */
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