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remove early_initcall hacks
[openwrt/openwrt.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.16/arch/mips/aruba/Makefile linux-2.6.16-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.16/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16-owrt/arch/mips/aruba/Makefile 2006-03-20 14:25:10.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/Makefile linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.16/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile 2006-03-20 14:25:10.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.c linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c 2006-03-20 14:25:10.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.h linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h 2006-03-20 14:25:10.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.16/arch/mips/aruba/prom.c linux-2.6.16-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.16/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.16-owrt/arch/mips/aruba/prom.c 2006-03-20 14:25:10.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.16/arch/mips/aruba/serial.c linux-2.6.16-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.16/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.16-owrt/arch/mips/aruba/serial.c 2006-03-20 14:25:10.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.16/arch/mips/aruba/setup.c linux-2.6.16-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.16/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.16-owrt/arch/mips/aruba/setup.c 2006-03-20 14:30:00.000000000 +0100
786 @@ -0,0 +1,125 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + return "MIPS IDT32434 - ARUBA";
909 +}
910 +
911 +EXPORT_SYMBOL(get_system_type);
912 diff -Nur linux-2.6.16/arch/mips/aruba/time.c linux-2.6.16-owrt/arch/mips/aruba/time.c
913 --- linux-2.6.16/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
914 +++ linux-2.6.16-owrt/arch/mips/aruba/time.c 2006-03-20 14:25:10.000000000 +0100
915 @@ -0,0 +1,108 @@
916 +/**************************************************************************
917 + *
918 + * BRIEF MODULE DESCRIPTION
919 + * timer routines for IDT EB434 boards
920 + *
921 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
922 + *
923 + * This program is free software; you can redistribute it and/or modify it
924 + * under the terms of the GNU General Public License as published by the
925 + * Free Software Foundation; either version 2 of the License, or (at your
926 + * option) any later version.
927 + *
928 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
929 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
930 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
931 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
932 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
933 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
934 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
935 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
936 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
937 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
938 + *
939 + * You should have received a copy of the GNU General Public License along
940 + * with this program; if not, write to the Free Software Foundation, Inc.,
941 + * 675 Mass Ave, Cambridge, MA 02139, USA.
942 + *
943 + *
944 + **************************************************************************
945 + * May 2004 rkt, neb
946 + *
947 + * Initial Release
948 + *
949 + *
950 + *
951 + **************************************************************************
952 + */
953 +
954 +#include <linux/config.h>
955 +#include <linux/init.h>
956 +#include <linux/kernel_stat.h>
957 +#include <linux/sched.h>
958 +#include <linux/spinlock.h>
959 +#include <linux/mc146818rtc.h>
960 +#include <linux/irq.h>
961 +#include <linux/timex.h>
962 +
963 +#include <linux/param.h>
964 +#include <asm/mipsregs.h>
965 +#include <asm/ptrace.h>
966 +#include <asm/time.h>
967 +#include <asm/hardirq.h>
968 +
969 +#include <asm/mipsregs.h>
970 +#include <asm/ptrace.h>
971 +#include <asm/debug.h>
972 +#include <asm/time.h>
973 +
974 +#include <asm/idt-boards/rc32434/rc32434.h>
975 +
976 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
977 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
978 +
979 +extern unsigned int idt_cpu_freq;
980 +
981 +static unsigned long __init cal_r4koff(void)
982 +{
983 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
984 + return (mips_hpt_frequency / HZ);
985 +}
986 +
987 +void __init aruba_time_init(void)
988 +{
989 + unsigned int est_freq, flags;
990 + local_irq_save(flags);
991 +
992 + printk("calculating r4koff... ");
993 + r4k_offset = cal_r4koff();
994 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
995 +
996 + est_freq = 2 * r4k_offset * HZ;
997 + est_freq += 5000; /* round */
998 + est_freq -= est_freq % 10000;
999 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1000 + (est_freq % 1000000) * 100 / 1000000);
1001 + local_irq_restore(flags);
1002 +
1003 +}
1004 +
1005 +void __init aruba_timer_setup(struct irqaction *irq)
1006 +{
1007 + /* we are using the cpu counter for timer interrupts */
1008 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1009 +
1010 + /* to generate the first timer interrupt */
1011 + r4k_cur = (read_c0_count() + r4k_offset);
1012 + write_c0_compare(r4k_cur);
1013 +
1014 +}
1015 +
1016 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1017 +{
1018 + irq_enter();
1019 + kstat_this_cpu.irqs[irq]++;
1020 +
1021 + timer_interrupt(irq, NULL, regs);
1022 + irq_exit();
1023 +}
1024 diff -Nur linux-2.6.16/arch/mips/Kconfig linux-2.6.16-owrt/arch/mips/Kconfig
1025 --- linux-2.6.16/arch/mips/Kconfig 2006-03-20 06:53:29.000000000 +0100
1026 +++ linux-2.6.16-owrt/arch/mips/Kconfig 2006-03-20 14:25:10.000000000 +0100
1027 @@ -227,6 +227,17 @@
1028 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1029 a kernel for this platform.
1030
1031 +config MACH_ARUBA
1032 + bool "Support for the ARUBA product line"
1033 + select DMA_NONCOHERENT
1034 + select CPU_HAS_PREFETCH
1035 + select HW_HAS_PCI
1036 + select SWAP_IO_SPACE
1037 + select SYS_SUPPORTS_32BIT_KERNEL
1038 + select SYS_HAS_CPU_MIPS32_R1
1039 + select SYS_SUPPORTS_BIG_ENDIAN
1040 +
1041 +
1042 config MACH_JAZZ
1043 bool "Support for the Jazz family of machines"
1044 select ARC
1045 diff -Nur linux-2.6.16/arch/mips/Makefile linux-2.6.16-owrt/arch/mips/Makefile
1046 --- linux-2.6.16/arch/mips/Makefile 2006-03-20 06:53:29.000000000 +0100
1047 +++ linux-2.6.16-owrt/arch/mips/Makefile 2006-03-20 14:25:10.000000000 +0100
1048 @@ -279,6 +279,14 @@
1049 #
1050
1051 #
1052 +# Aruba
1053 +#
1054 +
1055 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1056 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1057 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1058 +
1059 +#
1060 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1061 #
1062 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1063 diff -Nur linux-2.6.16/arch/mips/mm/tlbex.c linux-2.6.16-owrt/arch/mips/mm/tlbex.c
1064 --- linux-2.6.16/arch/mips/mm/tlbex.c 2006-03-20 06:53:29.000000000 +0100
1065 +++ linux-2.6.16-owrt/arch/mips/mm/tlbex.c 2006-03-20 14:25:10.000000000 +0100
1066 @@ -852,7 +852,6 @@
1067
1068 case CPU_R10000:
1069 case CPU_R12000:
1070 - case CPU_4KC:
1071 case CPU_SB1:
1072 case CPU_SB1A:
1073 case CPU_4KSC:
1074 @@ -880,6 +879,7 @@
1075 tlbw(p);
1076 break;
1077
1078 + case CPU_4KC:
1079 case CPU_4KEC:
1080 case CPU_24K:
1081 case CPU_34K:
1082 diff -Nur linux-2.6.16/drivers/net/Kconfig linux-2.6.16-owrt/drivers/net/Kconfig
1083 --- linux-2.6.16/drivers/net/Kconfig 2006-03-20 06:53:29.000000000 +0100
1084 +++ linux-2.6.16-owrt/drivers/net/Kconfig 2006-03-20 14:25:10.000000000 +0100
1085 @@ -187,6 +187,13 @@
1086
1087 source "drivers/net/arm/Kconfig"
1088
1089 +config IDT_RC32434_ETH
1090 + tristate "IDT RC32434 Local Ethernet support"
1091 + depends on NET_ETHERNET
1092 + help
1093 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1094 + To compile this driver as a module, choose M here.
1095 +
1096 config MACE
1097 tristate "MACE (Power Mac ethernet) support"
1098 depends on NET_ETHERNET && PPC_PMAC && PPC32
1099 diff -Nur linux-2.6.16/drivers/net/Makefile linux-2.6.16-owrt/drivers/net/Makefile
1100 --- linux-2.6.16/drivers/net/Makefile 2006-03-20 06:53:29.000000000 +0100
1101 +++ linux-2.6.16-owrt/drivers/net/Makefile 2006-03-20 14:25:10.000000000 +0100
1102 @@ -38,6 +38,7 @@
1103
1104 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1105
1106 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1107 obj-$(CONFIG_DGRS) += dgrs.o
1108 obj-$(CONFIG_VORTEX) += 3c59x.o
1109 obj-$(CONFIG_TYPHOON) += typhoon.o
1110 diff -Nur linux-2.6.16/drivers/net/natsemi.c linux-2.6.16-owrt/drivers/net/natsemi.c
1111 --- linux-2.6.16/drivers/net/natsemi.c 2006-03-20 06:53:29.000000000 +0100
1112 +++ linux-2.6.16-owrt/drivers/net/natsemi.c 2006-03-20 14:25:10.000000000 +0100
1113 @@ -771,6 +771,49 @@
1114 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1115 static struct ethtool_ops ethtool_ops;
1116
1117 +#ifdef CONFIG_MACH_ARUBA
1118 +
1119 +#include <linux/ctype.h>
1120 +
1121 +#ifndef ERR
1122 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1123 +#endif
1124 +
1125 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1126 +{
1127 + int i, j;
1128 + unsigned char result, value;
1129 +
1130 + for (i=0; i<6; i++) {
1131 + result = 0;
1132 + if (i != 5 && *(macstr+2) != ':') {
1133 + ERR("invalid mac address format: %d %c\n",
1134 + i, *(macstr+2));
1135 + return -EINVAL;
1136 + }
1137 + for (j=0; j<2; j++) {
1138 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1139 + toupper(*macstr)-'A'+10) < 16) {
1140 + result = result*16 + value;
1141 + macstr++;
1142 + }
1143 + else {
1144 + ERR("invalid mac address "
1145 + "character: %c\n", *macstr);
1146 + return -EINVAL;
1147 + }
1148 + }
1149 +
1150 + macstr++;
1151 + dev->dev_addr[i] = result;
1152 + }
1153 +
1154 + dev->dev_addr[5]++;
1155 + return 0;
1156 +}
1157 +
1158 +#endif
1159 +
1160 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1161 {
1162 return (void __iomem *) dev->base_addr;
1163 @@ -859,6 +902,7 @@
1164 goto err_ioremap;
1165 }
1166
1167 +#ifndef CONFIG_MACH_ARUBA
1168 /* Work around the dropped serial bit. */
1169 prev_eedata = eeprom_read(ioaddr, 6);
1170 for (i = 0; i < 3; i++) {
1171 @@ -867,6 +911,19 @@
1172 dev->dev_addr[i*2+1] = eedata >> 7;
1173 prev_eedata = eedata;
1174 }
1175 +#else
1176 + {
1177 + char mac[32];
1178 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1179 + extern char *getenv(char *e);
1180 + memset(mac, 0, 32);
1181 + memcpy(mac, getenv("ethaddr"), 17);
1182 + if (parse_mac_addr(dev, mac)){
1183 + printk("%s: MAC address not found\n", __func__);
1184 + memcpy(dev->dev_addr, def_mac, 6);
1185 + }
1186 + }
1187 +#endif
1188
1189 dev->base_addr = (unsigned long __force) ioaddr;
1190 dev->irq = irq;
1191 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.c linux-2.6.16-owrt/drivers/net/rc32434_eth.c
1192 --- linux-2.6.16/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1193 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.c 2006-03-20 14:25:10.000000000 +0100
1194 @@ -0,0 +1,1268 @@
1195 +/**************************************************************************
1196 + *
1197 + * BRIEF MODULE DESCRIPTION
1198 + * Driver for the IDT RC32434 on-chip ethernet controller.
1199 + *
1200 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1201 + *
1202 + * This program is free software; you can redistribute it and/or modify it
1203 + * under the terms of the GNU General Public License as published by the
1204 + * Free Software Foundation; either version 2 of the License, or (at your
1205 + * option) any later version.
1206 + *
1207 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1208 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1209 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1210 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1211 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1212 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1213 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1214 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1215 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1216 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1217 + *
1218 + * You should have received a copy of the GNU General Public License along
1219 + * with this program; if not, write to the Free Software Foundation, Inc.,
1220 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1221 + *
1222 + *
1223 + **************************************************************************
1224 + * May 2004 rkt, neb
1225 + *
1226 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1227 + *
1228 + * Aug 2004 Sadik
1229 + *
1230 + * Added NAPI
1231 + *
1232 + **************************************************************************
1233 + */
1234 +
1235 +#include <linux/config.h>
1236 +#include <linux/module.h>
1237 +#include <linux/kernel.h>
1238 +#include <linux/moduleparam.h>
1239 +#include <linux/sched.h>
1240 +#include <linux/ctype.h>
1241 +#include <linux/types.h>
1242 +#include <linux/fcntl.h>
1243 +#include <linux/interrupt.h>
1244 +#include <linux/ptrace.h>
1245 +#include <linux/init.h>
1246 +#include <linux/ioport.h>
1247 +#include <linux/proc_fs.h>
1248 +#include <linux/in.h>
1249 +#include <linux/slab.h>
1250 +#include <linux/string.h>
1251 +#include <linux/delay.h>
1252 +#include <linux/netdevice.h>
1253 +#include <linux/etherdevice.h>
1254 +#include <linux/skbuff.h>
1255 +#include <linux/errno.h>
1256 +#include <asm/bootinfo.h>
1257 +#include <asm/system.h>
1258 +#include <asm/bitops.h>
1259 +#include <asm/pgtable.h>
1260 +#include <asm/segment.h>
1261 +#include <asm/io.h>
1262 +#include <asm/dma.h>
1263 +
1264 +#include "rc32434_eth.h"
1265 +
1266 +#define DRIVER_VERSION "(mar2904)"
1267 +
1268 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1269 +
1270 +
1271 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1272 + ((dev)->dev_addr[1]))
1273 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1274 + ((dev)->dev_addr[3] << 16) | \
1275 + ((dev)->dev_addr[4] << 8) | \
1276 + ((dev)->dev_addr[5]))
1277 +
1278 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1279 +static char mac0[18] = "08:00:06:05:40:01";
1280 +
1281 +MODULE_PARM(mac0, "c18");
1282 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1283 +
1284 +static struct rc32434_if_t {
1285 + char *name;
1286 + struct net_device *dev;
1287 + char* mac_str;
1288 + int weight;
1289 + u32 iobase;
1290 + u32 rxdmabase;
1291 + u32 txdmabase;
1292 + int rx_dma_irq;
1293 + int tx_dma_irq;
1294 + int rx_ovr_irq;
1295 + int tx_und_irq;
1296 +} rc32434_iflist[] =
1297 +{
1298 + {
1299 + "rc32434_eth0", NULL, mac0,
1300 + 64,
1301 + ETH0_PhysicalAddress,
1302 + ETH0_RX_DMA_ADDR,
1303 + ETH0_TX_DMA_ADDR,
1304 + ETH0_DMA_RX_IRQ,
1305 + ETH0_DMA_TX_IRQ,
1306 + ETH0_RX_OVR_IRQ,
1307 + ETH0_TX_UND_IRQ
1308 + }
1309 +};
1310 +
1311 +
1312 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1313 +{
1314 + int i, j;
1315 + unsigned char result, value;
1316 +
1317 + for (i=0; i<6; i++) {
1318 + result = 0;
1319 + if (i != 5 && *(macstr+2) != ':') {
1320 + ERR("invalid mac address format: %d %c\n",
1321 + i, *(macstr+2));
1322 + return -EINVAL;
1323 + }
1324 + for (j=0; j<2; j++) {
1325 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1326 + toupper(*macstr)-'A'+10) < 16) {
1327 + result = result*16 + value;
1328 + macstr++;
1329 + }
1330 + else {
1331 + ERR("invalid mac address "
1332 + "character: %c\n", *macstr);
1333 + return -EINVAL;
1334 + }
1335 + }
1336 +
1337 + macstr++;
1338 + dev->dev_addr[i] = result;
1339 + }
1340 +
1341 + return 0;
1342 +}
1343 +
1344 +
1345 +
1346 +static inline void rc32434_abort_tx(struct net_device *dev)
1347 +{
1348 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1349 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1350 +
1351 +}
1352 +
1353 +static inline void rc32434_abort_rx(struct net_device *dev)
1354 +{
1355 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1356 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1357 +
1358 +}
1359 +
1360 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1361 +{
1362 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1363 +}
1364 +
1365 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1366 +{
1367 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1368 +}
1369 +
1370 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1371 +{
1372 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1373 +}
1374 +
1375 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1376 +{
1377 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1378 +}
1379 +
1380 +#ifdef RC32434_PROC_DEBUG
1381 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1382 + int length, int *eof, void *data)
1383 +{
1384 + struct net_device *dev = (struct net_device *)data;
1385 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1386 + int len = 0;
1387 +
1388 + /* print out header */
1389 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1390 + len += sprintf (buf + len,
1391 + "DMA halt count = %10d, DMA run count = %10d\n",
1392 + lp->dma_halt_cnt, lp->dma_run_cnt);
1393 +
1394 + if (fpos >= len) {
1395 + *start = buf;
1396 + *eof = 1;
1397 + return 0;
1398 + }
1399 + *start = buf + fpos;
1400 +
1401 + if ((len -= fpos) > length)
1402 + return length;
1403 + *eof = 1;
1404 +
1405 + return len;
1406 +
1407 +}
1408 +#endif
1409 +
1410 +
1411 +/*
1412 + * Restart the RC32434 ethernet controller.
1413 + */
1414 +static int rc32434_restart(struct net_device *dev)
1415 +{
1416 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1417 +
1418 + /*
1419 + * Disable interrupts
1420 + */
1421 + disable_irq(lp->rx_irq);
1422 + disable_irq(lp->tx_irq);
1423 +#ifdef RC32434_REVISION
1424 + disable_irq(lp->ovr_irq);
1425 +#endif
1426 + disable_irq(lp->und_irq);
1427 +
1428 + /* Mask F E bit in Tx DMA */
1429 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1430 + /* Mask D H E bit in Rx DMA */
1431 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1432 +
1433 + rc32434_init(dev);
1434 + rc32434_multicast_list(dev);
1435 +
1436 + enable_irq(lp->und_irq);
1437 +#ifdef RC32434_REVISION
1438 + enable_irq(lp->ovr_irq);
1439 +#endif
1440 + enable_irq(lp->tx_irq);
1441 + enable_irq(lp->rx_irq);
1442 +
1443 + return 0;
1444 +}
1445 +
1446 +int rc32434_init_module(void)
1447 +{
1448 +#ifdef CONFIG_MACH_ARUBA
1449 + if (mips_machtype != MACH_ARUBA_AP70)
1450 + return 1;
1451 +#endif
1452 +
1453 + printk(KERN_INFO DRIVER_NAME " \n");
1454 + return rc32434_probe(0);
1455 +}
1456 +
1457 +static int rc32434_probe(int port_num)
1458 +{
1459 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1460 + struct rc32434_local *lp = NULL;
1461 + struct net_device *dev = NULL;
1462 + int i, retval,err;
1463 +
1464 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1465 + if(!dev) {
1466 + ERR("rc32434_eth: alloc_etherdev failed\n");
1467 + return -1;
1468 + }
1469 +
1470 + SET_MODULE_OWNER(dev);
1471 + bif->dev = dev;
1472 +
1473 +#ifdef CONFIG_MACH_ARUBA
1474 + {
1475 + extern char * getenv(char *e);
1476 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1477 + }
1478 +#endif
1479 +
1480 + printk("mac: %s\n", bif->mac_str);
1481 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1482 + ERR("MAC address parse failed\n");
1483 + free_netdev(dev);
1484 + return -1;
1485 + }
1486 +
1487 +
1488 + /* Initialize the device structure. */
1489 + if (dev->priv == NULL) {
1490 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1491 + memset(lp, 0, sizeof(struct rc32434_local));
1492 + }
1493 + else {
1494 + lp = (struct rc32434_local *)dev->priv;
1495 + }
1496 +
1497 + lp->rx_irq = bif->rx_dma_irq;
1498 + lp->tx_irq = bif->tx_dma_irq;
1499 + lp->ovr_irq = bif->rx_ovr_irq;
1500 + lp->und_irq = bif->tx_und_irq;
1501 +
1502 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1503 +
1504 + if (!lp->eth_regs) {
1505 + ERR("Can't remap eth registers\n");
1506 + retval = -ENXIO;
1507 + goto probe_err_out;
1508 + }
1509 +
1510 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1511 +
1512 + if (!lp->rx_dma_regs) {
1513 + ERR("Can't remap Rx DMA registers\n");
1514 + retval = -ENXIO;
1515 + goto probe_err_out;
1516 + }
1517 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1518 +
1519 + if (!lp->tx_dma_regs) {
1520 + ERR("Can't remap Tx DMA registers\n");
1521 + retval = -ENXIO;
1522 + goto probe_err_out;
1523 + }
1524 +
1525 +#ifdef RC32434_PROC_DEBUG
1526 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1527 + rc32434_read_proc, dev);
1528 +#endif
1529 +
1530 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1531 + if (!lp->td_ring) {
1532 + ERR("Can't allocate descriptors\n");
1533 + retval = -ENOMEM;
1534 + goto probe_err_out;
1535 + }
1536 +
1537 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1538 +
1539 + /* now convert TD_RING pointer to KSEG1 */
1540 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1541 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1542 +
1543 +
1544 + spin_lock_init(&lp->lock);
1545 +
1546 + dev->base_addr = bif->iobase;
1547 + /* just use the rx dma irq */
1548 + dev->irq = bif->rx_dma_irq;
1549 +
1550 + dev->priv = lp;
1551 +
1552 + dev->open = rc32434_open;
1553 + dev->stop = rc32434_close;
1554 + dev->hard_start_xmit = rc32434_send_packet;
1555 + dev->get_stats = rc32434_get_stats;
1556 + dev->set_multicast_list = &rc32434_multicast_list;
1557 + dev->tx_timeout = rc32434_tx_timeout;
1558 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1559 +
1560 +#ifdef CONFIG_IDT_USE_NAPI
1561 + dev->poll = rc32434_poll;
1562 + dev->weight = bif->weight;
1563 + printk("Using NAPI with weight %d\n",dev->weight);
1564 +#else
1565 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1566 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1567 +#endif
1568 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1569 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1570 +
1571 + if ((err = register_netdev(dev))) {
1572 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1573 + free_netdev(dev);
1574 + retval = -EINVAL;
1575 + goto probe_err_out;
1576 + }
1577 +
1578 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1579 + for (i = 0; i < 6; i++) {
1580 + printk("%2.2x", dev->dev_addr[i]);
1581 + if (i<5)
1582 + printk(":");
1583 + }
1584 + printk("\n");
1585 +
1586 + return 0;
1587 +
1588 + probe_err_out:
1589 + rc32434_cleanup_module();
1590 + ERR(" failed. Returns %d\n", retval);
1591 + return retval;
1592 +
1593 +}
1594 +
1595 +
1596 +static void rc32434_cleanup_module(void)
1597 +{
1598 + int i;
1599 +
1600 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1601 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1602 + if (bif->dev != NULL) {
1603 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1604 + if (lp != NULL) {
1605 + if (lp->eth_regs)
1606 + iounmap((void*)lp->eth_regs);
1607 + if (lp->rx_dma_regs)
1608 + iounmap((void*)lp->rx_dma_regs);
1609 + if (lp->tx_dma_regs)
1610 + iounmap((void*)lp->tx_dma_regs);
1611 + if (lp->td_ring)
1612 + kfree((void*)KSEG0ADDR(lp->td_ring));
1613 +
1614 +#ifdef RC32434_PROC_DEBUG
1615 + if (lp->ps) {
1616 + remove_proc_entry(bif->name, proc_net);
1617 + }
1618 +#endif
1619 + kfree(lp);
1620 + }
1621 +
1622 + unregister_netdev(bif->dev);
1623 + free_netdev(bif->dev);
1624 + kfree(bif->dev);
1625 + }
1626 + }
1627 +}
1628 +
1629 +
1630 +
1631 +static int rc32434_open(struct net_device *dev)
1632 +{
1633 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1634 +
1635 + /* Initialize */
1636 + if (rc32434_init(dev)) {
1637 + ERR("Error: cannot open the Ethernet device\n");
1638 + return -EAGAIN;
1639 + }
1640 +
1641 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1642 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1643 + SA_SHIRQ | SA_INTERRUPT,
1644 + "rc32434 ethernet Rx", dev)) {
1645 + ERR(": unable to get Rx DMA IRQ %d\n",
1646 + lp->rx_irq);
1647 + return -EAGAIN;
1648 + }
1649 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1650 + SA_SHIRQ | SA_INTERRUPT,
1651 + "rc32434 ethernet Tx", dev)) {
1652 + ERR(": unable to get Tx DMA IRQ %d\n",
1653 + lp->tx_irq);
1654 + free_irq(lp->rx_irq, dev);
1655 + return -EAGAIN;
1656 + }
1657 +
1658 +#ifdef RC32434_REVISION
1659 + /* Install handler for overrun error. */
1660 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1661 + SA_SHIRQ | SA_INTERRUPT,
1662 + "Ethernet Overflow", dev)) {
1663 + ERR(": unable to get OVR IRQ %d\n",
1664 + lp->ovr_irq);
1665 + free_irq(lp->rx_irq, dev);
1666 + free_irq(lp->tx_irq, dev);
1667 + return -EAGAIN;
1668 + }
1669 +#endif
1670 +
1671 + /* Install handler for underflow error. */
1672 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1673 + SA_SHIRQ | SA_INTERRUPT,
1674 + "Ethernet Underflow", dev)) {
1675 + ERR(": unable to get UND IRQ %d\n",
1676 + lp->und_irq);
1677 + free_irq(lp->rx_irq, dev);
1678 + free_irq(lp->tx_irq, dev);
1679 +#ifdef RC32434_REVISION
1680 + free_irq(lp->ovr_irq, dev);
1681 +#endif
1682 + return -EAGAIN;
1683 + }
1684 +
1685 +
1686 + return 0;
1687 +}
1688 +
1689 +
1690 +
1691 +
1692 +static int rc32434_close(struct net_device *dev)
1693 +{
1694 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1695 + u32 tmp;
1696 +
1697 + /* Disable interrupts */
1698 + disable_irq(lp->rx_irq);
1699 + disable_irq(lp->tx_irq);
1700 +#ifdef RC32434_REVISION
1701 + disable_irq(lp->ovr_irq);
1702 +#endif
1703 + disable_irq(lp->und_irq);
1704 +
1705 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1706 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1707 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1708 +
1709 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1710 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1711 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1712 +
1713 + free_irq(lp->rx_irq, dev);
1714 + free_irq(lp->tx_irq, dev);
1715 +#ifdef RC32434_REVISION
1716 + free_irq(lp->ovr_irq, dev);
1717 +#endif
1718 + free_irq(lp->und_irq, dev);
1719 + return 0;
1720 +}
1721 +
1722 +
1723 +/* transmit packet */
1724 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1725 +{
1726 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1727 + unsigned long flags;
1728 + u32 length;
1729 + DMAD_t td;
1730 +
1731 +
1732 + spin_lock_irqsave(&lp->lock, flags);
1733 +
1734 + td = &lp->td_ring[lp->tx_chain_tail];
1735 +
1736 + /* stop queue when full, drop pkts if queue already full */
1737 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1738 + lp->tx_full = 1;
1739 +
1740 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1741 + netif_stop_queue(dev);
1742 + }
1743 + else {
1744 + lp->stats.tx_dropped++;
1745 + dev_kfree_skb_any(skb);
1746 + spin_unlock_irqrestore(&lp->lock, flags);
1747 + return 1;
1748 + }
1749 + }
1750 +
1751 + lp->tx_count ++;
1752 +
1753 + lp->tx_skb[lp->tx_chain_tail] = skb;
1754 +
1755 + length = skb->len;
1756 +
1757 + /* Setup the transmit descriptor. */
1758 + td->ca = CPHYSADDR(skb->data);
1759 +
1760 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1761 + if( lp->tx_chain_status == empty ) {
1762 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1763 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1764 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1765 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1766 + }
1767 + else {
1768 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1769 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1770 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1771 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1772 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1773 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1774 + lp->tx_chain_status = empty;
1775 + }
1776 + }
1777 + else {
1778 + if( lp->tx_chain_status == empty ) {
1779 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1780 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1781 + lp->tx_chain_status = filled;
1782 + }
1783 + else {
1784 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1785 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1786 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1787 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1788 + }
1789 + }
1790 +
1791 + dev->trans_start = jiffies;
1792 +
1793 + spin_unlock_irqrestore(&lp->lock, flags);
1794 +
1795 + return 0;
1796 +}
1797 +
1798 +
1799 +/* Ethernet MII-PHY Handler */
1800 +static void rc32434_mii_handler(unsigned long data)
1801 +{
1802 + struct net_device *dev = (struct net_device *)data;
1803 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1804 + unsigned long flags;
1805 + unsigned long duplex_status;
1806 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1807 +
1808 + spin_lock_irqsave(&lp->lock, flags);
1809 +
1810 + /* Two ports are using the same MII, the difference is the PHY address */
1811 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1812 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1813 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1814 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1815 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1816 +
1817 + ERR("irq:%x port_addr:%x RDD:%x\n",
1818 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1819 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1820 + if(duplex_status != lp->duplex_mode) {
1821 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1822 + lp->duplex_mode = duplex_status;
1823 + rc32434_restart(dev);
1824 + }
1825 +
1826 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1827 + add_timer(&lp->mii_phy_timer);
1828 +
1829 + spin_unlock_irqrestore(&lp->lock, flags);
1830 +
1831 +}
1832 +
1833 +#ifdef RC32434_REVISION
1834 +/* Ethernet Rx Overflow interrupt */
1835 +static irqreturn_t
1836 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1837 +{
1838 + struct net_device *dev = (struct net_device *)dev_id;
1839 + struct rc32434_local *lp;
1840 + unsigned int ovr;
1841 + irqreturn_t retval = IRQ_NONE;
1842 +
1843 + ASSERT(dev != NULL);
1844 +
1845 + lp = (struct rc32434_local *)dev->priv;
1846 + spin_lock(&lp->lock);
1847 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1848 +
1849 + if(ovr & ETHINTFC_ovr_m) {
1850 + netif_stop_queue(dev);
1851 +
1852 + /* clear OVR bit */
1853 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1854 +
1855 + /* Restart interface */
1856 + rc32434_restart(dev);
1857 + retval = IRQ_HANDLED;
1858 + }
1859 + spin_unlock(&lp->lock);
1860 +
1861 + return retval;
1862 +}
1863 +
1864 +#endif
1865 +
1866 +
1867 +/* Ethernet Tx Underflow interrupt */
1868 +static irqreturn_t
1869 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1870 +{
1871 + struct net_device *dev = (struct net_device *)dev_id;
1872 + struct rc32434_local *lp;
1873 + unsigned int und;
1874 + irqreturn_t retval = IRQ_NONE;
1875 +
1876 + ASSERT(dev != NULL);
1877 +
1878 + lp = (struct rc32434_local *)dev->priv;
1879 +
1880 + spin_lock(&lp->lock);
1881 +
1882 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1883 +
1884 + if(und & ETHINTFC_und_m) {
1885 + netif_stop_queue(dev);
1886 +
1887 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1888 +
1889 + /* Restart interface */
1890 + rc32434_restart(dev);
1891 + retval = IRQ_HANDLED;
1892 + }
1893 +
1894 + spin_unlock(&lp->lock);
1895 +
1896 + return retval;
1897 +}
1898 +
1899 +
1900 +/* Ethernet Rx DMA interrupt */
1901 +static irqreturn_t
1902 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1903 +{
1904 + struct net_device *dev = (struct net_device *)dev_id;
1905 + struct rc32434_local* lp;
1906 + volatile u32 dmas,dmasm;
1907 + irqreturn_t retval;
1908 +
1909 + ASSERT(dev != NULL);
1910 +
1911 + lp = (struct rc32434_local *)dev->priv;
1912 +
1913 + spin_lock(&lp->lock);
1914 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1915 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1916 + /* Mask D H E bit in Rx DMA */
1917 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1918 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1919 +#ifdef CONFIG_IDT_USE_NAPI
1920 + if(netif_rx_schedule_prep(dev))
1921 + __netif_rx_schedule(dev);
1922 +#else
1923 + tasklet_hi_schedule(lp->rx_tasklet);
1924 +#endif
1925 +
1926 + if (dmas & DMAS_e_m)
1927 + ERR(": DMA error\n");
1928 +
1929 + retval = IRQ_HANDLED;
1930 + }
1931 + else
1932 + retval = IRQ_NONE;
1933 +
1934 + spin_unlock(&lp->lock);
1935 + return retval;
1936 +}
1937 +
1938 +#ifdef CONFIG_IDT_USE_NAPI
1939 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1940 +#else
1941 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1942 +#endif
1943 +{
1944 + struct net_device *dev = (struct net_device *)rx_data_dev;
1945 + struct rc32434_local* lp = netdev_priv(dev);
1946 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1947 + struct sk_buff *skb, *skb_new;
1948 + u8* pkt_buf;
1949 + u32 devcs, count, pkt_len, pktuncrc_len;
1950 + volatile u32 dmas;
1951 +#ifdef CONFIG_IDT_USE_NAPI
1952 + u32 received = 0;
1953 + int rx_work_limit = min(*budget,dev->quota);
1954 +#else
1955 + unsigned long flags;
1956 + spin_lock_irqsave(&lp->lock, flags);
1957 +#endif
1958 +
1959 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1960 +#ifdef CONFIG_IDT_USE_NAPI
1961 + if(--rx_work_limit <0)
1962 + {
1963 + break;
1964 + }
1965 +#endif
1966 + /* init the var. used for the later operations within the while loop */
1967 + skb_new = NULL;
1968 + devcs = rd->devcs;
1969 + pkt_len = RCVPKT_LENGTH(devcs);
1970 + skb = lp->rx_skb[lp->rx_next_done];
1971 +
1972 + if (count < 64) {
1973 + lp->stats.rx_errors++;
1974 + lp->stats.rx_dropped++;
1975 + }
1976 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1977 + /* check that this is a whole packet */
1978 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1979 + lp->stats.rx_errors++;
1980 + lp->stats.rx_dropped++;
1981 + }
1982 + else if ( (devcs & ETHRX_rok_m) ) {
1983 +
1984 + {
1985 + /* must be the (first and) last descriptor then */
1986 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1987 +
1988 + pktuncrc_len = pkt_len - 4;
1989 + /* invalidate the cache */
1990 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1991 +
1992 + /* Malloc up new buffer. */
1993 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1994 +
1995 + if (skb_new != NULL){
1996 + /* Make room */
1997 + skb_put(skb, pktuncrc_len);
1998 +
1999 + skb->protocol = eth_type_trans(skb, dev);
2000 +
2001 + /* pass the packet to upper layers */
2002 +#ifdef CONFIG_IDT_USE_NAPI
2003 + netif_receive_skb(skb);
2004 +#else
2005 + netif_rx(skb);
2006 +#endif
2007 +
2008 + dev->last_rx = jiffies;
2009 + lp->stats.rx_packets++;
2010 + lp->stats.rx_bytes += pktuncrc_len;
2011 +
2012 + if (IS_RCV_MP(devcs))
2013 + lp->stats.multicast++;
2014 +
2015 + /* 16 bit align */
2016 + skb_reserve(skb_new, 2);
2017 +
2018 + skb_new->dev = dev;
2019 + lp->rx_skb[lp->rx_next_done] = skb_new;
2020 + }
2021 + else {
2022 + ERR("no memory, dropping rx packet.\n");
2023 + lp->stats.rx_errors++;
2024 + lp->stats.rx_dropped++;
2025 + }
2026 + }
2027 +
2028 + }
2029 + else {
2030 + /* This should only happen if we enable accepting broken packets */
2031 + lp->stats.rx_errors++;
2032 + lp->stats.rx_dropped++;
2033 +
2034 + /* add statistics counters */
2035 + if (IS_RCV_CRC_ERR(devcs)) {
2036 + DBG(2, "RX CRC error\n");
2037 + lp->stats.rx_crc_errors++;
2038 + }
2039 + else if (IS_RCV_LOR_ERR(devcs)) {
2040 + DBG(2, "RX LOR error\n");
2041 + lp->stats.rx_length_errors++;
2042 + }
2043 + else if (IS_RCV_LE_ERR(devcs)) {
2044 + DBG(2, "RX LE error\n");
2045 + lp->stats.rx_length_errors++;
2046 + }
2047 + else if (IS_RCV_OVR_ERR(devcs)) {
2048 + lp->stats.rx_over_errors++;
2049 + }
2050 + else if (IS_RCV_CV_ERR(devcs)) {
2051 + /* code violation */
2052 + DBG(2, "RX CV error\n");
2053 + lp->stats.rx_frame_errors++;
2054 + }
2055 + else if (IS_RCV_CES_ERR(devcs)) {
2056 + DBG(2, "RX Preamble error\n");
2057 + }
2058 + }
2059 +
2060 + rd->devcs = 0;
2061 +
2062 + /* restore descriptor's curr_addr */
2063 + if(skb_new)
2064 + rd->ca = CPHYSADDR(skb_new->data);
2065 + else
2066 + rd->ca = CPHYSADDR(skb->data);
2067 +
2068 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2069 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2070 +
2071 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2072 + rd = &lp->rd_ring[lp->rx_next_done];
2073 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2074 + }
2075 +#ifdef CONFIG_IDT_USE_NAPI
2076 + dev->quota -= received;
2077 + *budget =- received;
2078 + if(rx_work_limit < 0)
2079 + goto not_done;
2080 +#endif
2081 +
2082 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2083 +
2084 + if(dmas & DMAS_h_m) {
2085 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2086 +#ifdef RC32434_PROC_DEBUG
2087 + lp->dma_halt_cnt++;
2088 +#endif
2089 + rd->devcs = 0;
2090 + skb = lp->rx_skb[lp->rx_next_done];
2091 + rd->ca = CPHYSADDR(skb->data);
2092 + rc32434_chain_rx(lp,rd);
2093 + }
2094 +
2095 +#ifdef CONFIG_IDT_USE_NAPI
2096 + netif_rx_complete(dev);
2097 +#endif
2098 + /* Enable D H E bit in Rx DMA */
2099 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2100 +#ifdef CONFIG_IDT_USE_NAPI
2101 + return 0;
2102 + not_done:
2103 + return 1;
2104 +#else
2105 + spin_unlock_irqrestore(&lp->lock, flags);
2106 + return;
2107 +#endif
2108 +
2109 +
2110 +}
2111 +
2112 +
2113 +
2114 +/* Ethernet Tx DMA interrupt */
2115 +static irqreturn_t
2116 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2117 +{
2118 + struct net_device *dev = (struct net_device *)dev_id;
2119 + struct rc32434_local *lp;
2120 + volatile u32 dmas,dmasm;
2121 + irqreturn_t retval;
2122 +
2123 + ASSERT(dev != NULL);
2124 +
2125 + lp = (struct rc32434_local *)dev->priv;
2126 +
2127 + spin_lock(&lp->lock);
2128 +
2129 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2130 +
2131 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2132 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2133 + /* Mask F E bit in Tx DMA */
2134 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2135 +
2136 + tasklet_hi_schedule(lp->tx_tasklet);
2137 +
2138 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2139 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2140 + lp->tx_chain_status = empty;
2141 + lp->tx_chain_head = lp->tx_chain_tail;
2142 + dev->trans_start = jiffies;
2143 + }
2144 +
2145 + if (dmas & DMAS_e_m)
2146 + ERR(": DMA error\n");
2147 +
2148 + retval = IRQ_HANDLED;
2149 + }
2150 + else
2151 + retval = IRQ_NONE;
2152 +
2153 + spin_unlock(&lp->lock);
2154 +
2155 + return retval;
2156 +}
2157 +
2158 +
2159 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2160 +{
2161 + struct net_device *dev = (struct net_device *)tx_data_dev;
2162 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2163 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2164 + u32 devcs;
2165 + unsigned long flags;
2166 + volatile u32 dmas;
2167 +
2168 + spin_lock_irqsave(&lp->lock, flags);
2169 +
2170 + /* process all desc that are done */
2171 + while(IS_DMA_FINISHED(td->control)) {
2172 + if(lp->tx_full == 1) {
2173 + netif_wake_queue(dev);
2174 + lp->tx_full = 0;
2175 + }
2176 +
2177 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2178 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2179 + lp->stats.tx_errors++;
2180 + lp->stats.tx_dropped++;
2181 +
2182 + /* should never happen */
2183 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2184 + }
2185 + else if (IS_TX_TOK(devcs)) {
2186 + lp->stats.tx_packets++;
2187 + }
2188 + else {
2189 + lp->stats.tx_errors++;
2190 + lp->stats.tx_dropped++;
2191 +
2192 + /* underflow */
2193 + if (IS_TX_UND_ERR(devcs))
2194 + lp->stats.tx_fifo_errors++;
2195 +
2196 + /* oversized frame */
2197 + if (IS_TX_OF_ERR(devcs))
2198 + lp->stats.tx_aborted_errors++;
2199 +
2200 + /* excessive deferrals */
2201 + if (IS_TX_ED_ERR(devcs))
2202 + lp->stats.tx_carrier_errors++;
2203 +
2204 + /* collisions: medium busy */
2205 + if (IS_TX_EC_ERR(devcs))
2206 + lp->stats.collisions++;
2207 +
2208 + /* late collision */
2209 + if (IS_TX_LC_ERR(devcs))
2210 + lp->stats.tx_window_errors++;
2211 +
2212 + }
2213 +
2214 + /* We must always free the original skb */
2215 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2216 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2217 + lp->tx_skb[lp->tx_next_done] = NULL;
2218 + }
2219 +
2220 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2221 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2222 + lp->td_ring[lp->tx_next_done].link = 0;
2223 + lp->td_ring[lp->tx_next_done].ca = 0;
2224 + lp->tx_count --;
2225 +
2226 + /* go on to next transmission */
2227 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2228 + td = &lp->td_ring[lp->tx_next_done];
2229 +
2230 + }
2231 +
2232 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2233 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2234 +
2235 + /* Enable F E bit in Tx DMA */
2236 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2237 + spin_unlock_irqrestore(&lp->lock, flags);
2238 +
2239 +}
2240 +
2241 +
2242 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2243 +{
2244 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2245 + return &lp->stats;
2246 +}
2247 +
2248 +
2249 +/*
2250 + * Set or clear the multicast filter for this adaptor.
2251 + */
2252 +static void rc32434_multicast_list(struct net_device *dev)
2253 +{
2254 + /* listen to broadcasts always and to treat */
2255 + /* IFF bits independantly */
2256 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2257 + unsigned long flags;
2258 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2259 +
2260 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2261 + recognise |= ETHARC_pro_m;
2262 +
2263 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2264 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2265 + else if (dev->mc_count > 0) {
2266 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2267 + recognise |= ETHARC_am_m; /* for the time being */
2268 + }
2269 +
2270 + spin_lock_irqsave(&lp->lock, flags);
2271 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2272 + spin_unlock_irqrestore(&lp->lock, flags);
2273 +}
2274 +
2275 +
2276 +static void rc32434_tx_timeout(struct net_device *dev)
2277 +{
2278 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2279 + unsigned long flags;
2280 +
2281 + spin_lock_irqsave(&lp->lock, flags);
2282 + rc32434_restart(dev);
2283 + spin_unlock_irqrestore(&lp->lock, flags);
2284 +
2285 +}
2286 +
2287 +
2288 +/*
2289 + * Initialize the RC32434 ethernet controller.
2290 + */
2291 +static int rc32434_init(struct net_device *dev)
2292 +{
2293 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2294 + int i, j;
2295 +
2296 + /* Disable DMA */
2297 + rc32434_abort_tx(dev);
2298 + rc32434_abort_rx(dev);
2299 +
2300 + /* reset ethernet logic */
2301 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2302 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2303 + dev->trans_start = jiffies;
2304 +
2305 + /* Enable Ethernet Interface */
2306 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2307 +
2308 +#ifndef CONFIG_IDT_USE_NAPI
2309 + tasklet_disable(lp->rx_tasklet);
2310 +#endif
2311 + tasklet_disable(lp->tx_tasklet);
2312 +
2313 + /* Initialize the transmit Descriptors */
2314 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2315 + lp->td_ring[i].control = DMAD_iof_m;
2316 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2317 + lp->td_ring[i].ca = 0;
2318 + lp->td_ring[i].link = 0;
2319 + if (lp->tx_skb[i] != NULL) {
2320 + dev_kfree_skb_any(lp->tx_skb[i]);
2321 + lp->tx_skb[i] = NULL;
2322 + }
2323 + }
2324 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2325 + lp-> tx_chain_status = empty;
2326 +
2327 + /*
2328 + * Initialize the receive descriptors so that they
2329 + * become a circular linked list, ie. let the last
2330 + * descriptor point to the first again.
2331 + */
2332 + for (i=0; i<RC32434_NUM_RDS; i++) {
2333 + struct sk_buff *skb = lp->rx_skb[i];
2334 +
2335 + if (lp->rx_skb[i] == NULL) {
2336 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2337 + if (skb == NULL) {
2338 + ERR("No memory in the system\n");
2339 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2340 + if (lp->rx_skb[j] != NULL)
2341 + dev_kfree_skb_any(lp->rx_skb[j]);
2342 +
2343 + return 1;
2344 + }
2345 + else {
2346 + skb->dev = dev;
2347 + skb_reserve(skb, 2);
2348 + lp->rx_skb[i] = skb;
2349 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2350 +
2351 + }
2352 + }
2353 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2354 + lp->rd_ring[i].devcs = 0;
2355 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2356 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2357 +
2358 + }
2359 + /* loop back */
2360 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2361 + lp->rx_next_done = 0;
2362 +
2363 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2364 + lp->rx_chain_head = 0;
2365 + lp->rx_chain_tail = 0;
2366 + lp->rx_chain_status = empty;
2367 +
2368 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2369 + /* Start Rx DMA */
2370 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2371 +
2372 + /* Enable F E bit in Tx DMA */
2373 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2374 + /* Enable D H E bit in Rx DMA */
2375 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2376 +
2377 + /* Accept only packets destined for this Ethernet device address */
2378 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2379 +
2380 + /* Set all Ether station address registers to their initial values */
2381 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2382 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2383 +
2384 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2385 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2386 +
2387 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2388 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2389 +
2390 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2391 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2392 +
2393 +
2394 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2395 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2396 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2397 +
2398 + /* Back to back inter-packet-gap */
2399 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2400 + /* Non - Back to back inter-packet-gap */
2401 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2402 +
2403 + /* Management Clock Prescaler Divisor */
2404 + /* Clock independent setting */
2405 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2406 + &lp->eth_regs->ethmcp);
2407 +
2408 + /* don't transmit until fifo contains 48b */
2409 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2410 +
2411 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2412 +
2413 +#ifndef CONFIG_IDT_USE_NAPI
2414 + tasklet_enable(lp->rx_tasklet);
2415 +#endif
2416 + tasklet_enable(lp->tx_tasklet);
2417 +
2418 + netif_start_queue(dev);
2419 +
2420 +
2421 + return 0;
2422 +
2423 +}
2424 +
2425 +
2426 +#ifndef MODULE
2427 +
2428 +static int __init rc32434_setup(char *options)
2429 +{
2430 + /* no options yet */
2431 + return 1;
2432 +}
2433 +
2434 +static int __init rc32434_setup_ethaddr0(char *options)
2435 +{
2436 + memcpy(mac0, options, 17);
2437 + mac0[17]= '\0';
2438 + return 1;
2439 +}
2440 +
2441 +__setup("rc32434eth=", rc32434_setup);
2442 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2443 +
2444 +
2445 +#endif /* MODULE */
2446 +
2447 +module_init(rc32434_init_module);
2448 +module_exit(rc32434_cleanup_module);
2449 +
2450 +
2451 +
2452 +
2453 +
2454 +
2455 +
2456 +
2457 +
2458 +
2459 +
2460 +
2461 +
2462 +
2463 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.h linux-2.6.16-owrt/drivers/net/rc32434_eth.h
2464 --- linux-2.6.16/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2465 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
2466 @@ -0,0 +1,187 @@
2467 +/**************************************************************************
2468 + *
2469 + * BRIEF MODULE DESCRIPTION
2470 + * Definitions for IDT RC32434 on-chip ethernet controller.
2471 + *
2472 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2473 + *
2474 + * This program is free software; you can redistribute it and/or modify it
2475 + * under the terms of the GNU General Public License as published by the
2476 + * Free Software Foundation; either version 2 of the License, or (at your
2477 + * option) any later version.
2478 + *
2479 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2480 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2481 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2482 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2483 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2484 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2485 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2486 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2487 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2488 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2489 + *
2490 + * You should have received a copy of the GNU General Public License along
2491 + * with this program; if not, write to the Free Software Foundation, Inc.,
2492 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2493 + *
2494 + *
2495 + **************************************************************************
2496 + * May 2004 rkt, neb
2497 + *
2498 + * Initial Release
2499 + *
2500 + * Aug 2004
2501 + *
2502 + * Added NAPI
2503 + *
2504 + **************************************************************************
2505 + */
2506 +
2507 +
2508 +#include <asm/idt-boards/rc32434/rc32434.h>
2509 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2510 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2511 +
2512 +#define RC32434_DEBUG 2
2513 +//#define RC32434_PROC_DEBUG
2514 +#undef RC32434_DEBUG
2515 +
2516 +#ifdef RC32434_DEBUG
2517 +
2518 +/* use 0 for production, 1 for verification, >2 for debug */
2519 +static int rc32434_debug = RC32434_DEBUG;
2520 +#define ASSERT(expr) \
2521 + if(!(expr)) { \
2522 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2523 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2524 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2525 +#else
2526 +#define ASSERT(expr) do {} while (0)
2527 +#define DBG(lvl, format, arg...) do {} while (0)
2528 +#endif
2529 +
2530 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2531 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2532 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2533 +
2534 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2535 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2536 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2537 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2538 +
2539 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2540 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2541 +
2542 +/* the following must be powers of two */
2543 +#ifdef CONFIG_IDT_USE_NAPI
2544 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2545 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2546 +#else
2547 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2548 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2549 +#endif
2550 +
2551 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2552 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2553 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2554 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2555 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2556 +
2557 +#define RC32434_TX_TIMEOUT HZ * 100
2558 +
2559 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2560 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2561 +
2562 +enum status { filled, empty};
2563 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2564 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2565 +
2566 +
2567 +/* Information that need to be kept for each board. */
2568 +struct rc32434_local {
2569 + ETH_t eth_regs;
2570 + DMA_Chan_t rx_dma_regs;
2571 + DMA_Chan_t tx_dma_regs;
2572 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2573 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2574 +
2575 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2576 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2577 +
2578 +#ifndef CONFIG_IDT_USE_NAPI
2579 + struct tasklet_struct * rx_tasklet;
2580 +#endif
2581 + struct tasklet_struct * tx_tasklet;
2582 +
2583 + int rx_next_done;
2584 + int rx_chain_head;
2585 + int rx_chain_tail;
2586 + enum status rx_chain_status;
2587 +
2588 + int tx_next_done;
2589 + int tx_chain_head;
2590 + int tx_chain_tail;
2591 + enum status tx_chain_status;
2592 + int tx_count;
2593 + int tx_full;
2594 +
2595 + struct timer_list mii_phy_timer;
2596 + unsigned long duplex_mode;
2597 +
2598 + int rx_irq;
2599 + int tx_irq;
2600 + int ovr_irq;
2601 + int und_irq;
2602 +
2603 + struct net_device_stats stats;
2604 + spinlock_t lock;
2605 +
2606 + /* debug /proc entry */
2607 + struct proc_dir_entry *ps;
2608 + int dma_halt_cnt; int dma_run_cnt;
2609 +};
2610 +
2611 +extern unsigned int idt_cpu_freq;
2612 +
2613 +/* Index to functions, as function prototypes. */
2614 +static int rc32434_open(struct net_device *dev);
2615 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2616 +static void rc32434_mii_handler(unsigned long data);
2617 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2618 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2619 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2620 +#ifdef RC32434_REVISION
2621 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2622 +#endif
2623 +static int rc32434_close(struct net_device *dev);
2624 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2625 +static void rc32434_multicast_list(struct net_device *dev);
2626 +static int rc32434_init(struct net_device *dev);
2627 +static void rc32434_tx_timeout(struct net_device *dev);
2628 +
2629 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2630 +#ifdef CONFIG_IDT_USE_NAPI
2631 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2632 +#else
2633 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2634 +#endif
2635 +static void rc32434_cleanup_module(void);
2636 +static int rc32434_probe(int port_num);
2637 +int rc32434_init_module(void);
2638 +
2639 +
2640 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2641 +{
2642 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2643 + rc32434_writel(0x10, &ch->dmac);
2644 +
2645 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2646 + dev->trans_start = jiffies;
2647 +
2648 + rc32434_writel(0, &ch->dmas);
2649 + }
2650 +
2651 + rc32434_writel(0, &ch->dmadptr);
2652 + rc32434_writel(0, &ch->dmandptr);
2653 +}
2654 diff -Nur linux-2.6.16/include/asm-mips/bootinfo.h linux-2.6.16-owrt/include/asm-mips/bootinfo.h
2655 --- linux-2.6.16/include/asm-mips/bootinfo.h 2006-03-20 06:53:29.000000000 +0100
2656 +++ linux-2.6.16-owrt/include/asm-mips/bootinfo.h 2006-03-20 14:25:10.000000000 +0100
2657 @@ -218,6 +218,17 @@
2658 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2659 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2660
2661 +
2662 +/*
2663 + * Valid machtype for group ARUBA
2664 + */
2665 +#define MACH_GROUP_ARUBA 23
2666 +#define MACH_ARUBA_UNKNOWN 0
2667 +#define MACH_ARUBA_AP60 1
2668 +#define MACH_ARUBA_AP65 2
2669 +#define MACH_ARUBA_AP70 3
2670 +#define MACH_ARUBA_AP40 4
2671 +
2672 #define CL_SIZE COMMAND_LINE_SIZE
2673
2674 const char *get_system_type(void);
2675 diff -Nur linux-2.6.16/include/asm-mips/cpu.h linux-2.6.16-owrt/include/asm-mips/cpu.h
2676 --- linux-2.6.16/include/asm-mips/cpu.h 2006-03-20 06:53:29.000000000 +0100
2677 +++ linux-2.6.16-owrt/include/asm-mips/cpu.h 2006-03-20 14:25:10.000000000 +0100
2678 @@ -53,6 +53,9 @@
2679 #define PRID_IMP_R12000 0x0e00
2680 #define PRID_IMP_R8000 0x1000
2681 #define PRID_IMP_PR4450 0x1200
2682 +#define PRID_IMP_RC32334 0x1800
2683 +#define PRID_IMP_RC32355 0x1900
2684 +#define PRID_IMP_RC32365 0x1900
2685 #define PRID_IMP_R4600 0x2000
2686 #define PRID_IMP_R4700 0x2100
2687 #define PRID_IMP_TX39 0x2200
2688 @@ -196,7 +199,8 @@
2689 #define CPU_34K 60
2690 #define CPU_PR4450 61
2691 #define CPU_SB1A 62
2692 -#define CPU_LAST 62
2693 +#define CPU_RC32300 63
2694 +#define CPU_LAST 63
2695
2696 /*
2697 * ISA Level encodings
2698 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2699 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2700 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-03-20 14:25:10.000000000 +0100
2701 @@ -0,0 +1,142 @@
2702 +/**************************************************************************
2703 + *
2704 + * BRIEF MODULE DESCRIPTION
2705 + * RC32300 helper routines
2706 + *
2707 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2708 + *
2709 + * This program is free software; you can redistribute it and/or modify it
2710 + * under the terms of the GNU General Public License as published by the
2711 + * Free Software Foundation; either version 2 of the License, or (at your
2712 + * option) any later version.
2713 + *
2714 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2715 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2716 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2717 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2718 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2719 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2720 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2721 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2722 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2723 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2724 + *
2725 + * You should have received a copy of the GNU General Public License along
2726 + * with this program; if not, write to the Free Software Foundation, Inc.,
2727 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2728 + *
2729 + *
2730 + **************************************************************************
2731 + * May 2004 P. Sadik.
2732 + *
2733 + * Initial Release
2734 + *
2735 + *
2736 + *
2737 + **************************************************************************
2738 + */
2739 +
2740 +#ifndef __IDT_RC32300_H__
2741 +#define __IDT_RC32300_H__
2742 +
2743 +#include <linux/delay.h>
2744 +#include <asm/io.h>
2745 +
2746 +
2747 +/* cpu pipeline flush */
2748 +static inline void rc32300_sync(void)
2749 +{
2750 + __asm__ volatile ("sync");
2751 +}
2752 +
2753 +static inline void rc32300_sync_udelay(int us)
2754 +{
2755 + __asm__ volatile ("sync");
2756 + udelay(us);
2757 +}
2758 +
2759 +static inline void rc32300_sync_delay(int ms)
2760 +{
2761 + __asm__ volatile ("sync");
2762 + mdelay(ms);
2763 +}
2764 +
2765 +/*
2766 + * Macros to access internal RC32300 registers. No byte
2767 + * swapping should be done when accessing the internal
2768 + * registers.
2769 + */
2770 +
2771 +static inline u8 rc32300_readb(unsigned long pa)
2772 +{
2773 + return *((volatile u8 *)KSEG1ADDR(pa));
2774 +}
2775 +static inline u16 rc32300_readw(unsigned long pa)
2776 +{
2777 + return *((volatile u16 *)KSEG1ADDR(pa));
2778 +}
2779 +static inline u32 rc32300_readl(unsigned long pa)
2780 +{
2781 + return *((volatile u32 *)KSEG1ADDR(pa));
2782 +}
2783 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2784 +{
2785 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2786 +}
2787 +static inline void rc32300_writew(u16 val, unsigned long pa)
2788 +{
2789 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2790 +}
2791 +static inline void rc32300_writel(u32 val, unsigned long pa)
2792 +{
2793 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2794 +}
2795 +
2796 +
2797 +#define local_readb __raw_readb
2798 +#define local_readw __raw_readw
2799 +#define local_readl __raw_readl
2800 +
2801 +#define local_writeb __raw_writeb
2802 +#define local_writew __raw_writew
2803 +#define local_writel __raw_writel
2804 +
2805 +
2806 +/*
2807 + * C access to CLZ and CLO instructions
2808 + * (count leading zeroes/ones).
2809 + */
2810 +static inline int rc32300_clz(unsigned long val)
2811 +{
2812 + int ret;
2813 + __asm__ volatile (
2814 + ".set\tnoreorder\n\t"
2815 + ".set\tnoat\n\t"
2816 + ".set\tmips32\n\t"
2817 + "clz\t%0,%1\n\t"
2818 + ".set\tmips0\n\t"
2819 + ".set\tat\n\t"
2820 + ".set\treorder"
2821 + : "=r" (ret)
2822 + : "r" (val));
2823 +
2824 + return ret;
2825 +}
2826 +static inline int rc32300_clo(unsigned long val)
2827 +{
2828 + int ret;
2829 + __asm__ volatile (
2830 + ".set\tnoreorder\n\t"
2831 + ".set\tnoat\n\t"
2832 + ".set\tmips32\n\t"
2833 + "clo\t%0,%1\n\t"
2834 + ".set\tmips0\n\t"
2835 + ".set\tat\n\t"
2836 + ".set\treorder"
2837 + : "=r" (ret)
2838 + : "r" (val));
2839 +
2840 + return ret;
2841 +}
2842 +
2843 +#endif // __IDT_RC32300_H__
2844 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2845 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2846 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-03-20 14:25:10.000000000 +0100
2847 @@ -0,0 +1,207 @@
2848 +/**************************************************************************
2849 + *
2850 + * BRIEF MODULE DESCRIPTION
2851 + * Definitions for IDT RC32334 CPU.
2852 + *
2853 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2854 + *
2855 + * This program is free software; you can redistribute it and/or modify it
2856 + * under the terms of the GNU General Public License as published by the
2857 + * Free Software Foundation; either version 2 of the License, or (at your
2858 + * option) any later version.
2859 + *
2860 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2861 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2862 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2863 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2864 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2865 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2866 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2867 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2868 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2869 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2870 + *
2871 + * You should have received a copy of the GNU General Public License along
2872 + * with this program; if not, write to the Free Software Foundation, Inc.,
2873 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2874 + *
2875 + *
2876 + **************************************************************************
2877 + * May 2004 P. Sadik.
2878 + *
2879 + * Initial Release
2880 + *
2881 + *
2882 + *
2883 + **************************************************************************
2884 + */
2885 +
2886 +
2887 +#ifndef __IDT_RC32334_H__
2888 +#define __IDT_RC32334_H__
2889 +
2890 +#include <linux/delay.h>
2891 +#include <asm/io.h>
2892 +
2893 +/* Base address of internal registers */
2894 +#define RC32334_REG_BASE 0x18000000
2895 +
2896 +/* CPU and IP Bus Control */
2897 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2898 +#define CPU_BTA 0xffffe204 // virtual!
2899 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2900 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2901 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2902 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2903 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2904 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2905 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2906 +
2907 +/* Memory Controller */
2908 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2909 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2910 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2911 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2912 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2913 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2914 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2915 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2916 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2917 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2918 +
2919 +/* PCI Controller */
2920 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2921 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2922 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2923 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2924 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2925 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2926 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2927 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2928 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2929 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2930 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2931 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2932 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2933 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2934 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2935 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2936 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2937 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2938 +
2939 +/* Timers */
2940 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2941 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2942 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2943 +#define TIMER_REG_OFFSET 0x10
2944 +
2945 +/* Programmable I/O */
2946 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2947 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2948 +
2949 +/*
2950 + * DMA
2951 + *
2952 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2953 + *
2954 + * DMA0: 18001400
2955 + * DMA1: 18001440
2956 + * DMA2: 18001900
2957 + * DMA3: 18001940
2958 + * NB: dma number must be immediate value or variable.
2959 + * It MUST NOT be a function since it would get called twice!
2960 + */
2961 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2962 +
2963 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2964 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2965 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2966 +
2967 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2968 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2969 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2970 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2971 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2972 +
2973 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2974 +
2975 +/* Expansion Interrupt Controller */
2976 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2977 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2978 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2979 +#define IC_GROUP_OFFSET 0x10
2980 +
2981 +#define NUM_INTR_GROUPS 15
2982 +/*
2983 + * The IRQ mapping is as follows:
2984 + *
2985 + * IRQ Mapped To
2986 + * --- -------------------
2987 + * 0 SW0 (IP0) SW0 intr
2988 + * 1 SW1 (IP1) SW1 intr
2989 + * 2 Int0 (IP2) board-specific
2990 + * 3 Int1 (IP3) board-specific
2991 + * 4 Int2 (IP4) board-specific
2992 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
2993 + * 6 Int4 (IP6) board-specific
2994 + * 7 Int5 (IP7) CP0 Timer
2995 + *
2996 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2997 + * internally on the RC32334 is routed to the Expansion
2998 + * Interrupt Controller.
2999 + */
3000 +#define MIPS_CPU_TIMER_IRQ 7
3001 +
3002 +#define GROUP1_IRQ_BASE 8 // bus error
3003 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3004 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3005 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3006 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3007 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3008 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3009 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3010 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3011 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3012 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3013 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3014 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3015 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3016 +
3017 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3018 +
3019 +/* 16550 UARTs */
3020 +#ifdef __MIPSEB__
3021 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3022 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3023 +#else
3024 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3025 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3026 +#endif
3027 +
3028 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3029 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3030 +
3031 +#define IDT_CLOCK_MULT 2
3032 +
3033 +/* NVRAM */
3034 +#define NVRAM_BASE 0x12000000
3035 +#define NVRAM_ENVSIZE_OFF 4
3036 +#define NVRAM_ENVSTART_OFF 0x40
3037 +
3038 +/* LCD 4-digit display */
3039 +#define LCD_CLEAR 0x14000400
3040 +#define LCD_DIGIT0 0x1400000f
3041 +#define LCD_DIGIT1 0x14000008
3042 +#define LCD_DIGIT2 0x14000007
3043 +#define LCD_DIGIT3 0x14000003
3044 +
3045 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3046 +#define RC32334_SCC8530_IRQ 2
3047 +#define RC32334_PCI_INTA_IRQ 3
3048 +#define RC32334_PCI_INTB_IRQ 4
3049 +#define RC32334_PCI_INTC_IRQ 6
3050 +#define RC32334_PCI_INTD_IRQ 7
3051 +
3052 +#define RAM_SIZE (32*1024*1024)
3053 +
3054 +#endif // __IDT_RC32334_H__
3055 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3056 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3057 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-03-20 14:25:10.000000000 +0100
3058 @@ -0,0 +1,206 @@
3059 +/**************************************************************************
3060 + *
3061 + * BRIEF MODULE DESCRIPTION
3062 + * DMA controller defines on IDT RC32355
3063 + *
3064 + * Copyright 2004 IDT Inc.
3065 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3066 + *
3067 + *
3068 + * This program is free software; you can redistribute it and/or modify it
3069 + * under the terms of the GNU General Public License as published by the
3070 + * Free Software Foundation; either version 2 of the License, or (at your
3071 + * option) any later version.
3072 + *
3073 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3074 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3075 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3076 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3077 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3078 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3079 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3080 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3081 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3082 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3083 + *
3084 + * You should have received a copy of the GNU General Public License along
3085 + * with this program; if not, write to the Free Software Foundation, Inc.,
3086 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3087 + *
3088 + *
3089 + * May 2004 rkt
3090 + * Initial Release
3091 + *
3092 + **************************************************************************
3093 + */
3094 +
3095 +#ifndef BANYAN_DMA_H
3096 +#define BANYAN_DMA_H
3097 +#include <asm/idt-boards/rc32300/rc32300.h>
3098 +
3099 +/*
3100 + * An image of one RC32355 dma channel registers
3101 + */
3102 +typedef struct {
3103 + u32 dmac;
3104 + u32 dmas;
3105 + u32 dmasm;
3106 + u32 dmadptr;
3107 + u32 dmandptr;
3108 +} rc32355_dma_ch_t;
3109 +
3110 +/*
3111 + * An image of all RC32355 dma channel registers
3112 + */
3113 +typedef struct {
3114 + rc32355_dma_ch_t ch[16];
3115 +} rc32355_dma_regs_t;
3116 +
3117 +
3118 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3119 +
3120 +
3121 +/* DMAC register layout */
3122 +
3123 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3124 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3125 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3126 +
3127 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3128 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3129 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3130 +
3131 +/* DMAS and DMASM register layout */
3132 +
3133 +#define DMAS_F 0x01 /* Finished */
3134 +#define DMAS_D 0x02 /* Done */
3135 +#define DMAS_C 0x04 /* Chain */
3136 +#define DMAS_E 0x08 /* Error */
3137 +#define DMAS_H 0x10 /* Halt */
3138 +
3139 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3140 +#define DMA_HALT_TIMEOUT 500
3141 +
3142 +
3143 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3144 +{
3145 + int timeout=1;
3146 +
3147 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3148 + local_writel(0, &ch->dmac);
3149 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3150 + if (local_readl(&ch->dmas) & DMAS_H) {
3151 + local_writel(0, &ch->dmas);
3152 + break;
3153 + }
3154 + }
3155 + }
3156 +
3157 + return timeout ? 0 : 1;
3158 +}
3159 +
3160 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3161 +{
3162 + local_writel(0, &ch->dmandptr);
3163 + local_writel(dma_addr, &ch->dmadptr);
3164 +}
3165 +
3166 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3167 +{
3168 + local_writel(dma_addr, &ch->dmandptr);
3169 +}
3170 +
3171 +
3172 +/* The following can be used to describe DMA channels 0 to 15, and the */
3173 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3174 +
3175 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3176 +
3177 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3178 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3179 +
3180 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3181 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3182 +
3183 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3184 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3185 +
3186 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3187 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3188 +
3189 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3190 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3191 +#define DMA_DEV_ATMVCC(entry) 0
3192 +
3193 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3194 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3195 +
3196 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3197 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3198 +
3199 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3200 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3201 +
3202 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3203 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3204 +
3205 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3206 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3207 +
3208 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3209 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3210 +
3211 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3212 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3213 +
3214 +#define DMA_CHAN_USBIN 13 /* USB input */
3215 +#define DMA_DEV_USBIN 0 /* USB input */
3216 +
3217 +#define DMA_CHAN_USBOUT 14 /* USB output */
3218 +#define DMA_DEV_USBOUT 0 /* USB output */
3219 +
3220 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3221 +#define DMA_DEV_EXTERN 0 /* External DMA */
3222 +
3223 +/*
3224 + * An RC32355 dma descriptor in system memory
3225 + */
3226 +typedef struct {
3227 + u32 cmdstat; /* control and status */
3228 + u32 curr_addr; /* current address of data */
3229 + u32 devcs; /* peripheral-specific control and status */
3230 + u32 link; /* link to next descriptor */
3231 +} rc32355_dma_desc_t;
3232 +
3233 +/* Values for the descriptor cmdstat word */
3234 +
3235 +#define DMADESC_F 0x80000000u /* Finished bit */
3236 +#define DMADESC_D 0x40000000u /* Done bit */
3237 +#define DMADESC_T 0x20000000u /* Terminated bit */
3238 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3239 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3240 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3241 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3242 +
3243 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3244 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3245 +
3246 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3247 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3248 +
3249 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3250 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3251 +
3252 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3253 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3254 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3255 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3256 +
3257 +#define DMA_DEVCMD(devcmd) \
3258 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3259 +#define DMA_DS(ds) \
3260 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3261 +#define DMA_COUNT(count) \
3262 + ((count) & DMADESC_COUNT_MASK)
3263 +
3264 +#endif /* RC32355_DMA_H */
3265 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3266 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3267 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-03-20 14:25:10.000000000 +0100
3268 @@ -0,0 +1,442 @@
3269 +/**************************************************************************
3270 + *
3271 + * BRIEF MODULE DESCRIPTION
3272 + * Ethernet registers on IDT RC32355
3273 + *
3274 + * Copyright 2004 IDT Inc.
3275 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3276 + *
3277 + *
3278 + * This program is free software; you can redistribute it and/or modify it
3279 + * under the terms of the GNU General Public License as published by the
3280 + * Free Software Foundation; either version 2 of the License, or (at your
3281 + * option) any later version.
3282 + *
3283 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3284 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3285 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3286 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3287 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3288 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3289 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3290 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3291 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3292 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3293 + *
3294 + * You should have received a copy of the GNU General Public License along
3295 + * with this program; if not, write to the Free Software Foundation, Inc.,
3296 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3297 + *
3298 + *
3299 + * May 2004 rkt
3300 + * Initial Release
3301 + *
3302 + **************************************************************************
3303 + */
3304 +
3305 +
3306 +#ifndef RC32355_ETHER_H
3307 +#define RC32355_ETHER_H
3308 +
3309 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3310 +
3311 +/*
3312 + * A partial image of the RC32355 ethernet registers
3313 + */
3314 +typedef struct {
3315 + u32 ethintfc;
3316 + u32 ethfifott;
3317 + u32 etharc;
3318 + u32 ethhash0;
3319 + u32 ethhash1;
3320 + u32 ethfifost;
3321 + u32 ethfifos;
3322 + u32 ethodeops;
3323 + u32 ethis;
3324 + u32 ethos;
3325 + u32 ethmcp;
3326 + u32 _u1;
3327 + u32 ethid;
3328 + u32 _u2;
3329 + u32 _u3;
3330 + u32 _u4;
3331 + u32 ethod;
3332 + u32 _u5;
3333 + u32 _u6;
3334 + u32 _u7;
3335 + u32 ethodeop;
3336 + u32 _u8[43];
3337 + u32 ethsal0;
3338 + u32 ethsah0;
3339 + u32 ethsal1;
3340 + u32 ethsah1;
3341 + u32 ethsal2;
3342 + u32 ethsah2;
3343 + u32 ethsal3;
3344 + u32 ethsah3;
3345 + u32 ethrbc;
3346 + u32 ethrpc;
3347 + u32 ethrupc;
3348 + u32 ethrfc;
3349 + u32 ethtbc;
3350 + u32 ethgpf;
3351 + u32 _u9[50];
3352 + u32 ethmac1;
3353 + u32 ethmac2;
3354 + u32 ethipgt;
3355 + u32 ethipgr;
3356 + u32 ethclrt;
3357 + u32 ethmaxf;
3358 + u32 _u10;
3359 + u32 ethmtest;
3360 + u32 miimcfg;
3361 + u32 miimcmd;
3362 + u32 miimaddr;
3363 + u32 miimwtd;
3364 + u32 miimrdd;
3365 + u32 miimind;
3366 + u32 _u11;
3367 + u32 _u12;
3368 + u32 ethcfsa0;
3369 + u32 ethcfsa1;
3370 + u32 ethcfsa2;
3371 +} rc32355_eth_regs_t;
3372 +
3373 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3374 +
3375 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3376 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3377 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3378 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3379 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3380 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3381 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3382 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3383 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3384 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3385 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3386 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3387 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3388 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3389 +
3390 +/* for n in { 0, 1, 2, 3 } */
3391 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3392 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3393 +
3394 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3395 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3396 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3397 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3398 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3399 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3400 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3401 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3402 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3403 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3404 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3405 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3406 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3407 +
3408 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3409 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3410 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3411 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3412 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3413 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3414 +
3415 +/* for n in { 0, 1, 2 } */
3416 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3417 +
3418 +
3419 +/*
3420 + * Register Interpretations follow
3421 + */
3422 +
3423 +/******************************************************************************
3424 + * ETHINTFC register
3425 + *****************************************************************************/
3426 +
3427 +#define ETHERINTFC_EN (1<<0)
3428 +#define ETHERINTFC_ITS (1<<1)
3429 +#define ETHERINTFC_RES (1<<2)
3430 +#define ETHERINTFC_RIP (1<<2)
3431 +#define ETHERINTFC_JAM (1<<3)
3432 +
3433 +/******************************************************************************
3434 + * ETHFIFOTT register
3435 + *****************************************************************************/
3436 +
3437 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3438 +
3439 +/******************************************************************************
3440 + * ETHARC register
3441 + *****************************************************************************/
3442 +
3443 +#define ETHERARC_PRO (1<<0)
3444 +#define ETHERARC_AM (1<<1)
3445 +#define ETHERARC_AFM (1<<2)
3446 +#define ETHERARC_AB (1<<3)
3447 +
3448 +/******************************************************************************
3449 + * ETHHASH registers
3450 + *****************************************************************************/
3451 +
3452 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3453 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3454 +
3455 +/******************************************************************************
3456 + * ETHSA registers
3457 + *****************************************************************************/
3458 +
3459 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3460 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3461 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3462 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3463 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3464 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3465 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3466 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3467 +
3468 +/******************************************************************************
3469 + * ETHFIFOST register
3470 + *****************************************************************************/
3471 +
3472 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3473 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3474 +
3475 +/******************************************************************************
3476 + * ETHFIFOS register
3477 + *****************************************************************************/
3478 +
3479 +#define ETHERFIFOS_IR (1<<0)
3480 +#define ETHERFIFOS_OR (1<<1)
3481 +#define ETHERFIFOS_OVR (1<<2)
3482 +#define ETHERFIFOS_UND (1<<3)
3483 +
3484 +/******************************************************************************
3485 + * DATA registers
3486 + *****************************************************************************/
3487 +
3488 +#define ETHERID(v) (((v)&0xffff)<<0)
3489 +#define ETHEROD(v) (((v)&0xffff)<<0)
3490 +
3491 +/******************************************************************************
3492 + * ETHODEOPS register
3493 + *****************************************************************************/
3494 +
3495 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3496 +
3497 +/******************************************************************************
3498 + * ETHODEOP register
3499 + *****************************************************************************/
3500 +
3501 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3502 +
3503 +/******************************************************************************
3504 + * ETHIS register
3505 + *****************************************************************************/
3506 +
3507 +#define ETHERIS_EOP (1<<0)
3508 +#define ETHERIS_ROK (1<<2)
3509 +#define ETHERIS_FM (1<<3)
3510 +#define ETHERIS_MP (1<<4)
3511 +#define ETHERIS_BP (1<<5)
3512 +#define ETHERIS_VLT (1<<6)
3513 +#define ETHERIS_CF (1<<7)
3514 +#define ETHERIS_OVR (1<<8)
3515 +#define ETHERIS_CRC (1<<9)
3516 +#define ETHERIS_CV (1<<10)
3517 +#define ETHERIS_DB (1<<11)
3518 +#define ETHERIS_LE (1<<12)
3519 +#define ETHERIS_LOR (1<<13)
3520 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3521 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3522 +
3523 +/******************************************************************************
3524 + * ETHOS register
3525 + *****************************************************************************/
3526 +
3527 +#define ETHEROS_T (1<<0)
3528 +#define ETHEROS_TOK (1<<6)
3529 +#define ETHEROS_MP (1<<7)
3530 +#define ETHEROS_BP (1<<8)
3531 +#define ETHEROS_UND (1<<9)
3532 +#define ETHEROS_OF (1<<10)
3533 +#define ETHEROS_ED (1<<11)
3534 +#define ETHEROS_EC (1<<12)
3535 +#define ETHEROS_LC (1<<13)
3536 +#define ETHEROS_TD (1<<14)
3537 +#define ETHEROS_CRC (1<<15)
3538 +#define ETHEROS_LE (1<<16)
3539 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3540 +#define ETHEROS_PFD (1<<21)
3541 +
3542 +/******************************************************************************
3543 + * Statistics registers
3544 + *****************************************************************************/
3545 +
3546 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3547 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3548 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3549 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3550 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3551 +
3552 +/******************************************************************************
3553 + * ETHGPF register
3554 + *****************************************************************************/
3555 +
3556 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3557 +
3558 +/******************************************************************************
3559 + * MAC registers
3560 + *****************************************************************************/
3561 +//ETHMAC1
3562 +#define ETHERMAC1_RE (1<<0)
3563 +#define ETHERMAC1_PAF (1<<1)
3564 +#define ETHERMAC1_RFC (1<<2)
3565 +#define ETHERMAC1_TFC (1<<3)
3566 +#define ETHERMAC1_LB (1<<4)
3567 +#define ETHERMAC1_MR (1<<15)
3568 +
3569 +//ETHMAC2
3570 +#define ETHERMAC2_FD (1<<0)
3571 +#define ETHERMAC2_FLC (1<<1)
3572 +#define ETHERMAC2_HFE (1<<2)
3573 +#define ETHERMAC2_DC (1<<3)
3574 +#define ETHERMAC2_CEN (1<<4)
3575 +#define ETHERMAC2_PE (1<<5)
3576 +#define ETHERMAC2_VPE (1<<6)
3577 +#define ETHERMAC2_APE (1<<7)
3578 +#define ETHERMAC2_PPE (1<<8)
3579 +#define ETHERMAC2_LPE (1<<9)
3580 +#define ETHERMAC2_NB (1<<12)
3581 +#define ETHERMAC2_BP (1<<13)
3582 +#define ETHERMAC2_ED (1<<14)
3583 +
3584 +//ETHIPGT
3585 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3586 +
3587 +//ETHIPGR
3588 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3589 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3590 +
3591 +//ETHCLRT
3592 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3593 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3594 +
3595 +//ETHMAXF
3596 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3597 +
3598 +//ETHMTEST
3599 +#define ETHERMTEST_TB (1<<2)
3600 +
3601 +//ETHMCP
3602 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3603 +
3604 +//MIIMCFG
3605 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3606 +#define ETHERMIIMCFG_R (1<<15)
3607 +
3608 +//MIIMCMD
3609 +#define ETHERMIIMCMD_RD (1<<0)
3610 +#define ETHERMIIMCMD_SCN (1<<1)
3611 +
3612 +//MIIMADDR
3613 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3614 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3615 +
3616 +//MIIMWTD
3617 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3618 +
3619 +//MIIMRDD
3620 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3621 +
3622 +//MIIMIND
3623 +#define ETHERMIIMIND_BSY (1<<0)
3624 +#define ETHERMIIMIND_SCN (1<<1)
3625 +#define ETHERMIIMIND_NV (1<<2)
3626 +
3627 +//DMA DEVCS IN
3628 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3629 +#define ETHERDMA_IN_CES (1<<14)
3630 +#define ETHERDMA_IN_LOR (1<<13)
3631 +#define ETHERDMA_IN_LE (1<<12)
3632 +#define ETHERDMA_IN_DB (1<<11)
3633 +#define ETHERDMA_IN_CV (1<<10)
3634 +#define ETHERDMA_IN_CRC (1<<9)
3635 +#define ETHERDMA_IN_OVR (1<<8)
3636 +#define ETHERDMA_IN_CF (1<<7)
3637 +#define ETHERDMA_IN_VLT (1<<6)
3638 +#define ETHERDMA_IN_BP (1<<5)
3639 +#define ETHERDMA_IN_MP (1<<4)
3640 +#define ETHERDMA_IN_FM (1<<3)
3641 +#define ETHERDMA_IN_ROK (1<<2)
3642 +#define ETHERDMA_IN_LD (1<<1)
3643 +#define ETHERDMA_IN_FD (1<<0)
3644 +
3645 +//DMA DEVCS OUT
3646 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3647 +#define ETHERDMA_OUT_CNT 0x001e0000
3648 +#define ETHERDMA_OUT_SHFT 17
3649 +#define ETHERDMA_OUT_LE (1<<16)
3650 +
3651 +#define ETHERDMA_OUT_CRC (1<<15)
3652 +#define ETHERDMA_OUT_TD (1<<14)
3653 +#define ETHERDMA_OUT_LC (1<<13)
3654 +#define ETHERDMA_OUT_EC (1<<12)
3655 +#define ETHERDMA_OUT_ED (1<<11)
3656 +#define ETHERDMA_OUT_OF (1<<10)
3657 +#define ETHERDMA_OUT_UND (1<<9)
3658 +#define ETHERDMA_OUT_BP (1<<8)
3659 +#define ETHERDMA_OUT_MP (1<<7)
3660 +#define ETHERDMA_OUT_TOK (1<<6)
3661 +#define ETHERDMA_OUT_HEN (1<<5)
3662 +#define ETHERDMA_OUT_CEN (1<<4)
3663 +#define ETHERDMA_OUT_PEN (1<<3)
3664 +#define ETHERDMA_OUT_OEN (1<<2)
3665 +#define ETHERDMA_OUT_LD (1<<1)
3666 +#define ETHERDMA_OUT_FD (1<<0)
3667 +
3668 +#define RCV_ERRS \
3669 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3670 +#define TX_ERRS \
3671 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3672 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3673 +
3674 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3675 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3676 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3677 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3678 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3679 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3680 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3681 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3682 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3683 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3684 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3685 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3686 + Range */
3687 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3688 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3689 + received packet */
3690 +
3691 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3692 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3693 +
3694 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3695 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3696 + Underflow */
3697 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3698 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3699 + deferral */
3700 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3701 + collisions */
3702 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3703 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3704 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3705 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3706 +
3707 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3708 +
3709 +#endif /* RC32355_ETHER_H */
3710 +
3711 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3712 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3713 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-03-20 14:25:10.000000000 +0100
3714 @@ -0,0 +1,177 @@
3715 +/**************************************************************************
3716 + *
3717 + * BRIEF MODULE DESCRIPTION
3718 + * Definitions for IDT RC32355 CPU.
3719 + *
3720 + * Copyright 2004 IDT Inc.
3721 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3722 + *
3723 + *
3724 + * This program is free software; you can redistribute it and/or modify it
3725 + * under the terms of the GNU General Public License as published by the
3726 + * Free Software Foundation; either version 2 of the License, or (at your
3727 + * option) any later version.
3728 + *
3729 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3730 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3731 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3732 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3733 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3734 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3735 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3736 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3737 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3738 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3739 + *
3740 + * You should have received a copy of the GNU General Public License along
3741 + * with this program; if not, write to the Free Software Foundation, Inc.,
3742 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3743 + *
3744 + *
3745 + * May 2004 rkt
3746 + * Initial Release
3747 + *
3748 + **************************************************************************
3749 + */
3750 +
3751 +
3752 +#ifndef _RC32355_H_
3753 +#define _RC32355_H_
3754 +
3755 +#include <linux/delay.h>
3756 +#include <asm/io.h>
3757 +
3758 +/* Base address of internal registers */
3759 +#define RC32355_REG_BASE 0x18000000
3760 +
3761 +/* System ID Registers */
3762 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3763 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3764 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3765 +
3766 +/* Reset Controller */
3767 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3768 +
3769 +/* Device Controller */
3770 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3771 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3772 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3773 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3774 +#define DEV_REG_OFFSET 0x10
3775 +
3776 +/* SDRAM Controller */
3777 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3778 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3779 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3780 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3781 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3782 +
3783 +/* Bus Arbiter */
3784 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3785 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3786 +
3787 +/* Counters/Timers */
3788 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3789 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3790 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3791 +#define TIMER_REG_OFFSET 0x0C
3792 +
3793 +/* System Integrity */
3794 +
3795 +/* Interrupt Controller */
3796 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3797 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3798 +#define IC_GROUP_OFFSET 0x08
3799 +
3800 +#define NUM_INTR_GROUPS 5
3801 +/*
3802 + * The IRQ mapping is as follows:
3803 + *
3804 + * IRQ Mapped To
3805 + * --- -------------------
3806 + * 0 SW0 (IP0) SW0 intr
3807 + * 1 SW1 (IP1) SW1 intr
3808 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3809 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3810 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3811 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3812 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3813 + * 7 Int5 (IP7) CP0 Timer
3814 + *
3815 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3816 + * internally on the RC32355 is routed to the Expansion
3817 + * Interrupt Controller.
3818 + */
3819 +#define MIPS_CPU_TIMER_IRQ 7
3820 +
3821 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3822 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3823 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3824 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3825 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3826 +
3827 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3828 +
3829 +/* DMA - see rc32355_dma.h for full list of registers */
3830 +
3831 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3832 +#define DMA_CHAN_OFFSET 0x14
3833 +
3834 +/* GPIO Controller */
3835 +
3836 +/* TDM Bus */
3837 +
3838 +/* 16550 UARTs */
3839 +#ifdef __MIPSEB__
3840 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3841 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3842 +#else
3843 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3844 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3845 +#endif
3846 +
3847 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3848 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3849 +
3850 +/* ATM */
3851 +
3852 +/* Ethernet - see rc32355_eth.h for full list of registers */
3853 +
3854 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3855 +
3856 +
3857 +#define IDT_CLOCK_MULT 2
3858 +
3859 +/* Memory map of 79EB355 board */
3860 +
3861 +/* DRAM */
3862 +#define RAM_BASE 0x00000000
3863 +#define RAM_SIZE (32*1024*1024)
3864 +
3865 +/* SRAM (device 1) */
3866 +#define SRAM_BASE 0x02000000
3867 +#define SRAM_SIZE 0x00100000
3868 +
3869 +/* FLASH (device 2) */
3870 +#define FLASH_BASE 0x0C000000
3871 +#define FLASH_SIZE 0x00C00000
3872 +
3873 +/* ATM PHY (device 4) */
3874 +#define ATM_PHY_BASE 0x14000000
3875 +
3876 +/* TDM switch (device 3) */
3877 +#define TDM_BASE 0x1A000000
3878 +
3879 +/* LCD panel (device 3) */
3880 +#define LCD_BASE 0x1A002000
3881 +
3882 +/* RTC (DS1511W) (device 3) */
3883 +#define RTC_BASE 0x1A004000
3884 +
3885 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3886 +#define NVRAM_ADDR RTC_BASE + 0x10
3887 +#define NVRAM_DATA RTC_BASE + 0x13
3888 +#define NVRAM_ENVSIZE_OFF 4
3889 +#define NVRAM_ENVSTART_OFF 32
3890 +
3891 +#endif /* _RC32355_H_ */
3892 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3893 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3894 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-03-20 14:25:10.000000000 +0100
3895 @@ -0,0 +1,226 @@
3896 +/**************************************************************************
3897 + *
3898 + * BRIEF MODULE DESCRIPTION
3899 + * RC32365/336 DMA hardware abstraction.
3900 + *
3901 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3902 + *
3903 + * This program is free software; you can redistribute it and/or modify it
3904 + * under the terms of the GNU General Public License as published by the
3905 + * Free Software Foundation; either version 2 of the License, or (at your
3906 + * option) any later version.
3907 + *
3908 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3909 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3910 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3911 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3912 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3913 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3914 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3915 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3916 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3917 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3918 + *
3919 + * You should have received a copy of the GNU General Public License along
3920 + * with this program; if not, write to the Free Software Foundation, Inc.,
3921 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3922 + *
3923 + *
3924 + **************************************************************************
3925 + * May 2004 P. Sadik.
3926 + *
3927 + * Initial Release
3928 + *
3929 + *
3930 + *
3931 + **************************************************************************
3932 + */
3933 +
3934 +#ifndef __IDT_RC32365_DMA_H__
3935 +#define __IDT_RC32365_DMA_H__
3936 +
3937 +enum
3938 +{
3939 + DMA0_PhysicalAddress = 0x18038000,
3940 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3941 +
3942 + DMA0_VirtualAddress = 0xb8038000,
3943 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3944 +} ;
3945 +
3946 +/*
3947 + * DMA descriptor (in physical memory).
3948 + */
3949 +
3950 +typedef struct DMAD_s
3951 +{
3952 + u32 control ; // Control. use DMAD_*
3953 + u32 ca ; // Current Address.
3954 + u32 devcs ; // Device control and status.
3955 + u32 link ; // Next descriptor in chain.
3956 +} volatile *DMAD_t ;
3957 +
3958 +enum
3959 +{
3960 + DMAD_size = sizeof (struct DMAD_s),
3961 + DMAD_count_b = 0, // in DMAD_t -> control
3962 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3963 + DMAD_ds_b = 20, // in DMAD_t -> control
3964 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3965 + DMAD_ds_extToMem0_v = 0,
3966 + DMAD_ds_memToExt0_v = 1,
3967 + DMAD_ds_extToMem1_v = 0,
3968 + DMAD_ds_memToExt1_v = 1,
3969 + DMAD_ds_ethRcv0_v = 0,
3970 + DMAD_ds_ethXmt0_v = 0,
3971 + DMAD_ds_ethRcv1_v = 0,
3972 + DMAD_ds_ethXmt2_v = 0,
3973 + DMAD_ds_memToFifo_v = 0,
3974 + DMAD_ds_fifoToMem_v = 0,
3975 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3976 + DMAD_ds_pciToMem_v = 0,
3977 + DMAD_ds_memToPci_v = 0,
3978 + DMAD_ds_securityInput_v = 0,
3979 + DMAD_ds_securityOutput_v = 0,
3980 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3981 +
3982 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3983 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
3984 + DMAD_devcmd_byte_v = 0, //memory-to-memory
3985 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
3986 + DMAD_devcmd_word_v = 2, //memory-to-memory
3987 + DMAD_devcmd_2words_v = 3, //memory-to-memory
3988 + DMAD_devcmd_4words_v = 4, //memory-to-memory
3989 + DMAD_devcmd_6words_v = 5, //memory-to-memory
3990 + DMAD_devcmd_8words_v = 6, //memory-to-memory
3991 + DMAD_devcmd_16words_v = 7, //memory-to-memory
3992 + DMAD_cof_b = 25, // chain on finished
3993 + DMAD_cof_m = 0x02000000, //
3994 + DMAD_cod_b = 26, // chain on done
3995 + DMAD_cod_m = 0x04000000, //
3996 + DMAD_iof_b = 27, // interrupt on finished
3997 + DMAD_iof_m = 0x08000000, //
3998 + DMAD_iod_b = 28, // interrupt on done
3999 + DMAD_iod_m = 0x10000000, //
4000 + DMAD_t_b = 29, // terminated
4001 + DMAD_t_m = 0x20000000, //
4002 + DMAD_d_b = 30, // done
4003 + DMAD_d_m = 0x40000000, //
4004 + DMAD_f_b = 31, // finished
4005 + DMAD_f_m = 0x80000000, //
4006 +} ;
4007 +
4008 +/*
4009 + * DMA register (within Internal Register Map).
4010 + */
4011 +
4012 +struct DMA_Chan_s
4013 +{
4014 + u32 dmac ; // Control.
4015 + u32 dmas ; // Status.
4016 + u32 dmasm ; // Mask.
4017 + u32 dmadptr ; // Descriptor pointer.
4018 + u32 dmandptr ; // Next descriptor pointer.
4019 +};
4020 +
4021 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4022 +
4023 +//DMA_Channels use DMACH_count instead
4024 +
4025 +enum
4026 +{
4027 + DMAC_run_b = 0, //
4028 + DMAC_run_m = 0x00000001, //
4029 + DMAC_dm_b = 1, // done mask
4030 + DMAC_dm_m = 0x00000002, //
4031 + DMAC_mode_b = 2, //
4032 + DMAC_mode_m = 0x0000000c, //
4033 + DMAC_mode_auto_v = 0,
4034 + DMAC_mode_burst_v = 1,
4035 + DMAC_mode_transfer_v = 2, //usually used
4036 + DMAC_mode_reserved_v = 3,
4037 + DMAC_a_b = 4, //
4038 + DMAC_a_m = 0x00000010, //
4039 +
4040 + DMAS_f_b = 0, // finished (sticky)
4041 + DMAS_f_m = 0x00000001, //
4042 + DMAS_d_b = 1, // done (sticky)
4043 + DMAS_d_m = 0x00000002, //
4044 + DMAS_c_b = 2, // chain (sticky)
4045 + DMAS_c_m = 0x00000004, //
4046 + DMAS_e_b = 3, // error (sticky)
4047 + DMAS_e_m = 0x00000008, //
4048 + DMAS_h_b = 4, // halt (sticky)
4049 + DMAS_h_m = 0x00000010, //
4050 +
4051 + DMASM_f_b = 0, // finished (1=mask)
4052 + DMASM_f_m = 0x00000001, //
4053 + DMASM_d_b = 1, // done (1=mask)
4054 + DMASM_d_m = 0x00000002, //
4055 + DMASM_c_b = 2, // chain (1=mask)
4056 + DMASM_c_m = 0x00000004, //
4057 + DMASM_e_b = 3, // error (1=mask)
4058 + DMASM_e_m = 0x00000008, //
4059 + DMASM_h_b = 4, // halt (1=mask)
4060 + DMASM_h_m = 0x00000010, //
4061 +} ;
4062 +
4063 +/*
4064 + * DMA channel definitions
4065 + */
4066 +
4067 +enum
4068 +{
4069 + DMACH_ethRcv0 = 0,
4070 + DMACH_ethXmt0 = 1,
4071 + DMACH_ethRcv1 = 2,
4072 + DMACH_ethXmt2 = 3,
4073 + DMACH_pciToMem = 4,
4074 + DMACH_memToPci = 5,
4075 + DMACH_securityInput = 6,
4076 + DMACH_securityOutput = 7,
4077 + DMACH_rng = 8,
4078 +
4079 + DMACH_count //must be last
4080 +};
4081 +
4082 +
4083 +typedef struct DMAC_s
4084 +{
4085 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4086 +} volatile *DMA_t ;
4087 +
4088 +
4089 +/*
4090 + * External DMA parameters
4091 +*/
4092 +
4093 +enum
4094 +{
4095 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4096 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4097 + DMADEVCMD_ts_byte_v = 0,
4098 + DMADEVCMD_ts_halfword_v = 1,
4099 + DMADEVCMD_ts_word_v = 2,
4100 + DMADEVCMD_ts_2word_v = 3,
4101 + DMADEVCMD_ts_4word_v = 4,
4102 + DMADEVCMD_ts_6word_v = 5,
4103 + DMADEVCMD_ts_8word_v = 6,
4104 + DMADEVCMD_ts_16word_v = 7
4105 +};
4106 +
4107 +
4108 +#if 1 // aws - Compatibility.
4109 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4110 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4111 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4112 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4113 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4114 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4115 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4116 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4117 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4118 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4119 +#endif // aws - Compatibility.
4120 +
4121 +#endif // __IDT_RC32365_DMA_H__
4122 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4123 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4124 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-03-20 14:25:10.000000000 +0100
4125 @@ -0,0 +1,86 @@
4126 +/**************************************************************************
4127 + *
4128 + * BRIEF MODULE DESCRIPTION
4129 + * RC32365/336 DMA interface routines.
4130 + *
4131 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4132 + *
4133 + * This program is free software; you can redistribute it and/or modify it
4134 + * under the terms of the GNU General Public License as published by the
4135 + * Free Software Foundation; either version 2 of the License, or (at your
4136 + * option) any later version.
4137 + *
4138 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4139 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4140 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4141 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4142 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4143 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4144 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4145 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4146 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4147 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4148 + *
4149 + * You should have received a copy of the GNU General Public License along
4150 + * with this program; if not, write to the Free Software Foundation, Inc.,
4151 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4152 + *
4153 + *
4154 + **************************************************************************
4155 + * May 2004 P. Sadik.
4156 + *
4157 + * Initial Release
4158 + *
4159 + *
4160 + *
4161 + **************************************************************************
4162 + */
4163 +
4164 +#ifndef __IDT_RC32365_DMA_V_H__
4165 +#define __IDT_RC32365_DMA_V_H__
4166 +
4167 +
4168 +#include <asm/idt-boards/rc32300/rc32300.h>
4169 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4170 +#include <asm/idt-boards/rc32300/rc32365.h>
4171 +
4172 +#define DMA_CHAN_OFFSET 0x14
4173 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4174 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4175 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4176 +
4177 +#define DMA_COUNT(count) \
4178 + ((count) & DMAD_count_m)
4179 +
4180 +#define DMA_HALT_TIMEOUT 500
4181 +
4182 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4183 +{
4184 + int timeout=1;
4185 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4186 + local_writel(0, &ch->dmac);
4187 +
4188 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4189 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4190 + local_writel(0, &ch->dmas);
4191 + break;
4192 + }
4193 + }
4194 +
4195 + }
4196 +
4197 + return timeout ? 0 : 1;
4198 +}
4199 +
4200 +
4201 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4202 +{
4203 + local_writel(0, &ch->dmandptr);
4204 + local_writel(dma_addr, &ch->dmadptr);
4205 +}
4206 +
4207 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4208 +{
4209 + local_writel(dma_addr, &ch->dmandptr);
4210 +}
4211 +#endif //__IDT_RC32365_DMA_V_H__
4212 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4213 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4214 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-03-20 14:25:10.000000000 +0100
4215 @@ -0,0 +1,344 @@
4216 +/**************************************************************************
4217 + *
4218 + * BRIEF MODULE DESCRIPTION
4219 + * RC32365/336 Ethernet hardware abstraction.
4220 + *
4221 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4222 + *
4223 + * This program is free software; you can redistribute it and/or modify it
4224 + * under the terms of the GNU General Public License as published by the
4225 + * Free Software Foundation; either version 2 of the License, or (at your
4226 + * option) any later version.
4227 + *
4228 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4229 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4230 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4231 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4232 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4233 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4234 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4235 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4236 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4237 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4238 + *
4239 + * You should have received a copy of the GNU General Public License along
4240 + * with this program; if not, write to the Free Software Foundation, Inc.,
4241 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4242 + *
4243 + *
4244 + **************************************************************************
4245 + * May 2004 P. Sadik.
4246 + *
4247 + * Initial Release
4248 + *
4249 + *
4250 + *
4251 + **************************************************************************
4252 + */
4253 +
4254 +#ifndef __IDT_RC32365_ETH_H__
4255 +#define __IDT_RC32365_ETH_H__
4256 +
4257 +enum
4258 +{
4259 + ETH0_PhysicalAddress = 0x18058000,
4260 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4261 + ETH0_VirtualAddress = 0xb8058000,
4262 +
4263 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4264 +
4265 + ETH1_PhysicalAddress = 0x18060000,
4266 + ETH1_VirtualAddress = 0xb8060000, // Default
4267 +} ;
4268 +
4269 +typedef struct
4270 +{
4271 + u32 ethintfc ;
4272 + u32 ethfifott ;
4273 + u32 etharc ;
4274 + u32 ethhash0 ;
4275 + u32 ethhash1 ;
4276 + u32 ethu0 [4] ; // Reserved.
4277 + u32 ethpfs ;
4278 + u32 ethmcp ;
4279 + u32 eth_u1 [10] ; // Reserved.
4280 + u32 ethspare ;
4281 + u32 eth_u2 [42] ; // Reserved.
4282 + u32 ethsal0 ;
4283 + u32 ethsah0 ;
4284 + u32 ethsal1 ;
4285 + u32 ethsah1 ;
4286 + u32 ethsal2 ;
4287 + u32 ethsah2 ;
4288 + u32 ethsal3 ;
4289 + u32 ethsah3 ;
4290 + u32 ethrbc ;
4291 + u32 ethrpc ;
4292 + u32 ethrupc ;
4293 + u32 ethrfc ;
4294 + u32 ethtbc ;
4295 + u32 ethgpf ;
4296 + u32 eth_u9 [50] ; // Reserved.
4297 + u32 ethmac1 ;
4298 + u32 ethmac2 ;
4299 + u32 ethipgt ;
4300 + u32 ethipgr ;
4301 + u32 ethclrt ;
4302 + u32 ethmaxf ;
4303 + u32 eth_u10 ; // Reserved.
4304 + u32 ethmtest ;
4305 + u32 miimcfg ;
4306 + u32 miimcmd ;
4307 + u32 miimaddr ;
4308 + u32 miimwtd ;
4309 + u32 miimrdd ;
4310 + u32 miimind ;
4311 + u32 eth_u11 ; // Reserved.
4312 + u32 eth_u12 ; // Reserved.
4313 + u32 ethcfsa0 ;
4314 + u32 ethcfsa1 ;
4315 + u32 ethcfsa2 ;
4316 +} volatile *ETH_t;
4317 +
4318 +enum
4319 +{
4320 + ETHINTFC_en_b = 0,
4321 + ETHINTFC_en_m = 0x00000001,
4322 + ETHINTFC_its_b = 1,
4323 + ETHINTFC_its_m = 0x00000002,
4324 + ETHINTFC_rip_b = 2,
4325 + ETHINTFC_rip_m = 0x00000004,
4326 + ETHINTFC_jam_b = 3,
4327 + ETHINTFC_jam_m = 0x00000008,
4328 + ETHINTFC_ovr_b = 4,
4329 + ETHINTFC_ovr_m = 0x00000010,
4330 + ETHINTFC_und_b = 5,
4331 + ETHINTFC_und_m = 0x00000020,
4332 +
4333 + ETHFIFOTT_tth_b = 0,
4334 + ETHFIFOTT_tth_m = 0x0000007f,
4335 +
4336 + ETHARC_pro_b = 0,
4337 + ETHARC_pro_m = 0x00000001,
4338 + ETHARC_am_b = 1,
4339 + ETHARC_am_m = 0x00000002,
4340 + ETHARC_afm_b = 2,
4341 + ETHARC_afm_m = 0x00000004,
4342 + ETHARC_ab_b = 3,
4343 + ETHARC_ab_m = 0x00000008,
4344 +
4345 + ETHSAL_byte5_b = 0,
4346 + ETHSAL_byte5_m = 0x000000ff,
4347 + ETHSAL_byte4_b = 8,
4348 + ETHSAL_byte4_m = 0x0000ff00,
4349 + ETHSAL_byte3_b = 16,
4350 + ETHSAL_byte3_m = 0x00ff0000,
4351 + ETHSAL_byte2_b = 24,
4352 + ETHSAL_byte2_m = 0xff000000,
4353 +
4354 + ETHSAH_byte1_b = 0,
4355 + ETHSAH_byte1_m = 0x000000ff,
4356 + ETHSAH_byte0_b = 8,
4357 + ETHSAH_byte0_m = 0x0000ff00,
4358 +
4359 + ETHGPF_ptv_b = 0,
4360 + ETHGPF_ptv_m = 0x0000ffff,
4361 +
4362 + ETHPFS_pfd_b = 0,
4363 + ETHPFS_pfd_m = 0x00000001,
4364 +
4365 + ETHCFSA0_cfsa4_b = 0,
4366 + ETHCFSA0_cfsa4_m = 0x000000ff,
4367 + ETHCFSA0_cfsa5_b = 8,
4368 + ETHCFSA0_cfsa5_m = 0x0000ff00,
4369 +
4370 + ETHCFSA1_cfsa2_b = 0,
4371 + ETHCFSA1_cfsa2_m = 0x000000ff,
4372 + ETHCFSA1_cfsa3_b = 8,
4373 + ETHCFSA1_cfsa3_m = 0x0000ff00,
4374 +
4375 + ETHCFSA2_cfsa0_b = 0,
4376 + ETHCFSA2_cfsa0_m = 0x000000ff,
4377 + ETHCFSA2_cfsa1_b = 8,
4378 + ETHCFSA2_cfsa1_m = 0x0000ff00,
4379 +
4380 + ETHMAC1_re_b = 0,
4381 + ETHMAC1_re_m = 0x00000001,
4382 + ETHMAC1_paf_b = 1,
4383 + ETHMAC1_paf_m = 0x00000002,
4384 + ETHMAC1_rfc_b = 2,
4385 + ETHMAC1_rfc_m = 0x00000004,
4386 + ETHMAC1_tfc_b = 3,
4387 + ETHMAC1_tfc_m = 0x00000008,
4388 + ETHMAC1_lb_b = 4,
4389 + ETHMAC1_lb_m = 0x00000010,
4390 + ETHMAC1_mr_b = 31,
4391 + ETHMAC1_mr_m = 0x80000000,
4392 +
4393 + ETHMAC2_fd_b = 0,
4394 + ETHMAC2_fd_m = 0x00000001,
4395 + ETHMAC2_flc_b = 1,
4396 + ETHMAC2_flc_m = 0x00000002,
4397 + ETHMAC2_hfe_b = 2,
4398 + ETHMAC2_hfe_m = 0x00000004,
4399 + ETHMAC2_dc_b = 3,
4400 + ETHMAC2_dc_m = 0x00000008,
4401 + ETHMAC2_cen_b = 4,
4402 + ETHMAC2_cen_m = 0x00000010,
4403 + ETHMAC2_pe_b = 5,
4404 + ETHMAC2_pe_m = 0x00000020,
4405 + ETHMAC2_vpe_b = 6,
4406 + ETHMAC2_vpe_m = 0x00000040,
4407 + ETHMAC2_ape_b = 7,
4408 + ETHMAC2_ape_m = 0x00000080,
4409 + ETHMAC2_ppe_b = 8,
4410 + ETHMAC2_ppe_m = 0x00000100,
4411 + ETHMAC2_lpe_b = 9,
4412 + ETHMAC2_lpe_m = 0x00000200,
4413 + ETHMAC2_nb_b = 12,
4414 + ETHMAC2_nb_m = 0x00001000,
4415 + ETHMAC2_bp_b = 13,
4416 + ETHMAC2_bp_m = 0x00002000,
4417 + ETHMAC2_ed_b = 14,
4418 + ETHMAC2_ed_m = 0x00004000,
4419 +
4420 + ETHIPGT_ipgt_b = 0,
4421 + ETHIPGT_ipgt_m = 0x0000007f,
4422 +
4423 + ETHIPGR_ipgr2_b = 0,
4424 + ETHIPGR_ipgr2_m = 0x0000007f,
4425 + ETHIPGR_ipgr1_b = 8,
4426 + ETHIPGR_ipgr1_m = 0x00007f00,
4427 +
4428 + ETHCLRT_maxret_b = 0,
4429 + ETHCLRT_maxret_m = 0x0000000f,
4430 + ETHCLRT_colwin_b = 8,
4431 + ETHCLRT_colwin_m = 0x00003f00,
4432 +
4433 + ETHMAXF_maxf_b = 0,
4434 + ETHMAXF_maxf_m = 0x0000ffff,
4435 +
4436 + ETHMTEST_tb_b = 2,
4437 + ETHMTEST_tb_m = 0x00000004,
4438 +
4439 + ETHMCP_div_b = 0,
4440 + ETHMCP_div_m = 0x000000ff,
4441 +
4442 + MIIMCFG_rsv_b = 0,
4443 + MIIMCFG_rsv_m = 0x0000000c,
4444 +
4445 + MIIMCMD_rd_b = 0,
4446 + MIIMCMD_rd_m = 0x00000001,
4447 + MIIMCMD_scn_b = 1,
4448 + MIIMCMD_scn_m = 0x00000002,
4449 +
4450 + MIIMADDR_regaddr_b = 0,
4451 + MIIMADDR_regaddr_m = 0x0000001f,
4452 + MIIMADDR_phyaddr_b = 8,
4453 + MIIMADDR_phyaddr_m = 0x00001f00,
4454 +
4455 + MIIMWTD_wdata_b = 0,
4456 + MIIMWTD_wdata_m = 0x0000ffff,
4457 +
4458 + MIIMRDD_rdata_b = 0,
4459 + MIIMRDD_rdata_m = 0x0000ffff,
4460 +
4461 + MIIMIND_bsy_b = 0,
4462 + MIIMIND_bsy_m = 0x00000001,
4463 + MIIMIND_scn_b = 1,
4464 + MIIMIND_scn_m = 0x00000002,
4465 + MIIMIND_nv_b = 2,
4466 + MIIMIND_nv_m = 0x00000004,
4467 +
4468 +} ;
4469 +
4470 +/*
4471 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4472 + */
4473 +enum
4474 +{
4475 + ETHRX_fd_b = 0,
4476 + ETHRX_fd_m = 0x00000001,
4477 + ETHRX_ld_b = 1,
4478 + ETHRX_ld_m = 0x00000002,
4479 + ETHRX_rok_b = 2,
4480 + ETHRX_rok_m = 0x00000004,
4481 + ETHRX_fm_b = 3,
4482 + ETHRX_fm_m = 0x00000008,
4483 + ETHRX_mp_b = 4,
4484 + ETHRX_mp_m = 0x00000010,
4485 + ETHRX_bp_b = 5,
4486 + ETHRX_bp_m = 0x00000020,
4487 + ETHRX_vlt_b = 6,
4488 + ETHRX_vlt_m = 0x00000040,
4489 + ETHRX_cf_b = 7,
4490 + ETHRX_cf_m = 0x00000080,
4491 + ETHRX_ovr_b = 8,
4492 + ETHRX_ovr_m = 0x00000100,
4493 + ETHRX_crc_b = 9,
4494 + ETHRX_crc_m = 0x00000200,
4495 + ETHRX_cv_b = 10,
4496 + ETHRX_cv_m = 0x00000400,
4497 + ETHRX_db_b = 11,
4498 + ETHRX_db_m = 0x00000800,
4499 + ETHRX_le_b = 12,
4500 + ETHRX_le_m = 0x00001000,
4501 + ETHRX_lor_b = 13,
4502 + ETHRX_lor_m = 0x00002000,
4503 + ETHRX_ces_b = 14,
4504 + ETHRX_ces_m = 0x00004000,
4505 + ETHRX_length_b = 16,
4506 + ETHRX_length_m = 0xffff0000,
4507 +
4508 + ETHTX_fd_b = 0,
4509 + ETHTX_fd_m = 0x00000001,
4510 + ETHTX_ld_b = 1,
4511 + ETHTX_ld_m = 0x00000002,
4512 + ETHTX_oen_b = 2,
4513 + ETHTX_oen_m = 0x00000004,
4514 + ETHTX_pen_b = 3,
4515 + ETHTX_pen_m = 0x00000008,
4516 + ETHTX_cen_b = 4,
4517 + ETHTX_cen_m = 0x00000010,
4518 + ETHTX_hen_b = 5,
4519 + ETHTX_hen_m = 0x00000020,
4520 + ETHTX_tok_b = 6,
4521 + ETHTX_tok_m = 0x00000040,
4522 + ETHTX_mp_b = 7,
4523 + ETHTX_mp_m = 0x00000080,
4524 + ETHTX_bp_b = 8,
4525 + ETHTX_bp_m = 0x00000100,
4526 + ETHTX_und_b = 9,
4527 + ETHTX_und_m = 0x00000200,
4528 + ETHTX_of_b = 10,
4529 + ETHTX_of_m = 0x00000400,
4530 + ETHTX_ed_b = 11,
4531 + ETHTX_ed_m = 0x00000800,
4532 + ETHTX_ec_b = 12,
4533 + ETHTX_ec_m = 0x00001000,
4534 + ETHTX_lc_b = 13,
4535 + ETHTX_lc_m = 0x00002000,
4536 + ETHTX_td_b = 14,
4537 + ETHTX_td_m = 0x00004000,
4538 + ETHTX_crc_b = 15,
4539 + ETHTX_crc_m = 0x00008000,
4540 + ETHTX_le_b = 16,
4541 + ETHTX_le_m = 0x00010000,
4542 + ETHTX_cc_b = 17,
4543 + ETHTX_cc_m = 0x001E0000,
4544 +} ;
4545 +
4546 +enum
4547 +{
4548 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
4549 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
4550 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
4551 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
4552 +} ;
4553 +
4554 +typedef struct
4555 +{
4556 + u32 ipabmcrx ;
4557 + u32 ipabmctx ;
4558 +}volatile *IPABM_ETH_t;
4559 +#endif //__IDT_RC32365_ETH_H__
4560 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4561 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
4562 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-03-20 14:25:10.000000000 +0100
4563 @@ -0,0 +1,72 @@
4564 +/**************************************************************************
4565 + *
4566 + * BRIEF MODULE DESCRIPTION
4567 + * RC32365/336 Ethernet status checking.
4568 + *
4569 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4570 + *
4571 + * This program is free software; you can redistribute it and/or modify it
4572 + * under the terms of the GNU General Public License as published by the
4573 + * Free Software Foundation; either version 2 of the License, or (at your
4574 + * option) any later version.
4575 + *
4576 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4577 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4578 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4579 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4580 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4581 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4582 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4583 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4584 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4585 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4586 + *
4587 + * You should have received a copy of the GNU General Public License along
4588 + * with this program; if not, write to the Free Software Foundation, Inc.,
4589 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4590 + *
4591 + *
4592 + **************************************************************************
4593 + * May 2004 P. Sadik.
4594 + *
4595 + * Initial Release
4596 + *
4597 + *
4598 + *
4599 + **************************************************************************
4600 + */
4601 +
4602 +#ifndef __IDT_RC32365_ETH_V_H__
4603 +#define __IDT_RC32365_ETH_V_H__
4604 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
4605 +
4606 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
4607 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
4608 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
4609 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
4610 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
4611 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
4612 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
4613 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
4614 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
4615 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
4616 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
4617 +
4618 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
4619 +
4620 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
4621 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
4622 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
4623 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
4624 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
4625 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
4626 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
4627 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
4628 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
4629 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
4630 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
4631 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
4632 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
4633 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
4634 +
4635 +#endif //__IDT_RC32365_ETH_V_H__
4636 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4637 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
4638 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-03-20 14:25:10.000000000 +0100
4639 @@ -0,0 +1,181 @@
4640 +/**************************************************************************
4641 + *
4642 + * BRIEF MODULE DESCRIPTION
4643 + * RC32365/336 GPIO hardware abstraction.
4644 + *
4645 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4646 + *
4647 + * This program is free software; you can redistribute it and/or modify it
4648 + * under the terms of the GNU General Public License as published by the
4649 + * Free Software Foundation; either version 2 of the License, or (at your
4650 + * option) any later version.
4651 + *
4652 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4653 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4654 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4655 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4656 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4657 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4658 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4659 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4660 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4661 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4662 + *
4663 + * You should have received a copy of the GNU General Public License along
4664 + * with this program; if not, write to the Free Software Foundation, Inc.,
4665 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4666 + *
4667 + *
4668 + **************************************************************************
4669 + * May 2004 P. Sadik.
4670 + *
4671 + * Initial Release
4672 + *
4673 + *
4674 + *
4675 + **************************************************************************
4676 + */
4677 +
4678 +#ifndef __IDT_RC32365_GPIO_H__
4679 +#define __IDT_RC32365_GPIO_H__
4680 +
4681 +enum
4682 +{
4683 + GPIO0_PhysicalAddress = 0x18048000,
4684 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
4685 +
4686 + GPIO0_VirtualAddress = 0xb8048000,
4687 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
4688 +} ;
4689 +
4690 +typedef struct
4691 +{
4692 + u32 gpiofunc; /* GPIO Function Register
4693 + * gpiofunc[x]==0 bit = gpio
4694 + * func[x]==1 bit = altfunc
4695 + */
4696 + u32 gpiocfg; /* GPIO Configuration Register
4697 + * gpiocfg[x]==0 bit = input
4698 + * gpiocfg[x]==1 bit = output
4699 + */
4700 + u32 gpiod; /* GPIO Data Register
4701 + * gpiod[x] read/write gpio pinX status
4702 + */
4703 + u32 gpioilevel; /* GPIO Interrupt Status Register
4704 + * interrupt level (see gpioistat)
4705 + */
4706 + u32 gpioistat; /* Gpio Interrupt Status Register
4707 + * istat[x] = (gpiod[x] == level[x])
4708 + * cleared in ISR (STICKY bits)
4709 + */
4710 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
4711 +} volatile * GPIO_t ;
4712 +
4713 +typedef enum
4714 +{
4715 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
4716 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
4717 + GPIO_input_v = 0, // gpiocfg use pin as input.
4718 + GPIO_output_v = 1, // gpiocfg use pin as output.
4719 + GPIO_pin0_b = 0,
4720 + GPIO_pin0_m = 0x00000001,
4721 + GPIO_pin1_b = 1,
4722 + GPIO_pin1_m = 0x00000002,
4723 + GPIO_pin2_b = 2,
4724 + GPIO_pin2_m = 0x00000004,
4725 + GPIO_pin3_b = 3,
4726 + GPIO_pin3_m = 0x00000008,
4727 + GPIO_pin4_b = 4,
4728 + GPIO_pin4_m = 0x00000010,
4729 + GPIO_pin5_b = 5,
4730 + GPIO_pin5_m = 0x00000020,
4731 + GPIO_pin6_b = 6,
4732 + GPIO_pin6_m = 0x00000040,
4733 + GPIO_pin7_b = 7,
4734 + GPIO_pin7_m = 0x00000080,
4735 + GPIO_pin8_b = 8,
4736 + GPIO_pin8_m = 0x00000100,
4737 + GPIO_pin9_b = 9,
4738 + GPIO_pin9_m = 0x00000200,
4739 + GPIO_pin10_b = 10,
4740 + GPIO_pin10_m = 0x00000400,
4741 + GPIO_pin11_b = 11,
4742 + GPIO_pin11_m = 0x00000800,
4743 + GPIO_pin12_b = 12,
4744 + GPIO_pin12_m = 0x00001000,
4745 + GPIO_pin13_b = 13,
4746 + GPIO_pin13_m = 0x00002000,
4747 + GPIO_pin14_b = 14,
4748 + GPIO_pin14_m = 0x00004000,
4749 + GPIO_pin15_b = 15,
4750 + GPIO_pin15_m = 0x00008000,
4751 +
4752 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
4753 +
4754 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
4755 + GPIO_u0sout_m = GPIO_pin0_m,
4756 + GPIO_u0sout_cfg_v = GPIO_output_v,
4757 +
4758 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
4759 + GPIO_u0sinp_m = GPIO_pin1_m,
4760 + GPIO_u0sinp_cfg_v = GPIO_input_v,
4761 +
4762 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
4763 + GPIO_maddr22_m = GPIO_pin2_m,
4764 + GPIO_maddr22_cfg_v = GPIO_output_v,
4765 +
4766 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
4767 + GPIO_maddr23_m = GPIO_pin3_m,
4768 + GPIO_maddr23_cfg_v = GPIO_output_v,
4769 +
4770 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
4771 + GPIO_maddr24_m = GPIO_pin4_m,
4772 + GPIO_maddr24_cfg_v = GPIO_output_v,
4773 +
4774 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
4775 + GPIO_maddr25_m = GPIO_pin5_m,
4776 + GPIO_maddr25_cfg_v = GPIO_output_v,
4777 +
4778 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
4779 + GPIO_rngclk_m = GPIO_pin6_m,
4780 + GPIO_rngclk_cfg_v = GPIO_input_v,
4781 +
4782 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
4783 + GPIO_sdckenp_m = GPIO_pin7_m,
4784 + GPIO_sdckenp_cfg_v = GPIO_output_v,
4785 +
4786 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
4787 + GPIO_cen1_m = GPIO_pin8_m,
4788 + GPIO_cen1_cfg_v = GPIO_output_v,
4789 +
4790 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
4791 + GPIO_cen2_m = GPIO_pin9_m,
4792 + GPIO_cen2_cfg_v = GPIO_output_v,
4793 +
4794 + GPIO_regn_b = GPIO_pin10_b, // reserved.
4795 + GPIO_regn_m = GPIO_pin10_m,
4796 + GPIO_regn_cfg_v = GPIO_output_v,
4797 +
4798 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
4799 + GPIO_iordn_m = GPIO_pin11_m,
4800 + GPIO_iordn_cfg_v = GPIO_output_v,
4801 +
4802 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
4803 + GPIO_iowrn_m = GPIO_pin12_m,
4804 + GPIO_iowrn_cfg_v = GPIO_output_v,
4805 +
4806 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
4807 + GPIO_pcireqn2_m = GPIO_pin13_m,
4808 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
4809 +
4810 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
4811 + GPIO_pcigntn2_m = GPIO_pin14_m,
4812 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
4813 +
4814 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
4815 + GPIO_pcimuintn_m = GPIO_pin15_m,
4816 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
4817 +
4818 +} GPIO_DEFS_t;
4819 +
4820 +#endif //__IDT_RC32365_GPIO_H__
4821 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4822 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
4823 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-03-20 14:25:10.000000000 +0100
4824 @@ -0,0 +1,91 @@
4825 +/**************************************************************************
4826 + *
4827 + * BRIEF MODULE DESCRIPTION
4828 + * Routines to set/clear/toggle GPIO on RC32365
4829 + *
4830 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4831 + *
4832 + * This program is free software; you can redistribute it and/or modify it
4833 + * under the terms of the GNU General Public License as published by the
4834 + * Free Software Foundation; either version 2 of the License, or (at your
4835 + * option) any later version.
4836 + *
4837 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4838 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4839 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4840 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4841 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4842 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4843 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4844 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4845 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4846 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4847 + *
4848 + * You should have received a copy of the GNU General Public License along
4849 + * with this program; if not, write to the Free Software Foundation, Inc.,
4850 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4851 + *
4852 + *
4853 + **************************************************************************
4854 + * May 2004 P. Sadik.
4855 + *
4856 + * Initial Release
4857 + *
4858 + *
4859 + *
4860 + **************************************************************************
4861 + */
4862 +#ifndef __IDT_RC32365_GPIO_V_H__
4863 +#define __IDT_RC32365_GPIO_V_H__
4864 +
4865 +
4866 +#ifdef _LANGUAGE_ASSEMBLY
4867 +#define SET_GPIO(pin) \
4868 + lui t5,0xb804 ; \
4869 + ori t5,t5,0x8000 ; \
4870 + lw t4,8(t5) ; \
4871 + ori t4,t4,pin ; \
4872 + sw t4,8(t5) ;
4873 +
4874 +#define CLEAR_GPIO(pin) \
4875 + lui t5,0xb804 ; \
4876 + ori t5,t5,0x8000 ; \
4877 + lw t4,8(t5) ; \
4878 + lui t6,0xFFFF; \
4879 + ori t6,t6,0xFFFF; \
4880 + xori t6,t6,pin ; \
4881 + and t4,t6 ; \
4882 + sw t4,8(t5) ;
4883 +
4884 +#define TOGGLE_GPIO(pin) \
4885 + lui t5,0xb804 ; \
4886 + ori t5,t5,0x8000 ; \
4887 + lw t4,8(t5) ; \
4888 + xori t4,t4,pin ; \
4889 + sw t4,8(t5) ;
4890 +
4891 +#else // !_LANGUAGE_ASSEMBLY
4892 +#include <asm/rc32300/types.h>
4893 +#include <asm/rc32300/rc32365_gpio.h>
4894 +#include <asm/rc32300/rc32365.h>
4895 +
4896 +static inline void set_gpio(unsigned long pin)
4897 +{
4898 + idt_gpio->gpiod |= pin;
4899 +}
4900 +
4901 +static inline void clear_gpio(unsigned long pin)
4902 +{
4903 + idt_gpio->gpiod &= ~pin;
4904 +}
4905 +static inline void toggle_gpio(unsigned long pin)
4906 +{
4907 + idt_gpio->gpiod ^= pin;
4908 +}
4909 +#define SET_GPIO(pin) set_gpio(pin)
4910 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4911 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4912 +#endif // _LANGUAGE_ASSEMBLY
4913 +
4914 +#endif //__IDT_RC32365_GPIO_V_H__
4915 +
4916 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4917 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
4918 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-03-20 14:25:10.000000000 +0100
4919 @@ -0,0 +1,160 @@
4920 +/**************************************************************************
4921 + *
4922 + * BRIEF MODULE DESCRIPTION
4923 + * Definitions for IDT RC32365 CPU.
4924 + *
4925 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4926 + *
4927 + * This program is free software; you can redistribute it and/or modify it
4928 + * under the terms of the GNU General Public License as published by the
4929 + * Free Software Foundation; either version 2 of the License, or (at your
4930 + * option) any later version.
4931 + *
4932 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4933 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4934 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4935 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4936 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4937 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4938 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4939 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4940 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4941 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4942 + *
4943 + * You should have received a copy of the GNU General Public License along
4944 + * with this program; if not, write to the Free Software Foundation, Inc.,
4945 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4946 + *
4947 + *
4948 + **************************************************************************
4949 + * May 2004 P. Sadik.
4950 + *
4951 + * Initial Release
4952 + *
4953 + *
4954 + *
4955 + **************************************************************************
4956 + */
4957 +
4958 +#ifndef __IDT_RC32365_H__
4959 +#define __IDT_RC32365_H__
4960 +
4961 +extern unsigned int cedar_za;
4962 +
4963 +/* Base address of internal registers */
4964 +#define RC32365_REG_BASE 0x18000000
4965 +
4966 +/* System ID Registers */
4967 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
4968 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
4969 +
4970 +/* Reset Controller */
4971 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
4972 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
4973 +
4974 +/* Device Controller */
4975 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
4976 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
4977 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
4978 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
4979 +#define DEV_REG_OFFSET 0x10
4980 +
4981 +/* SDRAM Controller */
4982 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
4983 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
4984 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
4985 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
4986 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
4987 +
4988 +/* Counters/Timers */
4989 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
4990 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
4991 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
4992 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
4993 +#define TIMER_REG_OFFSET 0x10
4994 +
4995 +/* System Integrity */
4996 +
4997 +/* Interrupt Controller */
4998 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
4999 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
5000 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
5001 +#define IC_GROUP_OFFSET 0x0c
5002 +
5003 +#define NUM_INTR_GROUPS 5
5004 +/*
5005 + * The IRQ mapping is as follows:
5006 + *
5007 + * IRQ Mapped To
5008 + * --- -------------------
5009 + * 0 SW0 (IP0) SW0 intr
5010 + * 1 SW1 (IP1) SW1 intr
5011 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
5012 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
5013 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
5014 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
5015 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
5016 + * 7 Int5 (IP7) CP0 Timer
5017 + *
5018 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5019 + * internally on the RC32365 is routed to the Expansion
5020 + * Interrupt Controller.
5021 + */
5022 +#define MIPS_CPU_TIMER_IRQ 7
5023 +
5024 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
5025 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
5026 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
5027 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5028 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
5029 +
5030 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
5031 +
5032 +/* DMA - see rc32365_dma.h for full list of registers */
5033 +
5034 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5035 +#define DMA_CHAN_OFFSET 0x14
5036 +
5037 +/* GPIO Controller */
5038 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
5039 +
5040 +/* 16550 UARTs */
5041 +#ifdef __MIPSEB__
5042 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5043 +#else
5044 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5045 +#endif
5046 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
5047 +
5048 +/* Ethernet - see rc32365_eth.h for full list of registers */
5049 +
5050 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
5051 +
5052 +#define IDT_CLOCK_MULT 2
5053 +
5054 +/* FLASH (device 1) */
5055 +#define FLASH_BASE 0x08000000
5056 +#define FLASH_SIZE 0x00800000
5057 +
5058 +/* LCD 4-digit display (device 2) */
5059 +#define LCD_DIGIT0 0x0C000003
5060 +#define LCD_DIGIT1 0x0C000002
5061 +#define LCD_DIGIT2 0x0C000001
5062 +#define LCD_DIGIT3 0x0C000000
5063 +
5064 +/* RTC (DS1553) (device 2) */
5065 +#define RTC_BASE 0x0c800000
5066 +/* NVRAM */
5067 +#define NVRAM_BASE RTC_BASE
5068 +#define NVRAM_ENVSIZE_OFF 4
5069 +#define NVRAM_ENVSTART_OFF 32
5070 +
5071 +/* Interrupts routed on 79EB365 board */
5072 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
5073 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
5074 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5075 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5076 +
5077 +#define RAM_SIZE (32 * 1024 * 1024)
5078 +
5079 +#endif //__IDT_RC32365_H__
5080 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5081 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
5082 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-03-20 14:25:10.000000000 +0100
5083 @@ -0,0 +1,515 @@
5084 +/**************************************************************************
5085 + *
5086 + * BRIEF MODULE DESCRIPTION
5087 + * Datatype declaration for IDT 79EB365/336 PCI
5088 + *
5089 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5090 + *
5091 + * This program is free software; you can redistribute it and/or modify it
5092 + * under the terms of the GNU General Public License as published by the
5093 + * Free Software Foundation; either version 2 of the License, or (at your
5094 + * option) any later version.
5095 + *
5096 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5097 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5098 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5099 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5100 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5101 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5102 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5103 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5104 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5105 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5106 + *
5107 + * You should have received a copy of the GNU General Public License along
5108 + * with this program; if not, write to the Free Software Foundation, Inc.,
5109 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5110 + *
5111 + *
5112 + **************************************************************************
5113 + * May 2004 P. Sadik.
5114 + *
5115 + * Initial Release
5116 + *
5117 + *
5118 + *
5119 + **************************************************************************
5120 + */
5121 +
5122 +#ifndef __IDT_RC32365_PCI_H__
5123 +#define __IDT_RC32365_PCI_H__
5124 +
5125 +enum
5126 +{
5127 + PCI0_PhysicalAddress = 0x18068000,
5128 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
5129 +
5130 + PCI0_VirtualAddress = 0xb8068000,
5131 + PCI_VirtualAddress = PCI0_VirtualAddress,
5132 +} ;
5133 +
5134 +enum
5135 +{
5136 + PCI_LbaCount = 4, // Local base addresses.
5137 +} ;
5138 +
5139 +typedef struct
5140 +{
5141 + u32 a ; // Address.
5142 + u32 c ; // Control.
5143 + u32 m ; // mapping.
5144 +} PCI_Map_s ;
5145 +
5146 +typedef struct
5147 +{
5148 + u32 pcic ;
5149 + u32 pcis ;
5150 + u32 pcism ;
5151 + u32 pcicfga ;
5152 + u32 pcicfgd ;
5153 + PCI_Map_s pcilba [PCI_LbaCount] ;
5154 + u32 pcidac ;
5155 + u32 pcidas ;
5156 + u32 pcidasm ;
5157 + u32 pcidad ;
5158 + u32 pcidma8c ;
5159 + u32 pcidma9c ;
5160 + u32 pcitc ;
5161 +} volatile *PCI_t ;
5162 +
5163 +// PCI messaging unit.
5164 +enum
5165 +{
5166 + PCIM_Count = 2,
5167 +} ;
5168 +typedef struct
5169 +{
5170 + u32 pciim [PCIM_Count] ;
5171 + u32 pciom [PCIM_Count] ;
5172 + u32 pciid ;
5173 + u32 pciiic ;
5174 + u32 pciiim ;
5175 + u32 pciiod ;
5176 + u32 pciioic ;
5177 + u32 pciioim ;
5178 +} volatile *PCIM_t ;
5179 +
5180 +/*******************************************************************************
5181 + *
5182 + * PCI Control Register
5183 + *
5184 + ******************************************************************************/
5185 +enum
5186 +{
5187 + PCIC_en_b = 0,
5188 + PCIC_en_m = 0x00000001,
5189 + PCIC_tnr_b = 1,
5190 + PCIC_tnr_m = 0x00000002,
5191 + PCIC_sce_b = 2,
5192 + PCIC_sce_m = 0x00000004,
5193 + PCIC_ien_b = 3,
5194 + PCIC_ien_m = 0x00000008,
5195 + PCIC_aaa_b = 4,
5196 + PCIC_aaa_m = 0x00000010,
5197 + PCIC_eap_b = 5,
5198 + PCIC_eap_m = 0x00000020,
5199 + PCIC_pcim_b = 6,
5200 + PCIC_pcim_m = 0x000001c0,
5201 + PCIC_pcim_disabled_v = 0,
5202 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
5203 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
5204 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
5205 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
5206 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
5207 + PCIC_pcim_reserved6_v = 6,
5208 + PCIC_pcim_reserved7_v = 7,
5209 + PCIC_igm_b = 9,
5210 + PCIC_igm_m = 0x00000200,
5211 +} ;
5212 +
5213 +/*******************************************************************************
5214 + *
5215 + * PCI Status Register
5216 + *
5217 + ******************************************************************************/
5218 +enum {
5219 + PCIS_eed_b = 0,
5220 + PCIS_eed_m = 0x00000001,
5221 + PCIS_wr_b = 1,
5222 + PCIS_wr_m = 0x00000002,
5223 + PCIS_nmi_b = 2,
5224 + PCIS_nmi_m = 0x00000004,
5225 + PCIS_ii_b = 3,
5226 + PCIS_ii_m = 0x00000008,
5227 + PCIS_cwe_b = 4,
5228 + PCIS_cwe_m = 0x00000010,
5229 + PCIS_cre_b = 5,
5230 + PCIS_cre_m = 0x00000020,
5231 + PCIS_mdpe_b = 6,
5232 + PCIS_mdpe_m = 0x00000040,
5233 + PCIS_sta_b = 7,
5234 + PCIS_sta_m = 0x00000080,
5235 + PCIS_rta_b = 8,
5236 + PCIS_rta_m = 0x00000100,
5237 + PCIS_rma_b = 9,
5238 + PCIS_rma_m = 0x00000200,
5239 + PCIS_sse_b = 10,
5240 + PCIS_sse_m = 0x00000400,
5241 + PCIS_ose_b = 11,
5242 + PCIS_ose_m = 0x00000800,
5243 + PCIS_pe_b = 12,
5244 + PCIS_pe_m = 0x00001000,
5245 + PCIS_tae_b = 13,
5246 + PCIS_tae_m = 0x00002000,
5247 + PCIS_rle_b = 14,
5248 + PCIS_rle_m = 0x00004000,
5249 + PCIS_bme_b = 15,
5250 + PCIS_bme_m = 0x00008000,
5251 + PCIS_prd_b = 16,
5252 + PCIS_prd_m = 0x00010000,
5253 + PCIS_rip_b = 17,
5254 + PCIS_rip_m = 0x00020000,
5255 +} ;
5256 +
5257 +/*******************************************************************************
5258 + *
5259 + * PCI Status Mask Register
5260 + *
5261 + ******************************************************************************/
5262 +enum {
5263 + PCISM_eed_b = 0,
5264 + PCISM_eed_m = 0x00000001,
5265 + PCISM_wr_b = 1,
5266 + PCISM_wr_m = 0x00000002,
5267 + PCISM_nmi_b = 2,
5268 + PCISM_nmi_m = 0x00000004,
5269 + PCISM_ii_b = 3,
5270 + PCISM_ii_m = 0x00000008,
5271 + PCISM_cwe_b = 4,
5272 + PCISM_cwe_m = 0x00000010,
5273 + PCISM_cre_b = 5,
5274 + PCISM_cre_m = 0x00000020,
5275 + PCISM_mdpe_b = 6,
5276 + PCISM_mdpe_m = 0x00000040,
5277 + PCISM_sta_b = 7,
5278 + PCISM_sta_m = 0x00000080,
5279 + PCISM_rta_b = 8,
5280 + PCISM_rta_m = 0x00000100,
5281 + PCISM_rma_b = 9,
5282 + PCISM_rma_m = 0x00000200,
5283 + PCISM_sse_b = 10,
5284 + PCISM_sse_m = 0x00000400,
5285 + PCISM_ose_b = 11,
5286 + PCISM_ose_m = 0x00000800,
5287 + PCISM_pe_b = 12,
5288 + PCISM_pe_m = 0x00001000,
5289 + PCISM_tae_b = 13,
5290 + PCISM_tae_m = 0x00002000,
5291 + PCISM_rle_b = 14,
5292 + PCISM_rle_m = 0x00004000,
5293 + PCISM_bme_b = 15,
5294 + PCISM_bme_m = 0x00008000,
5295 + PCISM_prd_b = 16,
5296 + PCISM_prd_m = 0x00010000,
5297 + PCISM_rip_b = 17,
5298 + PCISM_rip_m = 0x00020000,
5299 +} ;
5300 +
5301 +/*******************************************************************************
5302 + *
5303 + * PCI Configuration Address Register
5304 + *
5305 + ******************************************************************************/
5306 +enum {
5307 + PCICFGA_reg_b = 2,
5308 + PCICFGA_reg_m = 0x000000fc,
5309 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
5310 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
5311 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
5312 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
5313 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
5314 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
5315 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
5316 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
5317 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5318 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
5319 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
5320 + PCICFGA_reg_pba0m_v = 0x48>>2,
5321 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
5322 + PCICFGA_reg_pba1m_v = 0x50>>2,
5323 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
5324 + PCICFGA_reg_pba2m_v = 0x58>>2,
5325 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
5326 + PCICFGA_reg_pba3m_v = 0x60>>2,
5327 + PCICFGA_reg_pmgt_v = 0x64>>2,
5328 + PCICFGA_func_b = 8,
5329 + PCICFGA_func_m = 0x00000700,
5330 + PCICFGA_dev_b = 11,
5331 + PCICFGA_dev_m = 0x0000f800,
5332 + PCICFGA_dev_internal_v = 0,
5333 + PCICFGA_bus_b = 16,
5334 + PCICFGA_bus_m = 0x00ff0000,
5335 + PCICFGA_bus_type0_v = 0, //local bus
5336 + PCICFGA_en_b = 31, // read only
5337 + PCICFGA_en_m = 0x80000000,
5338 +} ;
5339 +
5340 +enum {
5341 + PCFGID_vendor_b = 0,
5342 + PCFGID_vendor_m = 0x0000ffff,
5343 + PCFGID_vendor_IDT_v = 0x111d,
5344 + PCFGID_device_b = 16,
5345 + PCFGID_device_m = 0xffff0000,
5346 + PCFGID_device_Acaciade_v = 0x0207,
5347 +
5348 + PCFG04_command_ioena_b = 1,
5349 + PCFG04_command_ioena_m = 0x00000001,
5350 + PCFG04_command_memena_b = 2,
5351 + PCFG04_command_memena_m = 0x00000002,
5352 + PCFG04_command_bmena_b = 3,
5353 + PCFG04_command_bmena_m = 0x00000004,
5354 + PCFG04_command_mwinv_b = 5,
5355 + PCFG04_command_mwinv_m = 0x00000010,
5356 + PCFG04_command_parena_b = 7,
5357 + PCFG04_command_parena_m = 0x00000040,
5358 + PCFG04_command_serrena_b = 9,
5359 + PCFG04_command_serrena_m = 0x00000100,
5360 + PCFG04_command_fastbbena_b = 10,
5361 + PCFG04_command_fastbbena_m = 0x00000200,
5362 + PCFG04_status_b = 16,
5363 + PCFG04_status_m = 0xffff0000,
5364 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
5365 + PCFG04_status_66MHz_m = 0x00200000,
5366 + PCFG04_status_fbb_b = 23,
5367 + PCFG04_status_fbb_m = 0x00800000,
5368 + PCFG04_status_mdpe_b = 24,
5369 + PCFG04_status_mdpe_m = 0x01000000,
5370 + PCFG04_status_dst_b = 25,
5371 + PCFG04_status_dst_m = 0x06000000,
5372 + PCFG04_status_sta_b = 27,
5373 + PCFG04_status_sta_m = 0x08000000,
5374 + PCFG04_status_rta_b = 28,
5375 + PCFG04_status_rta_m = 0x10000000,
5376 + PCFG04_status_rma_b = 29,
5377 + PCFG04_status_rma_m = 0x20000000,
5378 + PCFG04_status_sse_b = 30,
5379 + PCFG04_status_sse_m = 0x40000000,
5380 + PCFG04_status_pe_b = 31,
5381 + PCFG04_status_pe_m = 0x40000000,
5382 +
5383 + PCFG08_revId_b = 0,
5384 + PCFG08_revId_m = 0x000000ff,
5385 + PCFG08_classCode_b = 0,
5386 + PCFG08_classCode_m = 0xffffff00,
5387 + PCFG08_classCode_bridge_v = 06,
5388 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
5389 + PCFG0C_cacheline_b = 0,
5390 + PCFG0C_cacheline_m = 0x000000ff,
5391 + PCFG0C_masterLatency_b = 8,
5392 + PCFG0C_masterLatency_m = 0x0000ff00,
5393 + PCFG0C_headerType_b = 16,
5394 + PCFG0C_headerType_m = 0x00ff0000,
5395 + PCFG0C_bist_b = 24,
5396 + PCFG0C_bist_m = 0xff000000,
5397 +
5398 + PCIPBA_msi_b = 0,
5399 + PCIPBA_msi_m = 0x00000001,
5400 + PCIPBA_p_b = 3,
5401 + PCIPBA_p_m = 0x00000004,
5402 + PCIPBA_baddr_b = 8,
5403 + PCIPBA_baddr_m = 0xffffff00,
5404 +
5405 + PCFGSS_vendorId_b = 0,
5406 + PCFGSS_vendorId_m = 0x0000ffff,
5407 + PCFGSS_id_b = 16,
5408 + PCFGSS_id_m = 0xffff0000,
5409 +
5410 + PCFG3C_interruptLine_b = 0,
5411 + PCFG3C_interruptLine_m = 0x000000ff,
5412 + PCFG3C_interruptPin_b = 8,
5413 + PCFG3C_interruptPin_m = 0x0000ff00,
5414 + PCFG3C_minGrant_b = 16,
5415 + PCFG3C_minGrant_m = 0x00ff0000,
5416 + PCFG3C_maxLat_b = 24,
5417 + PCFG3C_maxLat_m = 0xff000000,
5418 +
5419 + PCIPBAC_msi_b = 0,
5420 + PCIPBAC_msi_m = 0x00000001,
5421 + PCIPBAC_p_b = 1,
5422 + PCIPBAC_p_m = 0x00000002,
5423 + PCIPBAC_size_b = 2,
5424 + PCIPBAC_size_m = 0x0000007c,
5425 + PCIPBAC_sb_b = 7,
5426 + PCIPBAC_sb_m = 0x00000080,
5427 + PCIPBAC_pp_b = 8,
5428 + PCIPBAC_pp_m = 0x00000100,
5429 + PCIPBAC_mr_b = 9,
5430 + PCIPBAC_mr_m = 0x00000600,
5431 + PCIPBAC_mr_read_v =0, //no prefetching
5432 + PCIPBAC_mr_readLine_v =1,
5433 + PCIPBAC_mr_readMult_v =2,
5434 + PCIPBAC_mrl_b = 11,
5435 + PCIPBAC_mrl_m = 0x00000800,
5436 + PCIPBAC_mrm_b = 12,
5437 + PCIPBAC_mrm_m = 0x00001000,
5438 + PCIPBAC_trp_b = 13,
5439 + PCIPBAC_trp_m = 0x00002000,
5440 +
5441 + PCFG40_trdyTimeout_b = 0,
5442 + PCFG40_trdyTimeout_m = 0x000000ff,
5443 + PCFG40_retryLim_b = 8,
5444 + PCFG40_retryLim_m = 0x0000ff00,
5445 +};
5446 +
5447 +/*******************************************************************************
5448 + *
5449 + * PCI Local Base Address [0|1|2|3] Register
5450 + *
5451 + ******************************************************************************/
5452 +enum {
5453 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
5454 + PCILBA_baddr_m = 0xffffff00,
5455 +} ;
5456 +/*******************************************************************************
5457 + *
5458 + * PCI Local Base Address Control Register
5459 + *
5460 + ******************************************************************************/
5461 +enum {
5462 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
5463 + PCILBAC_msi_m = 0x00000001,
5464 + PCILBAC_msi_mem_v = 0,
5465 + PCILBAC_msi_io_v = 1,
5466 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
5467 + PCILBAC_size_m = 0x0000007c,
5468 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
5469 + PCILBAC_sb_m = 0x00000080,
5470 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
5471 + PCILBAC_rt_m = 0x00000100,
5472 + PCILBAC_rt_noprefetch_v = 0, // mem read
5473 + PCILBAC_rt_prefetch_v = 1, // mem readline
5474 +} ;
5475 +
5476 +/*******************************************************************************
5477 + *
5478 + * PCI Local Base Address [0|1|2|3] Mapping Register
5479 + *
5480 + ******************************************************************************/
5481 +enum {
5482 + PCILBAM_maddr_b = 8,
5483 + PCILBAM_maddr_m = 0xffffff00,
5484 +} ;
5485 +
5486 +/*******************************************************************************
5487 + *
5488 + * PCI Decoupled Access Control Register
5489 + *
5490 + ******************************************************************************/
5491 +enum {
5492 + PCIDAC_den_b = 0,
5493 + PCIDAC_den_m = 0x00000001,
5494 +} ;
5495 +
5496 +/*******************************************************************************
5497 + *
5498 + * PCI Decoupled Access Status Register
5499 + *
5500 + ******************************************************************************/
5501 +enum {
5502 + PCIDAS_d_b = 0,
5503 + PCIDAS_d_m = 0x00000001,
5504 + PCIDAS_b_b = 1,
5505 + PCIDAS_b_m = 0x00000002,
5506 + PCIDAS_e_b = 2,
5507 + PCIDAS_e_m = 0x00000004,
5508 + PCIDAS_ofe_b = 3,
5509 + PCIDAS_ofe_m = 0x00000008,
5510 + PCIDAS_off_b = 4,
5511 + PCIDAS_off_m = 0x00000010,
5512 + PCIDAS_ife_b = 5,
5513 + PCIDAS_ife_m = 0x00000020,
5514 + PCIDAS_iff_b = 6,
5515 + PCIDAS_iff_m = 0x00000040,
5516 +} ;
5517 +
5518 +/*******************************************************************************
5519 + *
5520 + * PCI DMA Channel 8 Configuration Register
5521 + *
5522 + ******************************************************************************/
5523 +enum
5524 +{
5525 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
5526 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
5527 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
5528 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
5529 +} ;
5530 +
5531 +/*******************************************************************************
5532 + *
5533 + * PCI DMA Channel 9 Configuration Register
5534 + *
5535 + ******************************************************************************/
5536 +enum
5537 +{
5538 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
5539 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
5540 +} ;
5541 +
5542 +/*******************************************************************************
5543 + *
5544 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5545 + *
5546 + ******************************************************************************/
5547 +enum {
5548 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
5549 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
5550 + // These are for reads (DMA channel 8)
5551 + PCIDMAD_devcmd_mr_v = 0, //memory read
5552 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
5553 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
5554 + PCIDMAD_devcmd_ior_v = 3, //I/O read
5555 + // These are for writes (DMA channel 9)
5556 + PCIDMAD_devcmd_mw_v = 0, //memory write
5557 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
5558 + PCIDMAD_devcmd_iow_v = 3, //I/O write
5559 +
5560 + // Swap byte field applies to both DMA channel 8 and 9
5561 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
5562 + PCIDMAD_sb_m = 0x01000000, // swap byte field
5563 +} ;
5564 +
5565 +
5566 +/*******************************************************************************
5567 + *
5568 + * PCI Target Control Register
5569 + *
5570 + ******************************************************************************/
5571 +enum
5572 +{
5573 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
5574 + PCITC_rtimer_m = 0x000000ff,
5575 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
5576 + PCITC_dtimer_m = 0x0000ff00,
5577 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
5578 + PCITC_rdr_m = 0x00040000,
5579 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
5580 + PCITC_ddt_m = 0x00080000,
5581 +} ;
5582 +/*******************************************************************************
5583 + *
5584 + * PCI messaging unit [applies to both inbound and outbound registers ]
5585 + *
5586 + ******************************************************************************/
5587 +enum
5588 +{
5589 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5590 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
5591 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5592 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
5593 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5594 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
5595 +};
5596 +
5597 +
5598 +#endif // __IDT_RC32365_PCI_H__
5599 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5600 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
5601 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-03-20 14:25:10.000000000 +0100
5602 @@ -0,0 +1,217 @@
5603 +/**************************************************************************
5604 + *
5605 + * BRIEF MODULE DESCRIPTION
5606 + * PCI header values for IDT 79EB365/336
5607 + *
5608 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5609 + *
5610 + * This program is free software; you can redistribute it and/or modify it
5611 + * under the terms of the GNU General Public License as published by the
5612 + * Free Software Foundation; either version 2 of the License, or (at your
5613 + * option) any later version.
5614 + *
5615 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5616 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5617 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5618 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5619 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5620 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5621 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5622 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5623 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5624 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5625 + *
5626 + * You should have received a copy of the GNU General Public License along
5627 + * with this program; if not, write to the Free Software Foundation, Inc.,
5628 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5629 + *
5630 + *
5631 + **************************************************************************
5632 + * May 2004 P. Sadik.
5633 + *
5634 + * Initial Release
5635 + *
5636 + *
5637 + *
5638 + **************************************************************************
5639 + */
5640 +
5641 +#ifndef __IDT_RC32365_PCI_V_H__
5642 +#define __IDT_RC32365_PCI_V_H__
5643 +
5644 +
5645 +#define PCI_MSG_VirtualAddress 0xB806C010
5646 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5647 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5648 +
5649 +#define PCIM_SHFT 0x6
5650 +#define PCIM_BIT_LEN 0x7
5651 +#define PCIM_H_EA 0x3
5652 +#define PCIM_H_IA_FIX 0x4
5653 +#define PCIM_H_IA_RR 0x5
5654 +
5655 +#define PCI_ADDR_START 0x50000000
5656 +
5657 +#define CPUTOPCI_MEM_WIN 0x02000000
5658 +#define CPUTOPCI_IO_WIN 0x00100000
5659 +#define PCILBA_SIZE_SHFT 2
5660 +#define PCILBA_SIZE_MASK 0x1F
5661 +#define SIZE_256MB 0x1C
5662 +#define SIZE_128MB 0x1B
5663 +#define SIZE_64MB 0x1A
5664 +#define SIZE_32MB 0x19
5665 +#define SIZE_16MB 0x18
5666 +#define SIZE_4MB 0x16
5667 +#define SIZE_2MB 0x15
5668 +#define SIZE_1MB 0x14
5669 +#define CEDAR_CONFIG0_ADDR 0x80000000
5670 +#define CEDAR_CONFIG1_ADDR 0x80000004
5671 +#define CEDAR_CONFIG2_ADDR 0x80000008
5672 +#define CEDAR_CONFIG3_ADDR 0x8000000C
5673 +#define CEDAR_CONFIG4_ADDR 0x80000010
5674 +#define CEDAR_CONFIG5_ADDR 0x80000014
5675 +#define CEDAR_CONFIG6_ADDR 0x80000018
5676 +#define CEDAR_CONFIG7_ADDR 0x8000001C
5677 +#define CEDAR_CONFIG8_ADDR 0x80000020
5678 +#define CEDAR_CONFIG9_ADDR 0x80000024
5679 +#define CEDAR_CONFIG10_ADDR 0x80000028
5680 +#define CEDAR_CONFIG11_ADDR 0x8000002C
5681 +#define CEDAR_CONFIG12_ADDR 0x80000030
5682 +#define CEDAR_CONFIG13_ADDR 0x80000034
5683 +#define CEDAR_CONFIG14_ADDR 0x80000038
5684 +#define CEDAR_CONFIG15_ADDR 0x8000003C
5685 +#define CEDAR_CONFIG16_ADDR 0x80000040
5686 +#define CEDAR_CONFIG17_ADDR 0x80000044
5687 +#define CEDAR_CONFIG18_ADDR 0x80000048
5688 +#define CEDAR_CONFIG19_ADDR 0x8000004C
5689 +#define CEDAR_CONFIG20_ADDR 0x80000050
5690 +#define CEDAR_CONFIG21_ADDR 0x80000054
5691 +#define CEDAR_CONFIG22_ADDR 0x80000058
5692 +#define CEDAR_CONFIG23_ADDR 0x8000005C
5693 +#define CEDAR_CONFIG24_ADDR 0x80000060
5694 +#define CEDAR_CONFIG25_ADDR 0x80000064
5695 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
5696 + PCFG04_command_memena_m | \
5697 + PCFG04_command_bmena_m | \
5698 + PCFG04_command_mwinv_m | \
5699 + PCFG04_command_parena_m | \
5700 + PCFG04_command_serrena_m )
5701 +
5702 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
5703 + PCFG04_status_sta_m | \
5704 + PCFG04_status_rta_m | \
5705 + PCFG04_status_rma_m | \
5706 + PCFG04_status_sse_m | \
5707 + PCFG04_status_pe_m)
5708 +
5709 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
5710 + CEDAR_CMD)
5711 +
5712 +#define CEDAR_REVID 0
5713 +#define CEDAR_CLASS_CODE 0
5714 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
5715 + CEDAR_REVID)
5716 +
5717 +#define CEDAR_CACHE_LINE_SIZE 4
5718 +#define CEDAR_MASTER_LAT 0x3c
5719 +#define CEDAR_HEADER_TYPE 0
5720 +#define CEDAR_BIST 0
5721 +
5722 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
5723 + (CEDAR_HEADER_TYPE << 16) | \
5724 + (CEDAR_MASTER_LAT << 8) | \
5725 + CEDAR_CACHE_LINE_SIZE)
5726 +
5727 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
5728 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
5729 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
5730 + internal Registers */
5731 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
5732 +
5733 +#define CEDAR_CNFG4 CEDAR_BAR0
5734 +#define CEDAR_CNFG5 CEDAR_BAR1
5735 +#define CEDAR_CNFG6 CEDAR_BAR2
5736 +#define CEDAR_CNFG7 CEDAR_BAR3
5737 +
5738 +#define CEDAR_SUBSYS_VENDOR_ID 0
5739 +#define CEDAR_SUBSYSTEM_ID 0
5740 +#define CEDAR_CNFG8 0
5741 +#define CEDAR_CNFG9 0
5742 +#define CEDAR_CNFG10 0
5743 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5744 + CEDAR_SUBSYSTEM_ID)
5745 +#define CEDAR_INT_LINE 1
5746 +#define CEDAR_INT_PIN 1
5747 +#define CEDAR_MIN_GNT 8
5748 +#define CEDAR_MAX_LAT 0x38
5749 +#define CEDAR_CNFG12 0
5750 +#define CEDAR_CNFG13 0
5751 +#define CEDAR_CNFG14 0
5752 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
5753 + (CEDAR_MIN_GNT << 16) | \
5754 + (CEDAR_INT_PIN << 8) | \
5755 + CEDAR_INT_LINE)
5756 +#define CEDAR_RETRY_LIMIT 0x80
5757 +#define CEDAR_TRDY_LIMIT 0x80
5758 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
5759 + CEDAR_TRDY_LIMIT)
5760 +#define PCI_PBAxC_R 0x0
5761 +#define PCI_PBAxC_RL 0x1
5762 +#define PCI_PBAxC_RM 0x2
5763 +#define SIZE_SHFT 2
5764 +#ifdef __MIPSEB__
5765 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5766 + PCIPBAC_pp_m | \
5767 + PCIPBAC_sb_m | \
5768 + (SIZE_128MB << SIZE_SHFT) | \
5769 + PCIPBAC_p_m)
5770 +#else
5771 +
5772 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5773 + PCIPBAC_pp_m | \
5774 + (SIZE_128MB << SIZE_SHFT) | \
5775 + PCIPBAC_p_m)
5776 +#endif
5777 +#define CEDAR_CNFG17 CEDAR_PBA0C
5778 +#define CEDAR_PBA0M 0x0
5779 +#define CEDAR_CNFG18 CEDAR_PBA0M
5780 +
5781 +#ifdef __MIPSEB__
5782 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5783 + PCIPBAC_sb_m | \
5784 + PCIPBAC_msi_m)
5785 +#else
5786 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5787 + PCIPBAC_msi_m)
5788 +#endif
5789 +#define CEDAR_CNFG19 CEDAR_PBA1C
5790 +#define CEDAR_PBA1M 0x0
5791 +#define CEDAR_CNFG20 CEDAR_PBA1M
5792 +
5793 +#ifdef __MIPSEB__
5794 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5795 + PCIPBAC_sb_m | \
5796 + PCIPBAC_msi_m)
5797 +#else
5798 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5799 + PCIPBAC_msi_m)
5800 +#endif
5801 +
5802 +#define CEDAR_CNFG21 CEDAR_PBA2C
5803 +#define CEDAR_PBA2M 0x18000000
5804 +#define CEDAR_CNFG22 CEDAR_PBA2M
5805 +
5806 +#ifdef __MIPSEB__
5807 +#define CEDAR_PBA3C PCIPBAC_sb_m
5808 +#else
5809 +#define CEDAR_PBA3C 0
5810 +#endif
5811 +
5812 +#define CEDAR_CNFG23 CEDAR_PBA3C
5813 +#define CEDAR_PBA3M 0
5814 +#define CEDAR_CNFG24 CEDAR_PBA3M
5815 +
5816 +#define PCITC_DTIMER_VAL 8
5817 +#define PCITC_RTIMER_VAL 0x10
5818 +
5819 +#endif //__IDT_RC32365_PCI_V_H__
5820 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5821 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
5822 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-03-20 14:25:10.000000000 +0100
5823 @@ -0,0 +1,205 @@
5824 +/**************************************************************************
5825 + *
5826 + * BRIEF MODULE DESCRIPTION
5827 + * DMA register definition
5828 + *
5829 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5830 + *
5831 + * This program is free software; you can redistribute it and/or modify it
5832 + * under the terms of the GNU General Public License as published by the
5833 + * Free Software Foundation; either version 2 of the License, or (at your
5834 + * option) any later version.
5835 + *
5836 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5837 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5838 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5839 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5840 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5841 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5842 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5843 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5844 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5845 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5846 + *
5847 + * You should have received a copy of the GNU General Public License along
5848 + * with this program; if not, write to the Free Software Foundation, Inc.,
5849 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5850 + *
5851 + *
5852 + **************************************************************************
5853 + * May 2004 rkt, neb
5854 + *
5855 + * Initial Release
5856 + *
5857 + *
5858 + *
5859 + **************************************************************************
5860 + */
5861 +
5862 +#ifndef __IDT_DMA_H__
5863 +#define __IDT_DMA_H__
5864 +
5865 +enum
5866 +{
5867 + DMA0_PhysicalAddress = 0x18040000,
5868 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5869 +
5870 + DMA0_VirtualAddress = 0xb8040000,
5871 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5872 +} ;
5873 +
5874 +/*
5875 + * DMA descriptor (in physical memory).
5876 + */
5877 +
5878 +typedef struct DMAD_s
5879 +{
5880 + u32 control ; // Control. use DMAD_*
5881 + u32 ca ; // Current Address.
5882 + u32 devcs ; // Device control and status.
5883 + u32 link ; // Next descriptor in chain.
5884 +} volatile *DMAD_t ;
5885 +
5886 +enum
5887 +{
5888 + DMAD_size = sizeof (struct DMAD_s),
5889 + DMAD_count_b = 0, // in DMAD_t -> control
5890 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5891 + DMAD_ds_b = 20, // in DMAD_t -> control
5892 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5893 + DMAD_ds_ethRcv0_v = 0,
5894 + DMAD_ds_ethXmt0_v = 0,
5895 + DMAD_ds_memToFifo_v = 0,
5896 + DMAD_ds_fifoToMem_v = 0,
5897 + DMAD_ds_pciToMem_v = 0,
5898 + DMAD_ds_memToPci_v = 0,
5899 +
5900 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5901 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5902 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5903 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5904 + DMAD_devcmd_word_v = 2, //memory-to-memory
5905 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5906 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5907 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5908 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5909 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5910 + DMAD_cof_b = 25, // chain on finished
5911 + DMAD_cof_m = 0x02000000, //
5912 + DMAD_cod_b = 26, // chain on done
5913 + DMAD_cod_m = 0x04000000, //
5914 + DMAD_iof_b = 27, // interrupt on finished
5915 + DMAD_iof_m = 0x08000000, //
5916 + DMAD_iod_b = 28, // interrupt on done
5917 + DMAD_iod_m = 0x10000000, //
5918 + DMAD_t_b = 29, // terminated
5919 + DMAD_t_m = 0x20000000, //
5920 + DMAD_d_b = 30, // done
5921 + DMAD_d_m = 0x40000000, //
5922 + DMAD_f_b = 31, // finished
5923 + DMAD_f_m = 0x80000000, //
5924 +} ;
5925 +
5926 +/*
5927 + * DMA register (within Internal Register Map).
5928 + */
5929 +
5930 +struct DMA_Chan_s
5931 +{
5932 + u32 dmac ; // Control.
5933 + u32 dmas ; // Status.
5934 + u32 dmasm ; // Mask.
5935 + u32 dmadptr ; // Descriptor pointer.
5936 + u32 dmandptr ; // Next descriptor pointer.
5937 +};
5938 +
5939 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5940 +
5941 +//DMA_Channels use DMACH_count instead
5942 +
5943 +enum
5944 +{
5945 + DMAC_run_b = 0, //
5946 + DMAC_run_m = 0x00000001, //
5947 + DMAC_dm_b = 1, // done mask
5948 + DMAC_dm_m = 0x00000002, //
5949 + DMAC_mode_b = 2, //
5950 + DMAC_mode_m = 0x0000000c, //
5951 + DMAC_mode_auto_v = 0,
5952 + DMAC_mode_burst_v = 1,
5953 + DMAC_mode_transfer_v = 2, //usually used
5954 + DMAC_mode_reserved_v = 3,
5955 + DMAC_a_b = 4, //
5956 + DMAC_a_m = 0x00000010, //
5957 +
5958 + DMAS_f_b = 0, // finished (sticky)
5959 + DMAS_f_m = 0x00000001, //
5960 + DMAS_d_b = 1, // done (sticky)
5961 + DMAS_d_m = 0x00000002, //
5962 + DMAS_c_b = 2, // chain (sticky)
5963 + DMAS_c_m = 0x00000004, //
5964 + DMAS_e_b = 3, // error (sticky)
5965 + DMAS_e_m = 0x00000008, //
5966 + DMAS_h_b = 4, // halt (sticky)
5967 + DMAS_h_m = 0x00000010, //
5968 +
5969 + DMASM_f_b = 0, // finished (1=mask)
5970 + DMASM_f_m = 0x00000001, //
5971 + DMASM_d_b = 1, // done (1=mask)
5972 + DMASM_d_m = 0x00000002, //
5973 + DMASM_c_b = 2, // chain (1=mask)
5974 + DMASM_c_m = 0x00000004, //
5975 + DMASM_e_b = 3, // error (1=mask)
5976 + DMASM_e_m = 0x00000008, //
5977 + DMASM_h_b = 4, // halt (1=mask)
5978 + DMASM_h_m = 0x00000010, //
5979 +} ;
5980 +
5981 +/*
5982 + * DMA channel definitions
5983 + */
5984 +
5985 +enum
5986 +{
5987 + DMACH_ethRcv0 = 0,
5988 + DMACH_ethXmt0 = 1,
5989 + DMACH_memToFifo = 2,
5990 + DMACH_fifoToMem = 3,
5991 + DMACH_pciToMem = 4,
5992 + DMACH_memToPci = 5,
5993 +
5994 + DMACH_count //must be last
5995 +};
5996 +
5997 +
5998 +typedef struct DMAC_s
5999 +{
6000 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
6001 +} volatile *DMA_t ;
6002 +
6003 +
6004 +/*
6005 + * External DMA parameters
6006 +*/
6007 +
6008 +enum
6009 +{
6010 + DMADEVCMD_ts_b = 0, // ts field in devcmd
6011 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
6012 + DMADEVCMD_ts_byte_v = 0,
6013 + DMADEVCMD_ts_halfword_v = 1,
6014 + DMADEVCMD_ts_word_v = 2,
6015 + DMADEVCMD_ts_2word_v = 3,
6016 + DMADEVCMD_ts_4word_v = 4,
6017 + DMADEVCMD_ts_6word_v = 5,
6018 + DMADEVCMD_ts_8word_v = 6,
6019 + DMADEVCMD_ts_16word_v = 7
6020 +};
6021 +
6022 +
6023 +#endif // __IDT_DMA_H__
6024 +
6025 +
6026 +
6027 +
6028 +
6029 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6030 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
6031 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-03-20 14:25:10.000000000 +0100
6032 @@ -0,0 +1,89 @@
6033 +/**************************************************************************
6034 + *
6035 + * BRIEF MODULE DESCRIPTION
6036 + * Definitions for DMA controller.
6037 + *
6038 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6039 + *
6040 + * This program is free software; you can redistribute it and/or modify it
6041 + * under the terms of the GNU General Public License as published by the
6042 + * Free Software Foundation; either version 2 of the License, or (at your
6043 + * option) any later version.
6044 + *
6045 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6046 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6047 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6048 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6049 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6050 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6051 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6052 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6053 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6054 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6055 + *
6056 + * You should have received a copy of the GNU General Public License along
6057 + * with this program; if not, write to the Free Software Foundation, Inc.,
6058 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6059 + *
6060 + *
6061 + **************************************************************************
6062 + * May 2004 rkt, neb.
6063 + *
6064 + * Initial Release
6065 + *
6066 + *
6067 + *
6068 + **************************************************************************
6069 + */
6070 +
6071 +#ifndef __IDT_DMA_V_H__
6072 +#define __IDT_DMA_V_H__
6073 +
6074 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
6075 +#include <asm/idt-boards/rc32434/rc32434.h>
6076 +
6077 +#define DMA_CHAN_OFFSET 0x14
6078 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6079 +#define DMA_COUNT(count) \
6080 + ((count) & DMAD_count_m)
6081 +
6082 +#define DMA_HALT_TIMEOUT 500
6083 +
6084 +
6085 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6086 +{
6087 + int timeout=1;
6088 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6089 + rc32434_writel(0, &ch->dmac);
6090 +
6091 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6092 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6093 + rc32434_writel(0, &ch->dmas);
6094 + break;
6095 + }
6096 + }
6097 +
6098 + }
6099 +
6100 + return timeout ? 0 : 1;
6101 +}
6102 +
6103 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6104 +{
6105 + rc32434_writel(0, &ch->dmandptr);
6106 + rc32434_writel(dma_addr, &ch->dmadptr);
6107 +}
6108 +
6109 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6110 +{
6111 + rc32434_writel(dma_addr, &ch->dmandptr);
6112 +}
6113 +
6114 +#endif // __IDT_DMA_V_H__
6115 +
6116 +
6117 +
6118 +
6119 +
6120 +
6121 +
6122 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6123 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
6124 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
6125 @@ -0,0 +1,333 @@
6126 +/**************************************************************************
6127 + *
6128 + * BRIEF MODULE DESCRIPTION
6129 + * Ethernet register definition
6130 + *
6131 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6132 + *
6133 + * This program is free software; you can redistribute it and/or modify it
6134 + * under the terms of the GNU General Public License as published by the
6135 + * Free Software Foundation; either version 2 of the License, or (at your
6136 + * option) any later version.
6137 + *
6138 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6139 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6140 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6141 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6142 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6143 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6144 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6145 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6146 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6147 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6148 + *
6149 + * You should have received a copy of the GNU General Public License along
6150 + * with this program; if not, write to the Free Software Foundation, Inc.,
6151 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6152 + *
6153 + *
6154 + **************************************************************************
6155 + * May 2004 rkt, neb.
6156 + *
6157 + * Initial Release
6158 + *
6159 + *
6160 + *
6161 + **************************************************************************
6162 + */
6163 +
6164 +#ifndef __IDT_ETH_H__
6165 +#define __IDT_ETH_H__
6166 +
6167 +
6168 +enum
6169 +{
6170 + ETH0_PhysicalAddress = 0x18060000,
6171 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
6172 +
6173 + ETH0_VirtualAddress = 0xb8060000,
6174 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
6175 +} ;
6176 +
6177 +typedef struct
6178 +{
6179 + u32 ethintfc ;
6180 + u32 ethfifott ;
6181 + u32 etharc ;
6182 + u32 ethhash0 ;
6183 + u32 ethhash1 ;
6184 + u32 ethu0 [4] ; // Reserved.
6185 + u32 ethpfs ;
6186 + u32 ethmcp ;
6187 + u32 eth_u1 [10] ; // Reserved.
6188 + u32 ethspare ;
6189 + u32 eth_u2 [42] ; // Reserved.
6190 + u32 ethsal0 ;
6191 + u32 ethsah0 ;
6192 + u32 ethsal1 ;
6193 + u32 ethsah1 ;
6194 + u32 ethsal2 ;
6195 + u32 ethsah2 ;
6196 + u32 ethsal3 ;
6197 + u32 ethsah3 ;
6198 + u32 ethrbc ;
6199 + u32 ethrpc ;
6200 + u32 ethrupc ;
6201 + u32 ethrfc ;
6202 + u32 ethtbc ;
6203 + u32 ethgpf ;
6204 + u32 eth_u9 [50] ; // Reserved.
6205 + u32 ethmac1 ;
6206 + u32 ethmac2 ;
6207 + u32 ethipgt ;
6208 + u32 ethipgr ;
6209 + u32 ethclrt ;
6210 + u32 ethmaxf ;
6211 + u32 eth_u10 ; // Reserved.
6212 + u32 ethmtest ;
6213 + u32 miimcfg ;
6214 + u32 miimcmd ;
6215 + u32 miimaddr ;
6216 + u32 miimwtd ;
6217 + u32 miimrdd ;
6218 + u32 miimind ;
6219 + u32 eth_u11 ; // Reserved.
6220 + u32 eth_u12 ; // Reserved.
6221 + u32 ethcfsa0 ;
6222 + u32 ethcfsa1 ;
6223 + u32 ethcfsa2 ;
6224 +} volatile *ETH_t;
6225 +
6226 +enum
6227 +{
6228 + ETHINTFC_en_b = 0,
6229 + ETHINTFC_en_m = 0x00000001,
6230 + ETHINTFC_its_b = 1,
6231 + ETHINTFC_its_m = 0x00000002,
6232 + ETHINTFC_rip_b = 2,
6233 + ETHINTFC_rip_m = 0x00000004,
6234 + ETHINTFC_jam_b = 3,
6235 + ETHINTFC_jam_m = 0x00000008,
6236 + ETHINTFC_ovr_b = 4,
6237 + ETHINTFC_ovr_m = 0x00000010,
6238 + ETHINTFC_und_b = 5,
6239 + ETHINTFC_und_m = 0x00000020,
6240 +
6241 + ETHFIFOTT_tth_b = 0,
6242 + ETHFIFOTT_tth_m = 0x0000007f,
6243 +
6244 + ETHARC_pro_b = 0,
6245 + ETHARC_pro_m = 0x00000001,
6246 + ETHARC_am_b = 1,
6247 + ETHARC_am_m = 0x00000002,
6248 + ETHARC_afm_b = 2,
6249 + ETHARC_afm_m = 0x00000004,
6250 + ETHARC_ab_b = 3,
6251 + ETHARC_ab_m = 0x00000008,
6252 +
6253 + ETHSAL_byte5_b = 0,
6254 + ETHSAL_byte5_m = 0x000000ff,
6255 + ETHSAL_byte4_b = 8,
6256 + ETHSAL_byte4_m = 0x0000ff00,
6257 + ETHSAL_byte3_b = 16,
6258 + ETHSAL_byte3_m = 0x00ff0000,
6259 + ETHSAL_byte2_b = 24,
6260 + ETHSAL_byte2_m = 0xff000000,
6261 +
6262 + ETHSAH_byte1_b = 0,
6263 + ETHSAH_byte1_m = 0x000000ff,
6264 + ETHSAH_byte0_b = 8,
6265 + ETHSAH_byte0_m = 0x0000ff00,
6266 +
6267 + ETHGPF_ptv_b = 0,
6268 + ETHGPF_ptv_m = 0x0000ffff,
6269 +
6270 + ETHPFS_pfd_b = 0,
6271 + ETHPFS_pfd_m = 0x00000001,
6272 +
6273 + ETHCFSA0_cfsa4_b = 0,
6274 + ETHCFSA0_cfsa4_m = 0x000000ff,
6275 + ETHCFSA0_cfsa5_b = 8,
6276 + ETHCFSA0_cfsa5_m = 0x0000ff00,
6277 +
6278 + ETHCFSA1_cfsa2_b = 0,
6279 + ETHCFSA1_cfsa2_m = 0x000000ff,
6280 + ETHCFSA1_cfsa3_b = 8,
6281 + ETHCFSA1_cfsa3_m = 0x0000ff00,
6282 +
6283 + ETHCFSA2_cfsa0_b = 0,
6284 + ETHCFSA2_cfsa0_m = 0x000000ff,
6285 + ETHCFSA2_cfsa1_b = 8,
6286 + ETHCFSA2_cfsa1_m = 0x0000ff00,
6287 +
6288 + ETHMAC1_re_b = 0,
6289 + ETHMAC1_re_m = 0x00000001,
6290 + ETHMAC1_paf_b = 1,
6291 + ETHMAC1_paf_m = 0x00000002,
6292 + ETHMAC1_rfc_b = 2,
6293 + ETHMAC1_rfc_m = 0x00000004,
6294 + ETHMAC1_tfc_b = 3,
6295 + ETHMAC1_tfc_m = 0x00000008,
6296 + ETHMAC1_lb_b = 4,
6297 + ETHMAC1_lb_m = 0x00000010,
6298 + ETHMAC1_mr_b = 31,
6299 + ETHMAC1_mr_m = 0x80000000,
6300 +
6301 + ETHMAC2_fd_b = 0,
6302 + ETHMAC2_fd_m = 0x00000001,
6303 + ETHMAC2_flc_b = 1,
6304 + ETHMAC2_flc_m = 0x00000002,
6305 + ETHMAC2_hfe_b = 2,
6306 + ETHMAC2_hfe_m = 0x00000004,
6307 + ETHMAC2_dc_b = 3,
6308 + ETHMAC2_dc_m = 0x00000008,
6309 + ETHMAC2_cen_b = 4,
6310 + ETHMAC2_cen_m = 0x00000010,
6311 + ETHMAC2_pe_b = 5,
6312 + ETHMAC2_pe_m = 0x00000020,
6313 + ETHMAC2_vpe_b = 6,
6314 + ETHMAC2_vpe_m = 0x00000040,
6315 + ETHMAC2_ape_b = 7,
6316 + ETHMAC2_ape_m = 0x00000080,
6317 + ETHMAC2_ppe_b = 8,
6318 + ETHMAC2_ppe_m = 0x00000100,
6319 + ETHMAC2_lpe_b = 9,
6320 + ETHMAC2_lpe_m = 0x00000200,
6321 + ETHMAC2_nb_b = 12,
6322 + ETHMAC2_nb_m = 0x00001000,
6323 + ETHMAC2_bp_b = 13,
6324 + ETHMAC2_bp_m = 0x00002000,
6325 + ETHMAC2_ed_b = 14,
6326 + ETHMAC2_ed_m = 0x00004000,
6327 +
6328 + ETHIPGT_ipgt_b = 0,
6329 + ETHIPGT_ipgt_m = 0x0000007f,
6330 +
6331 + ETHIPGR_ipgr2_b = 0,
6332 + ETHIPGR_ipgr2_m = 0x0000007f,
6333 + ETHIPGR_ipgr1_b = 8,
6334 + ETHIPGR_ipgr1_m = 0x00007f00,
6335 +
6336 + ETHCLRT_maxret_b = 0,
6337 + ETHCLRT_maxret_m = 0x0000000f,
6338 + ETHCLRT_colwin_b = 8,
6339 + ETHCLRT_colwin_m = 0x00003f00,
6340 +
6341 + ETHMAXF_maxf_b = 0,
6342 + ETHMAXF_maxf_m = 0x0000ffff,
6343 +
6344 + ETHMTEST_tb_b = 2,
6345 + ETHMTEST_tb_m = 0x00000004,
6346 +
6347 + ETHMCP_div_b = 0,
6348 + ETHMCP_div_m = 0x000000ff,
6349 +
6350 + MIIMCFG_rsv_b = 0,
6351 + MIIMCFG_rsv_m = 0x0000000c,
6352 +
6353 + MIIMCMD_rd_b = 0,
6354 + MIIMCMD_rd_m = 0x00000001,
6355 + MIIMCMD_scn_b = 1,
6356 + MIIMCMD_scn_m = 0x00000002,
6357 +
6358 + MIIMADDR_regaddr_b = 0,
6359 + MIIMADDR_regaddr_m = 0x0000001f,
6360 + MIIMADDR_phyaddr_b = 8,
6361 + MIIMADDR_phyaddr_m = 0x00001f00,
6362 +
6363 + MIIMWTD_wdata_b = 0,
6364 + MIIMWTD_wdata_m = 0x0000ffff,
6365 +
6366 + MIIMRDD_rdata_b = 0,
6367 + MIIMRDD_rdata_m = 0x0000ffff,
6368 +
6369 + MIIMIND_bsy_b = 0,
6370 + MIIMIND_bsy_m = 0x00000001,
6371 + MIIMIND_scn_b = 1,
6372 + MIIMIND_scn_m = 0x00000002,
6373 + MIIMIND_nv_b = 2,
6374 + MIIMIND_nv_m = 0x00000004,
6375 +
6376 +} ;
6377 +
6378 +/*
6379 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6380 + */
6381 +enum
6382 +{
6383 + ETHRX_fd_b = 0,
6384 + ETHRX_fd_m = 0x00000001,
6385 + ETHRX_ld_b = 1,
6386 + ETHRX_ld_m = 0x00000002,
6387 + ETHRX_rok_b = 2,
6388 + ETHRX_rok_m = 0x00000004,
6389 + ETHRX_fm_b = 3,
6390 + ETHRX_fm_m = 0x00000008,
6391 + ETHRX_mp_b = 4,
6392 + ETHRX_mp_m = 0x00000010,
6393 + ETHRX_bp_b = 5,
6394 + ETHRX_bp_m = 0x00000020,
6395 + ETHRX_vlt_b = 6,
6396 + ETHRX_vlt_m = 0x00000040,
6397 + ETHRX_cf_b = 7,
6398 + ETHRX_cf_m = 0x00000080,
6399 + ETHRX_ovr_b = 8,
6400 + ETHRX_ovr_m = 0x00000100,
6401 + ETHRX_crc_b = 9,
6402 + ETHRX_crc_m = 0x00000200,
6403 + ETHRX_cv_b = 10,
6404 + ETHRX_cv_m = 0x00000400,
6405 + ETHRX_db_b = 11,
6406 + ETHRX_db_m = 0x00000800,
6407 + ETHRX_le_b = 12,
6408 + ETHRX_le_m = 0x00001000,
6409 + ETHRX_lor_b = 13,
6410 + ETHRX_lor_m = 0x00002000,
6411 + ETHRX_ces_b = 14,
6412 + ETHRX_ces_m = 0x00004000,
6413 + ETHRX_length_b = 16,
6414 + ETHRX_length_m = 0xffff0000,
6415 +
6416 + ETHTX_fd_b = 0,
6417 + ETHTX_fd_m = 0x00000001,
6418 + ETHTX_ld_b = 1,
6419 + ETHTX_ld_m = 0x00000002,
6420 + ETHTX_oen_b = 2,
6421 + ETHTX_oen_m = 0x00000004,
6422 + ETHTX_pen_b = 3,
6423 + ETHTX_pen_m = 0x00000008,
6424 + ETHTX_cen_b = 4,
6425 + ETHTX_cen_m = 0x00000010,
6426 + ETHTX_hen_b = 5,
6427 + ETHTX_hen_m = 0x00000020,
6428 + ETHTX_tok_b = 6,
6429 + ETHTX_tok_m = 0x00000040,
6430 + ETHTX_mp_b = 7,
6431 + ETHTX_mp_m = 0x00000080,
6432 + ETHTX_bp_b = 8,
6433 + ETHTX_bp_m = 0x00000100,
6434 + ETHTX_und_b = 9,
6435 + ETHTX_und_m = 0x00000200,
6436 + ETHTX_of_b = 10,
6437 + ETHTX_of_m = 0x00000400,
6438 + ETHTX_ed_b = 11,
6439 + ETHTX_ed_m = 0x00000800,
6440 + ETHTX_ec_b = 12,
6441 + ETHTX_ec_m = 0x00001000,
6442 + ETHTX_lc_b = 13,
6443 + ETHTX_lc_m = 0x00002000,
6444 + ETHTX_td_b = 14,
6445 + ETHTX_td_m = 0x00004000,
6446 + ETHTX_crc_b = 15,
6447 + ETHTX_crc_m = 0x00008000,
6448 + ETHTX_le_b = 16,
6449 + ETHTX_le_m = 0x00010000,
6450 + ETHTX_cc_b = 17,
6451 + ETHTX_cc_m = 0x001E0000,
6452 +} ;
6453 +
6454 +#endif // __IDT_ETH_H__
6455 +
6456 +
6457 +
6458 +
6459 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6460 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
6461 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-03-20 14:25:10.000000000 +0100
6462 @@ -0,0 +1,77 @@
6463 +/**************************************************************************
6464 + *
6465 + * BRIEF MODULE DESCRIPTION
6466 + * Ethernet register definition
6467 + *
6468 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6469 + *
6470 + * This program is free software; you can redistribute it and/or modify it
6471 + * under the terms of the GNU General Public License as published by the
6472 + * Free Software Foundation; either version 2 of the License, or (at your
6473 + * option) any later version.
6474 + *
6475 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6476 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6477 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6478 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6479 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6480 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6481 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6482 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6483 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6484 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6485 + *
6486 + * You should have received a copy of the GNU General Public License along
6487 + * with this program; if not, write to the Free Software Foundation, Inc.,
6488 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6489 + *
6490 + *
6491 + **************************************************************************
6492 + * May 2004 rkt, neb.
6493 + *
6494 + * Initial Release
6495 + *
6496 + *
6497 + *
6498 + **************************************************************************
6499 + */
6500 +
6501 +#ifndef __IDT_ETH_V_H__
6502 +#define __IDT_ETH_V_H__
6503 +
6504 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
6505 +
6506 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
6507 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
6508 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
6509 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
6510 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
6511 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
6512 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
6513 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
6514 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
6515 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
6516 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
6517 +
6518 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
6519 +
6520 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
6521 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
6522 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
6523 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
6524 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
6525 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
6526 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
6527 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
6528 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
6529 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
6530 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
6531 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
6532 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
6533 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
6534 +#endif // __IDT_ETH_V_H__
6535 +
6536 +
6537 +
6538 +
6539 +
6540 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6541 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
6542 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-03-20 14:25:10.000000000 +0100
6543 @@ -0,0 +1,167 @@
6544 +/**************************************************************************
6545 + *
6546 + * BRIEF MODULE DESCRIPTION
6547 + * GPIO register definition
6548 + *
6549 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6550 + *
6551 + * This program is free software; you can redistribute it and/or modify it
6552 + * under the terms of the GNU General Public License as published by the
6553 + * Free Software Foundation; either version 2 of the License, or (at your
6554 + * option) any later version.
6555 + *
6556 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6557 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6558 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6559 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6560 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6561 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6562 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6563 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6564 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6565 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6566 + *
6567 + * You should have received a copy of the GNU General Public License along
6568 + * with this program; if not, write to the Free Software Foundation, Inc.,
6569 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6570 + *
6571 + *
6572 + **************************************************************************
6573 + * May 2004 rkt, neb.
6574 + *
6575 + * Initial Release
6576 + *
6577 + *
6578 + *
6579 + **************************************************************************
6580 + */
6581 +
6582 +#ifndef __IDT_GPIO_H__
6583 +#define __IDT_GPIO_H__
6584 +
6585 +enum
6586 +{
6587 + GPIO0_PhysicalAddress = 0x18050000,
6588 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
6589 +
6590 + GPIO0_VirtualAddress = 0xb8050000,
6591 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
6592 +} ;
6593 +
6594 +typedef struct
6595 +{
6596 + u32 gpiofunc; /* GPIO Function Register
6597 + * gpiofunc[x]==0 bit = gpio
6598 + * func[x]==1 bit = altfunc
6599 + */
6600 + u32 gpiocfg; /* GPIO Configuration Register
6601 + * gpiocfg[x]==0 bit = input
6602 + * gpiocfg[x]==1 bit = output
6603 + */
6604 + u32 gpiod; /* GPIO Data Register
6605 + * gpiod[x] read/write gpio pinX status
6606 + */
6607 + u32 gpioilevel; /* GPIO Interrupt Status Register
6608 + * interrupt level (see gpioistat)
6609 + */
6610 + u32 gpioistat; /* Gpio Interrupt Status Register
6611 + * istat[x] = (gpiod[x] == level[x])
6612 + * cleared in ISR (STICKY bits)
6613 + */
6614 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
6615 +} volatile * GPIO_t ;
6616 +
6617 +typedef enum
6618 +{
6619 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
6620 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
6621 + GPIO_input_v = 0, // gpiocfg use pin as input.
6622 + GPIO_output_v = 1, // gpiocfg use pin as output.
6623 + GPIO_pin0_b = 0,
6624 + GPIO_pin0_m = 0x00000001,
6625 + GPIO_pin1_b = 1,
6626 + GPIO_pin1_m = 0x00000002,
6627 + GPIO_pin2_b = 2,
6628 + GPIO_pin2_m = 0x00000004,
6629 + GPIO_pin3_b = 3,
6630 + GPIO_pin3_m = 0x00000008,
6631 + GPIO_pin4_b = 4,
6632 + GPIO_pin4_m = 0x00000010,
6633 + GPIO_pin5_b = 5,
6634 + GPIO_pin5_m = 0x00000020,
6635 + GPIO_pin6_b = 6,
6636 + GPIO_pin6_m = 0x00000040,
6637 + GPIO_pin7_b = 7,
6638 + GPIO_pin7_m = 0x00000080,
6639 + GPIO_pin8_b = 8,
6640 + GPIO_pin8_m = 0x00000100,
6641 + GPIO_pin9_b = 9,
6642 + GPIO_pin9_m = 0x00000200,
6643 + GPIO_pin10_b = 10,
6644 + GPIO_pin10_m = 0x00000400,
6645 + GPIO_pin11_b = 11,
6646 + GPIO_pin11_m = 0x00000800,
6647 + GPIO_pin12_b = 12,
6648 + GPIO_pin12_m = 0x00001000,
6649 + GPIO_pin13_b = 13,
6650 + GPIO_pin13_m = 0x00002000,
6651 +
6652 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
6653 +
6654 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
6655 + GPIO_u0sout_m = GPIO_pin0_m,
6656 + GPIO_u0sout_cfg_v = GPIO_output_v,
6657 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
6658 + GPIO_u0sinp_m = GPIO_pin1_m,
6659 + GPIO_u0sinp_cfg_v = GPIO_input_v,
6660 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
6661 + GPIO_u0rtsn_m = GPIO_pin2_m,
6662 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
6663 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
6664 + GPIO_u0ctsn_m = GPIO_pin3_m,
6665 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
6666 +
6667 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
6668 + GPIO_maddr22_m = GPIO_pin4_m,
6669 + GPIO_maddr22_cfg_v = GPIO_output_v,
6670 +
6671 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
6672 + GPIO_maddr23_m = GPIO_pin5_m,
6673 + GPIO_maddr23_cfg_v = GPIO_output_v,
6674 +
6675 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
6676 + GPIO_maddr24_m = GPIO_pin6_m,
6677 + GPIO_maddr24_cfg_v = GPIO_output_v,
6678 +
6679 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
6680 + GPIO_maddr25_m = GPIO_pin7_m,
6681 + GPIO_maddr25_cfg_v = GPIO_output_v,
6682 +
6683 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
6684 + GPIO_cpudmadebug_m = GPIO_pin8_m,
6685 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
6686 +
6687 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
6688 + GPIO_pcireq4_m = GPIO_pin9_m,
6689 + GPIO_pcireq4_cfg_v = GPIO_input_v,
6690 +
6691 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
6692 + GPIO_pcigrant4_m = GPIO_pin10_m,
6693 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
6694 +
6695 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
6696 + GPIO_pcireq5_m = GPIO_pin11_m,
6697 + GPIO_pcireq5_cfg_v = GPIO_input_v,
6698 +
6699 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
6700 + GPIO_pcigrant5_m = GPIO_pin12_m,
6701 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
6702 +
6703 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
6704 + GPIO_pcimuintn_m = GPIO_pin13_m,
6705 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
6706 +
6707 +} GPIO_DEFS_t;
6708 +
6709 +#endif // __IDT_GPIO_H__
6710 +
6711 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6712 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
6713 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-03-20 14:25:10.000000000 +0100
6714 @@ -0,0 +1,199 @@
6715 + /**************************************************************************
6716 + *
6717 + * BRIEF MODULE DESCRIPTION
6718 + * Definitions for IDT RC32434 CPU
6719 + *
6720 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6721 + *
6722 + * This program is free software; you can redistribute it and/or modify it
6723 + * under the terms of the GNU General Public License as published by the
6724 + * Free Software Foundation; either version 2 of the License, or (at your
6725 + * option) any later version.
6726 + *
6727 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6728 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6729 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6730 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6731 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6732 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6733 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6734 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6735 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6736 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6737 + *
6738 + * You should have received a copy of the GNU General Public License along
6739 + * with this program; if not, write to the Free Software Foundation, Inc.,
6740 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6741 + *
6742 + *
6743 + **************************************************************************
6744 + * May 2004 rkt, neb.
6745 + *
6746 + * Initial Release
6747 + *
6748 + *
6749 + *
6750 + **************************************************************************
6751 + */
6752 +
6753 +#ifndef _RC32434_H_
6754 +#define _RC32434_H_
6755 +
6756 +#include <linux/config.h>
6757 +#include <linux/delay.h>
6758 +#include <asm/io.h>
6759 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6760 +
6761 +#define RC32434_REG_BASE 0x18000000
6762 +
6763 +
6764 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6765 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
6766 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6767 +
6768 +#define IDT_CLOCK_MULT 2
6769 +#define MIPS_CPU_TIMER_IRQ 7
6770 +/* Interrupt Controller */
6771 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
6772 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
6773 +#define IC_GROUP_OFFSET 0x0C
6774 +#define RTC_BASE 0xBA001FF0
6775 +
6776 +#define NUM_INTR_GROUPS 5
6777 +/* 16550 UARTs */
6778 +
6779 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
6780 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6781 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6782 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6783 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6784 +
6785 +#ifdef __MIPSEB__
6786 +
6787 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6788 +#define EB434_UART1_BASE (0x19800003)
6789 +
6790 +#else
6791 +
6792 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6793 +#define EB434_UART1_BASE (0x19800000)
6794 +
6795 +#endif
6796 +
6797 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
6798 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
6799 +
6800 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
6801 +
6802 +/* cpu pipeline flush */
6803 +static inline void rc32434_sync(void)
6804 +{
6805 + __asm__ volatile ("sync");
6806 +}
6807 +
6808 +static inline void rc32434_sync_udelay(int us)
6809 +{
6810 + __asm__ volatile ("sync");
6811 + udelay(us);
6812 +}
6813 +
6814 +static inline void rc32434_sync_delay(int ms)
6815 +{
6816 + __asm__ volatile ("sync");
6817 + mdelay(ms);
6818 +}
6819 +
6820 +
6821 +
6822 +/*
6823 + * Macros to access internal RC32434 registers. No byte
6824 + * swapping should be done when accessing the internal
6825 + * registers.
6826 + */
6827 +
6828 +#define rc32434_readb __raw_readb
6829 +#define rc32434_readw __raw_readw
6830 +#define rc32434_readl __raw_readl
6831 +
6832 +#define rc32434_writeb __raw_writeb
6833 +#define rc32434_writew __raw_writew
6834 +#define rc32434_writel __raw_writel
6835 +
6836 +#if 0
6837 +static inline u8 rc32434_readb(unsigned long pa)
6838 +{
6839 + return *((volatile u8 *)KSEG1ADDR(pa));
6840 +}
6841 +static inline u16 rc32434_readw(unsigned long pa)
6842 +{
6843 + return *((volatile u16 *)KSEG1ADDR(pa));
6844 +}
6845 +static inline u32 rc32434_readl(unsigned long pa)
6846 +{
6847 + return *((volatile u32 *)KSEG1ADDR(pa));
6848 +}
6849 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6850 +{
6851 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
6852 +}
6853 +static inline void rc32434_writew(u16 val, unsigned long pa)
6854 +{
6855 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
6856 +}
6857 +static inline void rc32434_writel(u32 val, unsigned long pa)
6858 +{
6859 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
6860 +}
6861 +
6862 +#endif
6863 +
6864 +
6865 +/*
6866 + * C access to CLZ and CLO instructions
6867 + * (count leading zeroes/ones).
6868 + */
6869 +static inline int rc32434_clz(unsigned long val)
6870 +{
6871 + int ret;
6872 + __asm__ volatile (
6873 + ".set\tnoreorder\n\t"
6874 + ".set\tnoat\n\t"
6875 + ".set\tmips32\n\t"
6876 + "clz\t%0,%1\n\t"
6877 + ".set\tmips0\n\t"
6878 + ".set\tat\n\t"
6879 + ".set\treorder"
6880 + : "=r" (ret)
6881 + : "r" (val));
6882 +
6883 + return ret;
6884 +}
6885 +static inline int rc32434_clo(unsigned long val)
6886 +{
6887 + int ret;
6888 + __asm__ volatile (
6889 + ".set\tnoreorder\n\t"
6890 + ".set\tnoat\n\t"
6891 + ".set\tmips32\n\t"
6892 + "clo\t%0,%1\n\t"
6893 + ".set\tmips0\n\t"
6894 + ".set\tat\n\t"
6895 + ".set\treorder"
6896 + : "=r" (ret)
6897 + : "r" (val));
6898 +
6899 + return ret;
6900 +}
6901 +#endif /* _RC32434_H_ */
6902 +
6903 +
6904 +
6905 +
6906 +
6907 +
6908 +
6909 +
6910 +
6911 +
6912 +
6913 +
6914 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6915 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
6916 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-03-20 14:25:10.000000000 +0100
6917 @@ -0,0 +1,90 @@
6918 +/**************************************************************************
6919 + *
6920 + * BRIEF MODULE DESCRIPTION
6921 + * System Integrity register definition
6922 + *
6923 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6924 + *
6925 + * This program is free software; you can redistribute it and/or modify it
6926 + * under the terms of the GNU General Public License as published by the
6927 + * Free Software Foundation; either version 2 of the License, or (at your
6928 + * option) any later version.
6929 + *
6930 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6931 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6932 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6933 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6934 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6935 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6936 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6937 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6938 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6939 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6940 + *
6941 + * You should have received a copy of the GNU General Public License along
6942 + * with this program; if not, write to the Free Software Foundation, Inc.,
6943 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6944 + *
6945 + *
6946 + **************************************************************************
6947 + * May 2004 rkt, neb
6948 + *
6949 + * Initial Release
6950 + *
6951 + *
6952 + *
6953 + **************************************************************************
6954 + */
6955 +
6956 +#ifndef __IDT_INTEG_H__
6957 +#define __IDT_INTEG_H__
6958 +
6959 +enum
6960 +{
6961 + INTEG0_PhysicalAddress = 0x18030000,
6962 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
6963 +
6964 + INTEG0_VirtualAddress = 0xB8030000,
6965 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
6966 +} ;
6967 +
6968 +// if you are looking for CEA, try rst.h
6969 +typedef struct
6970 +{
6971 + u32 filler [0xc] ; // 0x30 bytes unused.
6972 + u32 errcs ; // sticky use ERRCS_
6973 + u32 wtcount ; // Watchdog timer count reg.
6974 + u32 wtcompare ; // Watchdog timer timeout value.
6975 + u32 wtc ; // Watchdog timer control. use WTC_
6976 +} volatile *INTEG_t ;
6977 +
6978 +enum
6979 +{
6980 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
6981 + ERRCS_wto_m = 0x00000001,
6982 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
6983 + ERRCS_wne_m = 0x00000002,
6984 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
6985 + ERRCS_ucw_m = 0x00000004,
6986 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
6987 + ERRCS_ucr_m = 0x00000008,
6988 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
6989 + ERRCS_upw_m = 0x00000010,
6990 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
6991 + ERRCS_upr_m = 0x00000020,
6992 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
6993 + ERRCS_udw_m = 0x00000040,
6994 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
6995 + ERRCS_udr_m = 0x00000080,
6996 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
6997 + ERRCS_sae_m = 0x00000100,
6998 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
6999 + ERRCS_wre_m = 0x00000200,
7000 +
7001 + WTC_en_b = 0, // In INTEG_t -> wtc
7002 + WTC_en_m = 0x00000001,
7003 + WTC_to_b = 1, // In INTEG_t -> wtc
7004 + WTC_to_m = 0x00000002,
7005 +} ;
7006 +
7007 +#endif // __IDT_INTEG_H__
7008 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7009 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
7010 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-03-20 14:25:10.000000000 +0100
7011 @@ -0,0 +1,174 @@
7012 +/**************************************************************************
7013 + *
7014 + * BRIEF MODULE DESCRIPTION
7015 + * Interrupt Controller register definition.
7016 + *
7017 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7018 + *
7019 + * This program is free software; you can redistribute it and/or modify it
7020 + * under the terms of the GNU General Public License as published by the
7021 + * Free Software Foundation; either version 2 of the License, or (at your
7022 + * option) any later version.
7023 + *
7024 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7025 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7026 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7027 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7028 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7029 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7030 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7031 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7032 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7033 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7034 + *
7035 + * You should have received a copy of the GNU General Public License along
7036 + * with this program; if not, write to the Free Software Foundation, Inc.,
7037 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7038 + *
7039 + *
7040 + **************************************************************************
7041 + * May 2004 rkt, neb.
7042 + *
7043 + * Initial Release
7044 + *
7045 + *
7046 + *
7047 + **************************************************************************
7048 + */
7049 +
7050 +#ifndef __IDT_INT_H__
7051 +#define __IDT_INT_H__
7052 +
7053 +enum
7054 +{
7055 + INT0_PhysicalAddress = 0x18038000,
7056 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
7057 +
7058 + INT0_VirtualAddress = 0xB8038000,
7059 + INT_VirtualAddress = INT0_VirtualAddress, // Default
7060 +} ;
7061 +
7062 +struct INT_s
7063 +{
7064 + u32 ipend ; //Pending interrupts. use INT?_
7065 + u32 itest ; //Test bits. use INT?_
7066 + u32 imask ; //Interrupt disabled when set. use INT?_
7067 +} ;
7068 +
7069 +enum
7070 +{
7071 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
7072 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
7073 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
7074 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
7075 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
7076 +
7077 + IPEND_count, // must be last (used in loops)
7078 + IPEND_min = IPEND2 // min IPEND (used in loops)
7079 +};
7080 +
7081 +typedef struct INTC_s
7082 +{
7083 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
7084 + u32 nmips ; // use NMIPS_
7085 +} volatile *INT_t ;
7086 +
7087 +enum
7088 +{
7089 + INT2_timer0_b = 0,
7090 + INT2_timer0_m = 0x00000001,
7091 + INT2_timer1_b = 1,
7092 + INT2_timer1_m = 0x00000002,
7093 + INT2_timer2_b = 2,
7094 + INT2_timer2_m = 0x00000004,
7095 + INT2_refresh_b = 3,
7096 + INT2_refresh_m = 0x00000008,
7097 + INT2_watchdogTimeout_b = 4,
7098 + INT2_watchdogTimeout_m = 0x00000010,
7099 + INT2_undecodedCpuWrite_b = 5,
7100 + INT2_undecodedCpuWrite_m = 0x00000020,
7101 + INT2_undecodedCpuRead_b = 6,
7102 + INT2_undecodedCpuRead_m = 0x00000040,
7103 + INT2_undecodedPciWrite_b = 7,
7104 + INT2_undecodedPciWrite_m = 0x00000080,
7105 + INT2_undecodedPciRead_b = 8,
7106 + INT2_undecodedPciRead_m = 0x00000100,
7107 + INT2_undecodedDmaWrite_b = 9,
7108 + INT2_undecodedDmaWrite_m = 0x00000200,
7109 + INT2_undecodedDmaRead_b = 10,
7110 + INT2_undecodedDmaRead_m = 0x00000400,
7111 + INT2_ipBusSlaveAckError_b = 11,
7112 + INT2_ipBusSlaveAckError_m = 0x00000800,
7113 +
7114 + INT3_dmaChannel0_b = 0,
7115 + INT3_dmaChannel0_m = 0x00000001,
7116 + INT3_dmaChannel1_b = 1,
7117 + INT3_dmaChannel1_m = 0x00000002,
7118 + INT3_dmaChannel2_b = 2,
7119 + INT3_dmaChannel2_m = 0x00000004,
7120 + INT3_dmaChannel3_b = 3,
7121 + INT3_dmaChannel3_m = 0x00000008,
7122 + INT3_dmaChannel4_b = 4,
7123 + INT3_dmaChannel4_m = 0x00000010,
7124 + INT3_dmaChannel5_b = 5,
7125 + INT3_dmaChannel5_m = 0x00000020,
7126 +
7127 + INT5_uartGeneral0_b = 0,
7128 + INT5_uartGeneral0_m = 0x00000001,
7129 + INT5_uartTxrdy0_b = 1,
7130 + INT5_uartTxrdy0_m = 0x00000002,
7131 + INT5_uartRxrdy0_b = 2,
7132 + INT5_uartRxrdy0_m = 0x00000004,
7133 + INT5_pci_b = 3,
7134 + INT5_pci_m = 0x00000008,
7135 + INT5_pciDecoupled_b = 4,
7136 + INT5_pciDecoupled_m = 0x00000010,
7137 + INT5_spi_b = 5,
7138 + INT5_spi_m = 0x00000020,
7139 + INT5_deviceDecoupled_b = 6,
7140 + INT5_deviceDecoupled_m = 0x00000040,
7141 + INT5_eth0Ovr_b = 9,
7142 + INT5_eth0Ovr_m = 0x00000200,
7143 + INT5_eth0Und_b = 10,
7144 + INT5_eth0Und_m = 0x00000400,
7145 + INT5_eth0Pfd_b = 11,
7146 + INT5_eth0Pfd_m = 0x00000800,
7147 + INT5_nvram_b = 12,
7148 + INT5_nvram_m = 0x00001000,
7149 +
7150 + INT6_gpio0_b = 0,
7151 + INT6_gpio0_m = 0x00000001,
7152 + INT6_gpio1_b = 1,
7153 + INT6_gpio1_m = 0x00000002,
7154 + INT6_gpio2_b = 2,
7155 + INT6_gpio2_m = 0x00000004,
7156 + INT6_gpio3_b = 3,
7157 + INT6_gpio3_m = 0x00000008,
7158 + INT6_gpio4_b = 4,
7159 + INT6_gpio4_m = 0x00000010,
7160 + INT6_gpio5_b = 5,
7161 + INT6_gpio5_m = 0x00000020,
7162 + INT6_gpio6_b = 6,
7163 + INT6_gpio6_m = 0x00000040,
7164 + INT6_gpio7_b = 7,
7165 + INT6_gpio7_m = 0x00000080,
7166 + INT6_gpio8_b = 8,
7167 + INT6_gpio8_m = 0x00000100,
7168 + INT6_gpio9_b = 9,
7169 + INT6_gpio9_m = 0x00000200,
7170 + INT6_gpio10_b = 10,
7171 + INT6_gpio10_m = 0x00000400,
7172 + INT6_gpio11_b = 11,
7173 + INT6_gpio11_m = 0x00000800,
7174 + INT6_gpio12_b = 12,
7175 + INT6_gpio12_m = 0x00001000,
7176 + INT6_gpio13_b = 13,
7177 + INT6_gpio13_m = 0x00002000,
7178 +
7179 + NMIPS_gpio_b = 0,
7180 + NMIPS_gpio_m = 0x00000001,
7181 +} ;
7182 +
7183 +#endif // __IDT_INT_H__
7184 +
7185 +
7186 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7187 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
7188 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-03-20 14:25:10.000000000 +0100
7189 @@ -0,0 +1,111 @@
7190 +/**************************************************************************
7191 + *
7192 + * BRIEF MODULE DESCRIPTION
7193 + * IP Arbiter register definitions
7194 + *
7195 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7196 + *
7197 + * This program is free software; you can redistribute it and/or modify it
7198 + * under the terms of the GNU General Public License as published by the
7199 + * Free Software Foundation; either version 2 of the License, or (at your
7200 + * option) any later version.
7201 + *
7202 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7203 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7204 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7205 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7206 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7207 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7208 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7209 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7210 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7211 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7212 + *
7213 + * You should have received a copy of the GNU General Public License along
7214 + * with this program; if not, write to the Free Software Foundation, Inc.,
7215 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7216 + *
7217 + *
7218 + **************************************************************************
7219 + * May 2004 rkt,neb
7220 + *
7221 + * Initial Release
7222 + *
7223 + *
7224 + *
7225 + **************************************************************************
7226 + */
7227 +
7228 +#ifndef __IDT_IPARB_H__
7229 +#define __IDT_IPARB_H__
7230 +
7231 +enum
7232 +{
7233 + IPARB0_PhysicalAddress = 0x18048000,
7234 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
7235 +
7236 + IPARB0_VirtualAddress = 0xB8048000,
7237 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
7238 +} ;
7239 +
7240 +enum
7241 +{
7242 + IPABMXC_ethernet0Receive = 0,
7243 + IPABMXC_ethernet0Transmit = 1,
7244 + IPABMXC_memoryToHoldFifo = 2,
7245 + IPABMXC_holdFifoToMemory = 3,
7246 + IPABMXC_pciToMemory = 4,
7247 + IPABMXC_memoryToPci = 5,
7248 + IPABMXC_pciTarget = 6,
7249 + IPABMXC_pciTargetStart = 7,
7250 + IPABMXC_cpuToIpBus = 8,
7251 +
7252 + IPABMXC_Count, // Must be last in list !
7253 + IPABMXC_Min = IPABMXC_ethernet0Receive,
7254 +
7255 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
7256 +} ;
7257 +
7258 +typedef struct
7259 +{
7260 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
7261 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
7262 + u32 ipac ; // use IPAC_
7263 + u32 ipaitcc; // use IPAITCC_
7264 + u32 ipaspare ;
7265 +} volatile * IPARB_t ;
7266 +
7267 +enum
7268 +{
7269 + IPAC_dp_b = 0,
7270 + IPAC_dp_m = 0x00000001,
7271 + IPAC_dep_b = 1,
7272 + IPAC_dep_m = 0x00000002,
7273 + IPAC_drm_b = 2,
7274 + IPAC_drm_m = 0x00000004,
7275 + IPAC_dwm_b = 3,
7276 + IPAC_dwm_m = 0x00000008,
7277 + IPAC_msk_b = 4,
7278 + IPAC_msk_m = 0x00000010,
7279 +
7280 + IPAPC_ptc_b = 0,
7281 + IPAPC_ptc_m = 0x00003fff,
7282 + IPAPC_mf_b = 14,
7283 + IPAPC_mf_m = 0x00004000,
7284 + IPAPC_cptc_b = 16,
7285 + IPAPC_cptc_m = 0x3fff0000,
7286 +
7287 + IPAITCC_itcc = 0,
7288 + IPAITCC_itcc, = 0x000001ff,
7289 +
7290 + IPABMC_mtc_b = 0,
7291 + IPABMC_mtc_m = 0x00000fff,
7292 + IPABMC_p_b = 12,
7293 + IPABMC_p_m = 0x00003000,
7294 + IPABMC_msk_b = 14,
7295 + IPABMC_msk_m = 0x00004000,
7296 + IPABMC_cmtc_b = 16,
7297 + IPABMC_cmtc_m = 0x0fff0000,
7298 +};
7299 +
7300 +#endif // __IDT_IPARB_H__
7301 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7302 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
7303 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-03-20 14:25:10.000000000 +0100
7304 @@ -0,0 +1,695 @@
7305 +/**************************************************************************
7306 + *
7307 + * BRIEF MODULE DESCRIPTION
7308 + * PCI register definitio
7309 + *
7310 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7311 + *
7312 + * This program is free software; you can redistribute it and/or modify it
7313 + * under the terms of the GNU General Public License as published by the
7314 + * Free Software Foundation; either version 2 of the License, or (at your
7315 + * option) any later version.
7316 + *
7317 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7318 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7319 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7320 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7321 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7322 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7323 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7324 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7325 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7326 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7327 + *
7328 + * You should have received a copy of the GNU General Public License along
7329 + * with this program; if not, write to the Free Software Foundation, Inc.,
7330 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7331 + *
7332 + *
7333 + **************************************************************************
7334 + * May 2004 rkt, neb.
7335 + *
7336 + * Initial Release
7337 + *
7338 + *
7339 + *
7340 + **************************************************************************
7341 + */
7342 +
7343 +#ifndef __IDT_PCI_H__
7344 +#define __IDT_PCI_H__
7345 +
7346 +enum
7347 +{
7348 + PCI0_PhysicalAddress = 0x18080000,
7349 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
7350 +
7351 + PCI0_VirtualAddress = 0xB8080000,
7352 + PCI_VirtualAddress = PCI0_VirtualAddress,
7353 +} ;
7354 +
7355 +enum
7356 +{
7357 + PCI_LbaCount = 4, // Local base addresses.
7358 +} ;
7359 +
7360 +typedef struct
7361 +{
7362 + u32 a ; // Address.
7363 + u32 c ; // Control.
7364 + u32 m ; // mapping.
7365 +} PCI_Map_s ;
7366 +
7367 +typedef struct
7368 +{
7369 + u32 pcic ;
7370 + u32 pcis ;
7371 + u32 pcism ;
7372 + u32 pcicfga ;
7373 + u32 pcicfgd ;
7374 + PCI_Map_s pcilba [PCI_LbaCount] ;
7375 + u32 pcidac ;
7376 + u32 pcidas ;
7377 + u32 pcidasm ;
7378 + u32 pcidad ;
7379 + u32 pcidma8c ;
7380 + u32 pcidma9c ;
7381 + u32 pcitc ;
7382 +} volatile *PCI_t ;
7383 +
7384 +// PCI messaging unit.
7385 +enum
7386 +{
7387 + PCIM_Count = 2,
7388 +} ;
7389 +typedef struct
7390 +{
7391 + u32 pciim [PCIM_Count] ;
7392 + u32 pciom [PCIM_Count] ;
7393 + u32 pciid ;
7394 + u32 pciiic ;
7395 + u32 pciiim ;
7396 + u32 pciiod ;
7397 + u32 pciioic ;
7398 + u32 pciioim ;
7399 +} volatile *PCIM_t ;
7400 +
7401 +/*******************************************************************************
7402 + *
7403 + * PCI Control Register
7404 + *
7405 + ******************************************************************************/
7406 +enum
7407 +{
7408 + PCIC_en_b = 0,
7409 + PCIC_en_m = 0x00000001,
7410 + PCIC_tnr_b = 1,
7411 + PCIC_tnr_m = 0x00000002,
7412 + PCIC_sce_b = 2,
7413 + PCIC_sce_m = 0x00000004,
7414 + PCIC_ien_b = 3,
7415 + PCIC_ien_m = 0x00000008,
7416 + PCIC_aaa_b = 4,
7417 + PCIC_aaa_m = 0x00000010,
7418 + PCIC_eap_b = 5,
7419 + PCIC_eap_m = 0x00000020,
7420 + PCIC_pcim_b = 6,
7421 + PCIC_pcim_m = 0x000001c0,
7422 + PCIC_pcim_disabled_v = 0,
7423 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
7424 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
7425 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
7426 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
7427 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
7428 + PCIC_pcim_reserved6_v = 6,
7429 + PCIC_pcim_reserved7_v = 7,
7430 + PCIC_igm_b = 9,
7431 + PCIC_igm_m = 0x00000200,
7432 +} ;
7433 +
7434 +/*******************************************************************************
7435 + *
7436 + * PCI Status Register
7437 + *
7438 + ******************************************************************************/
7439 +enum {
7440 + PCIS_eed_b = 0,
7441 + PCIS_eed_m = 0x00000001,
7442 + PCIS_wr_b = 1,
7443 + PCIS_wr_m = 0x00000002,
7444 + PCIS_nmi_b = 2,
7445 + PCIS_nmi_m = 0x00000004,
7446 + PCIS_ii_b = 3,
7447 + PCIS_ii_m = 0x00000008,
7448 + PCIS_cwe_b = 4,
7449 + PCIS_cwe_m = 0x00000010,
7450 + PCIS_cre_b = 5,
7451 + PCIS_cre_m = 0x00000020,
7452 + PCIS_mdpe_b = 6,
7453 + PCIS_mdpe_m = 0x00000040,
7454 + PCIS_sta_b = 7,
7455 + PCIS_sta_m = 0x00000080,
7456 + PCIS_rta_b = 8,
7457 + PCIS_rta_m = 0x00000100,
7458 + PCIS_rma_b = 9,
7459 + PCIS_rma_m = 0x00000200,
7460 + PCIS_sse_b = 10,
7461 + PCIS_sse_m = 0x00000400,
7462 + PCIS_ose_b = 11,
7463 + PCIS_ose_m = 0x00000800,
7464 + PCIS_pe_b = 12,
7465 + PCIS_pe_m = 0x00001000,
7466 + PCIS_tae_b = 13,
7467 + PCIS_tae_m = 0x00002000,
7468 + PCIS_rle_b = 14,
7469 + PCIS_rle_m = 0x00004000,
7470 + PCIS_bme_b = 15,
7471 + PCIS_bme_m = 0x00008000,
7472 + PCIS_prd_b = 16,
7473 + PCIS_prd_m = 0x00010000,
7474 + PCIS_rip_b = 17,
7475 + PCIS_rip_m = 0x00020000,
7476 +} ;
7477 +
7478 +/*******************************************************************************
7479 + *
7480 + * PCI Status Mask Register
7481 + *
7482 + ******************************************************************************/
7483 +enum {
7484 + PCISM_eed_b = 0,
7485 + PCISM_eed_m = 0x00000001,
7486 + PCISM_wr_b = 1,
7487 + PCISM_wr_m = 0x00000002,
7488 + PCISM_nmi_b = 2,
7489 + PCISM_nmi_m = 0x00000004,
7490 + PCISM_ii_b = 3,
7491 + PCISM_ii_m = 0x00000008,
7492 + PCISM_cwe_b = 4,
7493 + PCISM_cwe_m = 0x00000010,
7494 + PCISM_cre_b = 5,
7495 + PCISM_cre_m = 0x00000020,
7496 + PCISM_mdpe_b = 6,
7497 + PCISM_mdpe_m = 0x00000040,
7498 + PCISM_sta_b = 7,
7499 + PCISM_sta_m = 0x00000080,
7500 + PCISM_rta_b = 8,
7501 + PCISM_rta_m = 0x00000100,
7502 + PCISM_rma_b = 9,
7503 + PCISM_rma_m = 0x00000200,
7504 + PCISM_sse_b = 10,
7505 + PCISM_sse_m = 0x00000400,
7506 + PCISM_ose_b = 11,
7507 + PCISM_ose_m = 0x00000800,
7508 + PCISM_pe_b = 12,
7509 + PCISM_pe_m = 0x00001000,
7510 + PCISM_tae_b = 13,
7511 + PCISM_tae_m = 0x00002000,
7512 + PCISM_rle_b = 14,
7513 + PCISM_rle_m = 0x00004000,
7514 + PCISM_bme_b = 15,
7515 + PCISM_bme_m = 0x00008000,
7516 + PCISM_prd_b = 16,
7517 + PCISM_prd_m = 0x00010000,
7518 + PCISM_rip_b = 17,
7519 + PCISM_rip_m = 0x00020000,
7520 +} ;
7521 +
7522 +/*******************************************************************************
7523 + *
7524 + * PCI Configuration Address Register
7525 + *
7526 + ******************************************************************************/
7527 +enum {
7528 + PCICFGA_reg_b = 2,
7529 + PCICFGA_reg_m = 0x000000fc,
7530 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
7531 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
7532 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
7533 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
7534 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
7535 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
7536 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
7537 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
7538 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7539 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
7540 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
7541 + PCICFGA_reg_pba0m_v = 0x48>>2,
7542 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
7543 + PCICFGA_reg_pba1m_v = 0x50>>2,
7544 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
7545 + PCICFGA_reg_pba2m_v = 0x58>>2,
7546 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
7547 + PCICFGA_reg_pba3m_v = 0x60>>2,
7548 + PCICFGA_reg_pmgt_v = 0x64>>2,
7549 + PCICFGA_func_b = 8,
7550 + PCICFGA_func_m = 0x00000700,
7551 + PCICFGA_dev_b = 11,
7552 + PCICFGA_dev_m = 0x0000f800,
7553 + PCICFGA_dev_internal_v = 0,
7554 + PCICFGA_bus_b = 16,
7555 + PCICFGA_bus_m = 0x00ff0000,
7556 + PCICFGA_bus_type0_v = 0, //local bus
7557 + PCICFGA_en_b = 31, // read only
7558 + PCICFGA_en_m = 0x80000000,
7559 +} ;
7560 +
7561 +enum {
7562 + PCFGID_vendor_b = 0,
7563 + PCFGID_vendor_m = 0x0000ffff,
7564 + PCFGID_vendor_IDT_v = 0x111d,
7565 + PCFGID_device_b = 16,
7566 + PCFGID_device_m = 0xffff0000,
7567 + PCFGID_device_Korinade_v = 0x0214,
7568 +
7569 + PCFG04_command_ioena_b = 1,
7570 + PCFG04_command_ioena_m = 0x00000001,
7571 + PCFG04_command_memena_b = 2,
7572 + PCFG04_command_memena_m = 0x00000002,
7573 + PCFG04_command_bmena_b = 3,
7574 + PCFG04_command_bmena_m = 0x00000004,
7575 + PCFG04_command_mwinv_b = 5,
7576 + PCFG04_command_mwinv_m = 0x00000010,
7577 + PCFG04_command_parena_b = 7,
7578 + PCFG04_command_parena_m = 0x00000040,
7579 + PCFG04_command_serrena_b = 9,
7580 + PCFG04_command_serrena_m = 0x00000100,
7581 + PCFG04_command_fastbbena_b = 10,
7582 + PCFG04_command_fastbbena_m = 0x00000200,
7583 + PCFG04_status_b = 16,
7584 + PCFG04_status_m = 0xffff0000,
7585 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
7586 + PCFG04_status_66MHz_m = 0x00200000,
7587 + PCFG04_status_fbb_b = 23,
7588 + PCFG04_status_fbb_m = 0x00800000,
7589 + PCFG04_status_mdpe_b = 24,
7590 + PCFG04_status_mdpe_m = 0x01000000,
7591 + PCFG04_status_dst_b = 25,
7592 + PCFG04_status_dst_m = 0x06000000,
7593 + PCFG04_status_sta_b = 27,
7594 + PCFG04_status_sta_m = 0x08000000,
7595 + PCFG04_status_rta_b = 28,
7596 + PCFG04_status_rta_m = 0x10000000,
7597 + PCFG04_status_rma_b = 29,
7598 + PCFG04_status_rma_m = 0x20000000,
7599 + PCFG04_status_sse_b = 30,
7600 + PCFG04_status_sse_m = 0x40000000,
7601 + PCFG04_status_pe_b = 31,
7602 + PCFG04_status_pe_m = 0x40000000,
7603 +
7604 + PCFG08_revId_b = 0,
7605 + PCFG08_revId_m = 0x000000ff,
7606 + PCFG08_classCode_b = 0,
7607 + PCFG08_classCode_m = 0xffffff00,
7608 + PCFG08_classCode_bridge_v = 06,
7609 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
7610 + PCFG0C_cacheline_b = 0,
7611 + PCFG0C_cacheline_m = 0x000000ff,
7612 + PCFG0C_masterLatency_b = 8,
7613 + PCFG0C_masterLatency_m = 0x0000ff00,
7614 + PCFG0C_headerType_b = 16,
7615 + PCFG0C_headerType_m = 0x00ff0000,
7616 + PCFG0C_bist_b = 24,
7617 + PCFG0C_bist_m = 0xff000000,
7618 +
7619 + PCIPBA_msi_b = 0,
7620 + PCIPBA_msi_m = 0x00000001,
7621 + PCIPBA_p_b = 3,
7622 + PCIPBA_p_m = 0x00000004,
7623 + PCIPBA_baddr_b = 8,
7624 + PCIPBA_baddr_m = 0xffffff00,
7625 +
7626 + PCFGSS_vendorId_b = 0,
7627 + PCFGSS_vendorId_m = 0x0000ffff,
7628 + PCFGSS_id_b = 16,
7629 + PCFGSS_id_m = 0xffff0000,
7630 +
7631 + PCFG3C_interruptLine_b = 0,
7632 + PCFG3C_interruptLine_m = 0x000000ff,
7633 + PCFG3C_interruptPin_b = 8,
7634 + PCFG3C_interruptPin_m = 0x0000ff00,
7635 + PCFG3C_minGrant_b = 16,
7636 + PCFG3C_minGrant_m = 0x00ff0000,
7637 + PCFG3C_maxLat_b = 24,
7638 + PCFG3C_maxLat_m = 0xff000000,
7639 +
7640 + PCIPBAC_msi_b = 0,
7641 + PCIPBAC_msi_m = 0x00000001,
7642 + PCIPBAC_p_b = 1,
7643 + PCIPBAC_p_m = 0x00000002,
7644 + PCIPBAC_size_b = 2,
7645 + PCIPBAC_size_m = 0x0000007c,
7646 + PCIPBAC_sb_b = 7,
7647 + PCIPBAC_sb_m = 0x00000080,
7648 + PCIPBAC_pp_b = 8,
7649 + PCIPBAC_pp_m = 0x00000100,
7650 + PCIPBAC_mr_b = 9,
7651 + PCIPBAC_mr_m = 0x00000600,
7652 + PCIPBAC_mr_read_v =0, //no prefetching
7653 + PCIPBAC_mr_readLine_v =1,
7654 + PCIPBAC_mr_readMult_v =2,
7655 + PCIPBAC_mrl_b = 11,
7656 + PCIPBAC_mrl_m = 0x00000800,
7657 + PCIPBAC_mrm_b = 12,
7658 + PCIPBAC_mrm_m = 0x00001000,
7659 + PCIPBAC_trp_b = 13,
7660 + PCIPBAC_trp_m = 0x00002000,
7661 +
7662 + PCFG40_trdyTimeout_b = 0,
7663 + PCFG40_trdyTimeout_m = 0x000000ff,
7664 + PCFG40_retryLim_b = 8,
7665 + PCFG40_retryLim_m = 0x0000ff00,
7666 +};
7667 +
7668 +/*******************************************************************************
7669 + *
7670 + * PCI Local Base Address [0|1|2|3] Register
7671 + *
7672 + ******************************************************************************/
7673 +enum {
7674 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
7675 + PCILBA_baddr_m = 0xffffff00,
7676 +} ;
7677 +/*******************************************************************************
7678 + *
7679 + * PCI Local Base Address Control Register
7680 + *
7681 + ******************************************************************************/
7682 +enum {
7683 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
7684 + PCILBAC_msi_m = 0x00000001,
7685 + PCILBAC_msi_mem_v = 0,
7686 + PCILBAC_msi_io_v = 1,
7687 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
7688 + PCILBAC_size_m = 0x0000007c,
7689 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
7690 + PCILBAC_sb_m = 0x00000080,
7691 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
7692 + PCILBAC_rt_m = 0x00000100,
7693 + PCILBAC_rt_noprefetch_v = 0, // mem read
7694 + PCILBAC_rt_prefetch_v = 1, // mem readline
7695 +} ;
7696 +
7697 +/*******************************************************************************
7698 + *
7699 + * PCI Local Base Address [0|1|2|3] Mapping Register
7700 + *
7701 + ******************************************************************************/
7702 +enum {
7703 + PCILBAM_maddr_b = 8,
7704 + PCILBAM_maddr_m = 0xffffff00,
7705 +} ;
7706 +
7707 +/*******************************************************************************
7708 + *
7709 + * PCI Decoupled Access Control Register
7710 + *
7711 + ******************************************************************************/
7712 +enum {
7713 + PCIDAC_den_b = 0,
7714 + PCIDAC_den_m = 0x00000001,
7715 +} ;
7716 +
7717 +/*******************************************************************************
7718 + *
7719 + * PCI Decoupled Access Status Register
7720 + *
7721 + ******************************************************************************/
7722 +enum {
7723 + PCIDAS_d_b = 0,
7724 + PCIDAS_d_m = 0x00000001,
7725 + PCIDAS_b_b = 1,
7726 + PCIDAS_b_m = 0x00000002,
7727 + PCIDAS_e_b = 2,
7728 + PCIDAS_e_m = 0x00000004,
7729 + PCIDAS_ofe_b = 3,
7730 + PCIDAS_ofe_m = 0x00000008,
7731 + PCIDAS_off_b = 4,
7732 + PCIDAS_off_m = 0x00000010,
7733 + PCIDAS_ife_b = 5,
7734 + PCIDAS_ife_m = 0x00000020,
7735 + PCIDAS_iff_b = 6,
7736 + PCIDAS_iff_m = 0x00000040,
7737 +} ;
7738 +
7739 +/*******************************************************************************
7740 + *
7741 + * PCI DMA Channel 8 Configuration Register
7742 + *
7743 + ******************************************************************************/
7744 +enum
7745 +{
7746 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
7747 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
7748 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
7749 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
7750 +} ;
7751 +
7752 +/*******************************************************************************
7753 + *
7754 + * PCI DMA Channel 9 Configuration Register
7755 + *
7756 + ******************************************************************************/
7757 +enum
7758 +{
7759 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
7760 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
7761 +} ;
7762 +
7763 +/*******************************************************************************
7764 + *
7765 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7766 + *
7767 + ******************************************************************************/
7768 +enum {
7769 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
7770 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
7771 + // These are for reads (DMA channel 8)
7772 + PCIDMAD_devcmd_mr_v = 0, //memory read
7773 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
7774 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
7775 + PCIDMAD_devcmd_ior_v = 3, //I/O read
7776 + // These are for writes (DMA channel 9)
7777 + PCIDMAD_devcmd_mw_v = 0, //memory write
7778 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
7779 + PCIDMAD_devcmd_iow_v = 3, //I/O write
7780 +
7781 + // Swap byte field applies to both DMA channel 8 and 9
7782 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
7783 + PCIDMAD_sb_m = 0x01000000, // swap byte field
7784 +} ;
7785 +
7786 +
7787 +/*******************************************************************************
7788 + *
7789 + * PCI Target Control Register
7790 + *
7791 + ******************************************************************************/
7792 +enum
7793 +{
7794 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
7795 + PCITC_rtimer_m = 0x000000ff,
7796 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
7797 + PCITC_dtimer_m = 0x0000ff00,
7798 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
7799 + PCITC_rdr_m = 0x00040000,
7800 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
7801 + PCITC_ddt_m = 0x00080000,
7802 +} ;
7803 +/*******************************************************************************
7804 + *
7805 + * PCI messaging unit [applies to both inbound and outbound registers ]
7806 + *
7807 + ******************************************************************************/
7808 +enum
7809 +{
7810 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7811 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
7812 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7813 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
7814 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7815 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
7816 +};
7817 +
7818 +
7819 +
7820 +
7821 +
7822 +
7823 +#define PCI_MSG_VirtualAddress 0xB8088010
7824 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7825 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7826 +
7827 +#define PCIM_SHFT 0x6
7828 +#define PCIM_BIT_LEN 0x7
7829 +#define PCIM_H_EA 0x3
7830 +#define PCIM_H_IA_FIX 0x4
7831 +#define PCIM_H_IA_RR 0x5
7832 +#if 0
7833 +#define PCI_ADDR_START 0x13000000
7834 +#endif
7835 +
7836 +#define PCI_ADDR_START 0x50000000
7837 +
7838 +#define CPUTOPCI_MEM_WIN 0x02000000
7839 +#define CPUTOPCI_IO_WIN 0x00100000
7840 +#define PCILBA_SIZE_SHFT 2
7841 +#define PCILBA_SIZE_MASK 0x1F
7842 +#define SIZE_256MB 0x1C
7843 +#define SIZE_128MB 0x1B
7844 +#define SIZE_64MB 0x1A
7845 +#define SIZE_32MB 0x19
7846 +#define SIZE_16MB 0x18
7847 +#define SIZE_4MB 0x16
7848 +#define SIZE_2MB 0x15
7849 +#define SIZE_1MB 0x14
7850 +#define KORINA_CONFIG0_ADDR 0x80000000
7851 +#define KORINA_CONFIG1_ADDR 0x80000004
7852 +#define KORINA_CONFIG2_ADDR 0x80000008
7853 +#define KORINA_CONFIG3_ADDR 0x8000000C
7854 +#define KORINA_CONFIG4_ADDR 0x80000010
7855 +#define KORINA_CONFIG5_ADDR 0x80000014
7856 +#define KORINA_CONFIG6_ADDR 0x80000018
7857 +#define KORINA_CONFIG7_ADDR 0x8000001C
7858 +#define KORINA_CONFIG8_ADDR 0x80000020
7859 +#define KORINA_CONFIG9_ADDR 0x80000024
7860 +#define KORINA_CONFIG10_ADDR 0x80000028
7861 +#define KORINA_CONFIG11_ADDR 0x8000002C
7862 +#define KORINA_CONFIG12_ADDR 0x80000030
7863 +#define KORINA_CONFIG13_ADDR 0x80000034
7864 +#define KORINA_CONFIG14_ADDR 0x80000038
7865 +#define KORINA_CONFIG15_ADDR 0x8000003C
7866 +#define KORINA_CONFIG16_ADDR 0x80000040
7867 +#define KORINA_CONFIG17_ADDR 0x80000044
7868 +#define KORINA_CONFIG18_ADDR 0x80000048
7869 +#define KORINA_CONFIG19_ADDR 0x8000004C
7870 +#define KORINA_CONFIG20_ADDR 0x80000050
7871 +#define KORINA_CONFIG21_ADDR 0x80000054
7872 +#define KORINA_CONFIG22_ADDR 0x80000058
7873 +#define KORINA_CONFIG23_ADDR 0x8000005C
7874 +#define KORINA_CONFIG24_ADDR 0x80000060
7875 +#define KORINA_CONFIG25_ADDR 0x80000064
7876 +#define KORINA_CMD (PCFG04_command_ioena_m | \
7877 + PCFG04_command_memena_m | \
7878 + PCFG04_command_bmena_m | \
7879 + PCFG04_command_mwinv_m | \
7880 + PCFG04_command_parena_m | \
7881 + PCFG04_command_serrena_m )
7882 +
7883 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
7884 + PCFG04_status_sta_m | \
7885 + PCFG04_status_rta_m | \
7886 + PCFG04_status_rma_m | \
7887 + PCFG04_status_sse_m | \
7888 + PCFG04_status_pe_m)
7889 +
7890 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
7891 +
7892 +#define KORINA_REVID 0
7893 +#define KORINA_CLASS_CODE 0
7894 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
7895 + KORINA_REVID)
7896 +
7897 +#define KORINA_CACHE_LINE_SIZE 4
7898 +#define KORINA_MASTER_LAT 0x3c
7899 +#define KORINA_HEADER_TYPE 0
7900 +#define KORINA_BIST 0
7901 +
7902 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7903 + (KORINA_HEADER_TYPE<<16) | \
7904 + (KORINA_MASTER_LAT<<8) | \
7905 + KORINA_CACHE_LINE_SIZE )
7906 +
7907 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
7908 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
7909 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
7910 + internal Registers */
7911 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
7912 +
7913 +#define KORINA_CNFG4 KORINA_BAR0
7914 +#define KORINA_CNFG5 KORINA_BAR1
7915 +#define KORINA_CNFG6 KORINA_BAR2
7916 +#define KORINA_CNFG7 KORINA_BAR3
7917 +
7918 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7919 +#define KORINA_SUBSYSTEM_ID 0x0214
7920 +#define KORINA_CNFG8 0
7921 +#define KORINA_CNFG9 0
7922 +#define KORINA_CNFG10 0
7923 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7924 + KORINA_SUBSYSTEM_ID)
7925 +#define KORINA_INT_LINE 1
7926 +#define KORINA_INT_PIN 1
7927 +#define KORINA_MIN_GNT 8
7928 +#define KORINA_MAX_LAT 0x38
7929 +#define KORINA_CNFG12 0
7930 +#define KORINA_CNFG13 0
7931 +#define KORINA_CNFG14 0
7932 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
7933 + (KORINA_MIN_GNT<<16) | \
7934 + (KORINA_INT_PIN<<8) | \
7935 + KORINA_INT_LINE)
7936 +#define KORINA_RETRY_LIMIT 0x80
7937 +#define KORINA_TRDY_LIMIT 0x80
7938 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7939 + KORINA_TRDY_LIMIT)
7940 +#define PCI_PBAxC_R 0x0
7941 +#define PCI_PBAxC_RL 0x1
7942 +#define PCI_PBAxC_RM 0x2
7943 +#define SIZE_SHFT 2
7944 +
7945 +#if defined(__MIPSEB__)
7946 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7947 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7948 + PCIPBAC_pp_m | \
7949 + (SIZE_128MB<<SIZE_SHFT) | \
7950 + PCIPBAC_p_m)
7951 +#else
7952 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
7953 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7954 + PCIPBAC_pp_m | \
7955 + (SIZE_128MB<<SIZE_SHFT) | \
7956 + PCIPBAC_p_m)
7957 +#endif
7958 +#define KORINA_CNFG17 KORINA_PBA0C
7959 +#define KORINA_PBA0M 0x0
7960 +#define KORINA_CNFG18 KORINA_PBA0M
7961 +
7962 +#if defined(__MIPSEB__)
7963 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7964 + PCIPBAC_msi_m)
7965 +#else
7966 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
7967 + PCIPBAC_msi_m)
7968 +#endif
7969 +#define KORINA_CNFG19 KORINA_PBA1C
7970 +#define KORINA_PBA1M 0x0
7971 +#define KORINA_CNFG20 KORINA_PBA1M
7972 +
7973 +#if defined(__MIPSEB__)
7974 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7975 + PCIPBAC_msi_m)
7976 +#else
7977 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
7978 + PCIPBAC_msi_m)
7979 +#endif
7980 +#define KORINA_CNFG21 KORINA_PBA2C
7981 +#define KORINA_PBA2M 0x18000000
7982 +#define KORINA_CNFG22 KORINA_PBA2M
7983 +#define KORINA_PBA3C 0
7984 +#define KORINA_CNFG23 KORINA_PBA3C
7985 +#define KORINA_PBA3M 0
7986 +#define KORINA_CNFG24 KORINA_PBA3M
7987 +
7988 +
7989 +
7990 +#define PCITC_DTIMER_VAL 8
7991 +#define PCITC_RTIMER_VAL 0x10
7992 +
7993 +
7994 +
7995 +
7996 +#endif // __IDT_PCI_H__
7997 +
7998 +
7999 +
8000 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
8001 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
8002 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-03-20 14:25:10.000000000 +0100
8003 @@ -0,0 +1,119 @@
8004 +/**************************************************************************
8005 + *
8006 + * BRIEF MODULE DESCRIPTION
8007 + * Reset register definitions.
8008 + *
8009 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8010 + *
8011 + * This program is free software; you can redistribute it and/or modify it
8012 + * under the terms of the GNU General Public License as published by the
8013 + * Free Software Foundation; either version 2 of the License, or (at your
8014 + * option) any later version.
8015 + *
8016 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8017 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8018 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8019 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8020 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8021 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8022 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8023 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8024 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8025 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8026 + *
8027 + * You should have received a copy of the GNU General Public License along
8028 + * with this program; if not, write to the Free Software Foundation, Inc.,
8029 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8030 + *
8031 + *
8032 + **************************************************************************
8033 + * May 2004 rkt, neb.
8034 + *
8035 + * Initial Release
8036 + *
8037 + *
8038 + *
8039 + **************************************************************************
8040 + */
8041 +
8042 +#ifndef __IDT_RST_H__
8043 +#define __IDT_RST_H__
8044 +
8045 +enum
8046 +{
8047 + RST0_PhysicalAddress = 0x18000000,
8048 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
8049 +
8050 + RST0_VirtualAddress = 0xb8000000,
8051 + RST_VirtualAddress = RST0_VirtualAddress, // Default
8052 +} ;
8053 +
8054 +typedef struct RST_s
8055 +{
8056 + u32 filler [0x0006] ;
8057 + u32 sysid ;
8058 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
8059 + u32 reset ;
8060 + u32 bcv ;
8061 + u32 cea ;
8062 +} volatile * RST_t ;
8063 +
8064 +enum
8065 +{
8066 + SYSID_rev_b = 0,
8067 + SYSID_rev_m = 0x000000ff,
8068 + SYSID_imp_b = 8,
8069 + SYSID_imp_m = 0x000fff00,
8070 + SYSID_vendor_b = 8,
8071 + SYSID_vendor_m = 0xfff00000,
8072 +
8073 + BCV_pll_b = 0,
8074 + BCV_pll_m = 0x0000000f,
8075 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
8076 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
8077 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
8078 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
8079 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
8080 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
8081 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
8082 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
8083 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
8084 + BCV_pll_Res9_v = 0x9,
8085 + BCV_pll_Res10_v = 0xa,
8086 + BCV_pll_Res11_v = 0xb,
8087 + BCV_pll_Res12_v = 0xc,
8088 + BCV_pll_Res13_v = 0xd,
8089 + BCV_pll_Res14_v = 0xe,
8090 + BCV_pll_Res15_v = 0xf,
8091 + BCV_clkDiv_b = 4,
8092 + BCV_clkDiv_m = 0x00000030,
8093 + BCV_clkDiv_Div1_v = 0x0,
8094 + BCV_clkDiv_Div2_v = 0x1,
8095 + BCV_clkDiv_Div4_v = 0x2,
8096 + BCV_clkDiv_Res3_v = 0x3,
8097 + BCV_bigEndian_b = 6,
8098 + BCV_bigEndian_m = 0x00000040,
8099 + BCV_resetFast_b = 7,
8100 + BCV_resetFast_m = 0x00000080,
8101 + BCV_pciMode_b = 8,
8102 + BCV_pciMode_m = 0x00000700,
8103 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
8104 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
8105 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
8106 + BCV_pciMode_external_v = 3, // host, external arbiter.
8107 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
8108 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
8109 + BCV_pciMode_res6_v = 6,
8110 + BCV_pciMode_res7_v = 7,
8111 + BCV_watchDisable_b = 11,
8112 + BCV_watchDisable_m = 0x00000800,
8113 + BCV_res12_b = 12,
8114 + BCV_res12_m = 0x00001000,
8115 + BCV_res13_b = 13,
8116 + BCV_res13_m = 0x00002000,
8117 + BCV_res14_b = 14,
8118 + BCV_res14_m = 0x00004000,
8119 + BCV_res15_b = 15,
8120 + BCV_res15_m = 0x00008000,
8121 +} ;
8122 +#endif // __IDT_RST_H__
8123 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8124 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
8125 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-03-20 14:25:10.000000000 +0100
8126 @@ -0,0 +1,120 @@
8127 +/**************************************************************************
8128 + *
8129 + * BRIEF MODULE DESCRIPTION
8130 + * Serial Peripheral Interface register definitions.
8131 + *
8132 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8133 + *
8134 + * This program is free software; you can redistribute it and/or modify it
8135 + * under the terms of the GNU General Public License as published by the
8136 + * Free Software Foundation; either version 2 of the License, or (at your
8137 + * option) any later version.
8138 + *
8139 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8140 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8141 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8142 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8143 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8144 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8145 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8146 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8147 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8148 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8149 + *
8150 + * You should have received a copy of the GNU General Public License along
8151 + * with this program; if not, write to the Free Software Foundation, Inc.,
8152 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8153 + *
8154 + *
8155 + **************************************************************************
8156 + * May 2004 rkt, neb.
8157 + *
8158 + * Initial Release
8159 + *
8160 + *
8161 + *
8162 + **************************************************************************
8163 + */
8164 +
8165 +#ifndef __IDT_SPI_H__
8166 +#define __IDT_SPI_H__
8167 +
8168 +enum
8169 +{
8170 + SPI0_PhysicalAddress = 0x18070000,
8171 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
8172 +
8173 + SPI0_VirtualAddress = 0xB8070000,
8174 + SPI_VirtualAddress = SPI0_VirtualAddress,
8175 +} ;
8176 +
8177 +typedef struct
8178 +{
8179 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8180 + u32 spc ; // spi control reg use SPC_
8181 + u32 sps ; // spi status reg use SPS_
8182 + u32 spd ; // spi data reg use SPD_
8183 + u32 siofunc ; // serial IO function use SIOFUNC_
8184 + u32 siocfg ; // serial IO config use SIOCFG_
8185 + u32 siod; // serial IO data use SIOD_
8186 +} volatile *SPI_t ;
8187 +
8188 +enum
8189 +{
8190 + SPCP_div_b = 0,
8191 + SPCP_div_m = 0x000000ff,
8192 + SPC_spr_b = 0,
8193 + SPC_spr_m = 0x00000003,
8194 + SPC_spr_div2_v = 0,
8195 + SPC_spr_div4_v = 1,
8196 + SPC_spr_div16_v = 2,
8197 + SPC_spr_div32_v = 3,
8198 + SPC_cpha_b = 2,
8199 + SPC_cpha_m = 0x00000004,
8200 + SPC_cpol_b = 3,
8201 + SPC_cpol_m = 0x00000008,
8202 + SPC_mstr_b = 4,
8203 + SPC_mstr_m = 0x00000010,
8204 + SPC_spe_b = 6,
8205 + SPC_spe_m = 0x00000040,
8206 + SPC_spie_b = 7,
8207 + SPC_spie_m = 0x00000080,
8208 +
8209 + SPS_modf_b = 4,
8210 + SPS_modf_m = 0x00000010,
8211 + SPS_wcol_b = 6,
8212 + SPS_wcol_m = 0x00000040,
8213 + SPS_spif_b = 7,
8214 + SPS_spif_m = 0x00000070,
8215 +
8216 + SPD_data_b = 0,
8217 + SPD_data_m = 0x000000ff,
8218 +
8219 + SIOFUNC_sdo_b = 0,
8220 + SIOFUNC_sdo_m = 0x00000001,
8221 + SIOFUNC_sdi_b = 1,
8222 + SIOFUNC_sdi_m = 0x00000002,
8223 + SIOFUNC_sck_b = 2,
8224 + SIOFUNC_sck_m = 0x00000004,
8225 + SIOFUNC_pci_b = 3,
8226 + SIOFUNC_pci_m = 0x00000008,
8227 +
8228 + SIOCFG_sdo_b = 0,
8229 + SIOCFG_sdo_m = 0x00000001,
8230 + SIOCFG_sdi_b = 1,
8231 + SIOCFG_sdi_m = 0x00000002,
8232 + SIOCFG_sck_b = 2,
8233 + SIOCFG_sck_m = 0x00000004,
8234 + SIOCFG_pci_b = 3,
8235 + SIOCFG_pci_m = 0x00000008,
8236 +
8237 + SIOD_sdo_b = 0,
8238 + SIOD_sdo_m = 0x00000001,
8239 + SIOD_sdi_b = 1,
8240 + SIOD_sdi_m = 0x00000002,
8241 + SIOD_sck_b = 2,
8242 + SIOD_sck_m = 0x00000004,
8243 + SIOD_pci_b = 3,
8244 + SIOD_pci_m = 0x00000008,
8245 +} ;
8246 +#endif // __IDT_SPI_H__
8247 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8248 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
8249 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-03-20 14:25:10.000000000 +0100
8250 @@ -0,0 +1,91 @@
8251 +/**************************************************************************
8252 + *
8253 + * BRIEF MODULE DESCRIPTION
8254 + * Definitions for timer registers
8255 + *
8256 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8257 + *
8258 + * This program is free software; you can redistribute it and/or modify it
8259 + * under the terms of the GNU General Public License as published by the
8260 + * Free Software Foundation; either version 2 of the License, or (at your
8261 + * option) any later version.
8262 + *
8263 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8264 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8265 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8266 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8267 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8268 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8269 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8270 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8271 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8272 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8273 + *
8274 + * You should have received a copy of the GNU General Public License along
8275 + * with this program; if not, write to the Free Software Foundation, Inc.,
8276 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8277 + *
8278 + *
8279 + **************************************************************************
8280 + * May 2004 rkt,neb.
8281 + *
8282 + * Initial Release
8283 + *
8284 + *
8285 + *
8286 + **************************************************************************
8287 + */
8288 +
8289 +#ifndef __IDT_TIM_H__
8290 +#define __IDT_TIM_H__
8291 +
8292 +enum
8293 +{
8294 + TIM0_PhysicalAddress = 0x18028000,
8295 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
8296 +
8297 + TIM0_VirtualAddress = 0xb8028000,
8298 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
8299 +} ;
8300 +
8301 +enum
8302 +{
8303 + TIM_Count = 3,
8304 +} ;
8305 +
8306 +struct TIM_CNTR_s
8307 +{
8308 + u32 count ;
8309 + u32 compare ;
8310 + u32 ctc ; //use CTC_
8311 +} ;
8312 +
8313 +typedef struct TIM_s
8314 +{
8315 + struct TIM_CNTR_s tim [TIM_Count] ;
8316 + u32 rcount ; //use RCOUNT_
8317 + u32 rcompare ; //use RCOMPARE_
8318 + u32 rtc ; //use RTC_
8319 +} volatile * TIM_t ;
8320 +
8321 +enum
8322 +{
8323 + CTC_en_b = 0,
8324 + CTC_en_m = 0x00000001,
8325 + CTC_to_b = 1,
8326 + CTC_to_m = 0x00000002,
8327 +
8328 + RCOUNT_count_b = 0,
8329 + RCOUNT_count_m = 0x0000ffff,
8330 + RCOMPARE_compare_b = 0,
8331 + RCOMPARE_compare_m = 0x0000ffff,
8332 + RTC_ce_b = 0,
8333 + RTC_ce_m = 0x00000001,
8334 + RTC_to_b = 1,
8335 + RTC_to_m = 0x00000002,
8336 + RTC_rqe_b = 2,
8337 + RTC_rqe_m = 0x00000004,
8338 +
8339 +} ;
8340 +#endif // __IDT_TIM_H__
8341 +
8342 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8343 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
8344 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-03-20 14:25:10.000000000 +0100
8345 @@ -0,0 +1,189 @@
8346 +/**************************************************************************
8347 + *
8348 + * BRIEF MODULE DESCRIPTION
8349 + * UART register definitions
8350 + *
8351 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8352 + *
8353 + * This program is free software; you can redistribute it and/or modify it
8354 + * under the terms of the GNU General Public License as published by the
8355 + * Free Software Foundation; either version 2 of the License, or (at your
8356 + * option) any later version.
8357 + *
8358 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8359 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8360 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8361 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8362 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8363 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8364 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8365 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8366 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8367 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8368 + *
8369 + * You should have received a copy of the GNU General Public License along
8370 + * with this program; if not, write to the Free Software Foundation, Inc.,
8371 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8372 + *
8373 + *
8374 + **************************************************************************
8375 + * May 2004 rkt, neb.
8376 + *
8377 + * Initial Release
8378 + *
8379 + *
8380 + *
8381 + **************************************************************************
8382 + */
8383 +
8384 +#ifndef __IDT_UART_H__
8385 +#define __IDT_UART_H__
8386 +
8387 +enum
8388 +{
8389 + UART0_PhysicalAddress = 0x1c000000,
8390 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
8391 +
8392 + UART0_VirtualAddress = 0xbc000000,
8393 + UART_VirtualAddress = UART0_VirtualAddress, // Default
8394 +} ;
8395 +
8396 +/*
8397 + * Register definitions are in bytes so we can handle endian problems.
8398 + */
8399 +
8400 +typedef struct UART_s
8401 +{
8402 + union
8403 + {
8404 + u32 const uartrb ; // 0x00 - DLAB=0, read.
8405 + u32 uartth ; // 0x00 - DLAB=0, write.
8406 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
8407 + } ;
8408 +
8409 + union
8410 + {
8411 + u32 uartie ; // 0x04 - DLAB=0, read/write.
8412 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
8413 + } ;
8414 + union
8415 + {
8416 + u32 const uartii ; // 0x08 - DLAB=0, read.
8417 + u32 uartfc ; // 0x08 - DLAB=0, write.
8418 + } ;
8419 +
8420 + u32 uartlc ; // 0x0c
8421 + u32 uartmc ; // 0x10
8422 + u32 uartls ; // 0x14
8423 + u32 uartms ; // 0x18
8424 + u32 uarts ; // 0x1c
8425 +} volatile *UART_t ;
8426 +
8427 +// Reset registers.
8428 +typedef u32 volatile *UARTRR_t ;
8429 +
8430 +enum
8431 +{
8432 + UARTIE_rda_b = 0,
8433 + UARTIE_rda_m = 0x00000001,
8434 + UARTIE_the_b = 1,
8435 + UARTIE_the_m = 0x00000002,
8436 + UARTIE_rls_b = 2,
8437 + UARTIE_rls_m = 0x00000004,
8438 + UARTIE_ems_b = 3,
8439 + UARTIE_ems_m = 0x00000008,
8440 +
8441 + UARTII_pi_b = 0,
8442 + UARTII_pi_m = 0x00000001,
8443 + UARTII_iid_b = 1,
8444 + UARTII_iid_m = 0x0000000e,
8445 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
8446 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
8447 + UARTII_iid_rda_v = 2, // Receive data available
8448 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
8449 + UARTII_iid_res4_v = 4, // reserved.
8450 + UARTII_iid_res5_v = 5, // reserved.
8451 + UARTII_iid_cto_v = 6, // Character timeout.
8452 + UARTII_iid_res7_v = 7, // reserved.
8453 +
8454 + UARTFC_en_b = 0,
8455 + UARTFC_en_m = 0x00000001,
8456 + UARTFC_rr_b = 1,
8457 + UARTFC_rr_m = 0x00000002,
8458 + UARTFC_tr_b = 2,
8459 + UARTFC_tr_m = 0x00000004,
8460 + UARTFC_dms_b = 3,
8461 + UARTFC_dms_m = 0x00000008,
8462 + UARTFC_rt_b = 6,
8463 + UARTFC_rt_m = 0x000000c0,
8464 + UARTFC_rt_1Byte_v = 0,
8465 + UARTFC_rt_4Byte_v = 1,
8466 + UARTFC_rt_8Byte_v = 2,
8467 + UARTFC_rt_14Byte_v = 3,
8468 +
8469 + UARTLC_wls_b = 0,
8470 + UARTLC_wls_m = 0x00000003,
8471 + UARTLC_wls_5Bits_v = 0,
8472 + UARTLC_wls_6Bits_v = 1,
8473 + UARTLC_wls_7Bits_v = 2,
8474 + UARTLC_wls_8Bits_v = 3,
8475 + UARTLC_stb_b = 2,
8476 + UARTLC_stb_m = 0x00000004,
8477 + UARTLC_pen_b = 3,
8478 + UARTLC_pen_m = 0x00000008,
8479 + UARTLC_eps_b = 4,
8480 + UARTLC_eps_m = 0x00000010,
8481 + UARTLC_sp_b = 5,
8482 + UARTLC_sp_m = 0x00000020,
8483 + UARTLC_sb_b = 6,
8484 + UARTLC_sb_m = 0x00000040,
8485 + UARTLC_dlab_b = 7,
8486 + UARTLC_dlab_m = 0x00000080,
8487 +
8488 + UARTMC_dtr_b = 0,
8489 + UARTMC_dtr_m = 0x00000001,
8490 + UARTMC_rts_b = 1,
8491 + UARTMC_rts_m = 0x00000002,
8492 + UARTMC_o1_b = 2,
8493 + UARTMC_o1_m = 0x00000004,
8494 + UARTMC_o2_b = 3,
8495 + UARTMC_o2_m = 0x00000008,
8496 + UARTMC_lp_b = 4,
8497 + UARTMC_lp_m = 0x00000010,
8498 +
8499 + UARTLS_dr_b = 0,
8500 + UARTLS_dr_m = 0x00000001,
8501 + UARTLS_oe_b = 1,
8502 + UARTLS_oe_m = 0x00000002,
8503 + UARTLS_pe_b = 2,
8504 + UARTLS_pe_m = 0x00000004,
8505 + UARTLS_fe_b = 3,
8506 + UARTLS_fe_m = 0x00000008,
8507 + UARTLS_bi_b = 4,
8508 + UARTLS_bi_m = 0x00000010,
8509 + UARTLS_thr_b = 5,
8510 + UARTLS_thr_m = 0x00000020,
8511 + UARTLS_te_b = 6,
8512 + UARTLS_te_m = 0x00000040,
8513 + UARTLS_rfe_b = 7,
8514 + UARTLS_rfe_m = 0x00000080,
8515 +
8516 + UARTMS_dcts_b = 0,
8517 + UARTMS_dcts_m = 0x00000001,
8518 + UARTMS_ddsr_b = 1,
8519 + UARTMS_ddsr_m = 0x00000002,
8520 + UARTMS_teri_b = 2,
8521 + UARTMS_teri_m = 0x00000004,
8522 + UARTMS_ddcd_b = 3,
8523 + UARTMS_ddcd_m = 0x00000008,
8524 + UARTMS_cts_b = 4,
8525 + UARTMS_cts_m = 0x00000010,
8526 + UARTMS_dsr_b = 5,
8527 + UARTMS_dsr_m = 0x00000020,
8528 + UARTMS_ri_b = 6,
8529 + UARTMS_ri_m = 0x00000040,
8530 + UARTMS_dcd_b = 7,
8531 + UARTMS_dcd_m = 0x00000080,
8532 +} ;
8533 +
8534 +#endif // __IDT_UART_H__
8535 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8536 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
8537 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-03-20 14:25:10.000000000 +0100
8538 @@ -0,0 +1,231 @@
8539 +/**************************************************************************
8540 + *
8541 + * BRIEF MODULE DESCRIPTION
8542 + * Register definitions for IDT RC32438 DMA.
8543 + *
8544 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8545 + *
8546 + * This program is free software; you can redistribute it and/or modify it
8547 + * under the terms of the GNU General Public License as published by the
8548 + * Free Software Foundation; either version 2 of the License, or (at your
8549 + * option) any later version.
8550 + *
8551 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8552 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8553 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8554 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8555 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8556 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8557 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8558 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8559 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8560 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8561 + *
8562 + * You should have received a copy of the GNU General Public License along
8563 + * with this program; if not, write to the Free Software Foundation, Inc.,
8564 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8565 + *
8566 + *
8567 + **************************************************************************
8568 + * May 2004 P. Sadik.
8569 + *
8570 + * Initial Release
8571 + *
8572 + *
8573 + *
8574 + **************************************************************************
8575 + */
8576 +#ifndef __IDT_RC32438_DMA_H__
8577 +#define __IDT_RC32438_DMA_H__
8578 +enum
8579 +{
8580 + DMA0_PhysicalAddress = 0x18040000,
8581 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
8582 +
8583 + DMA0_VirtualAddress = 0xb8040000,
8584 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
8585 +} ;
8586 +
8587 +/*
8588 + * DMA descriptor (in physical memory).
8589 + */
8590 +
8591 +typedef struct DMAD_s
8592 +{
8593 + u32 control ; // Control. use DMAD_*
8594 + u32 ca ; // Current Address.
8595 + u32 devcs ; // Device control and status.
8596 + u32 link ; // Next descriptor in chain.
8597 +} volatile *DMAD_t ;
8598 +
8599 +enum
8600 +{
8601 + DMAD_size = sizeof (struct DMAD_s),
8602 + DMAD_count_b = 0, // in DMAD_t -> control
8603 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
8604 + DMAD_ds_b = 20, // in DMAD_t -> control
8605 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
8606 + DMAD_ds_extToMem0_v = 0,
8607 + DMAD_ds_memToExt0_v = 1,
8608 + DMAD_ds_extToMem1_v = 0,
8609 + DMAD_ds_memToExt1_v = 1,
8610 + DMAD_ds_ethRcv0_v = 0,
8611 + DMAD_ds_ethXmt0_v = 0,
8612 + DMAD_ds_ethRcv1_v = 0,
8613 + DMAD_ds_ethXmt2_v = 0,
8614 + DMAD_ds_memToFifo_v = 0,
8615 + DMAD_ds_fifoToMem_v = 0,
8616 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
8617 + DMAD_ds_pciToMem_v = 0,
8618 + DMAD_ds_memToPci_v = 0,
8619 + DMAD_ds_securityInput_v = 0,
8620 + DMAD_ds_securityOutput_v = 0,
8621 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
8622 +
8623 + DMAD_devcmd_b = 22, // in DMAD_t -> control
8624 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
8625 + DMAD_devcmd_byte_v = 0, //memory-to-memory
8626 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
8627 + DMAD_devcmd_word_v = 2, //memory-to-memory
8628 + DMAD_devcmd_2words_v = 3, //memory-to-memory
8629 + DMAD_devcmd_4words_v = 4, //memory-to-memory
8630 + DMAD_devcmd_6words_v = 5, //memory-to-memory
8631 + DMAD_devcmd_8words_v = 6, //memory-to-memory
8632 + DMAD_devcmd_16words_v = 7, //memory-to-memory
8633 + DMAD_cof_b = 25, // chain on finished
8634 + DMAD_cof_m = 0x02000000, //
8635 + DMAD_cod_b = 26, // chain on done
8636 + DMAD_cod_m = 0x04000000, //
8637 + DMAD_iof_b = 27, // interrupt on finished
8638 + DMAD_iof_m = 0x08000000, //
8639 + DMAD_iod_b = 28, // interrupt on done
8640 + DMAD_iod_m = 0x10000000, //
8641 + DMAD_t_b = 29, // terminated
8642 + DMAD_t_m = 0x20000000, //
8643 + DMAD_d_b = 30, // done
8644 + DMAD_d_m = 0x40000000, //
8645 + DMAD_f_b = 31, // finished
8646 + DMAD_f_m = 0x80000000, //
8647 +} ;
8648 +
8649 +/*
8650 + * DMA register (within Internal Register Map).
8651 + */
8652 +
8653 +struct DMA_Chan_s
8654 +{
8655 + u32 dmac ; // Control.
8656 + u32 dmas ; // Status.
8657 + u32 dmasm ; // Mask.
8658 + u32 dmadptr ; // Descriptor pointer.
8659 + u32 dmandptr ; // Next descriptor pointer.
8660 +};
8661 +
8662 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8663 +
8664 +//DMA_Channels use DMACH_count instead
8665 +
8666 +enum
8667 +{
8668 + DMAC_run_b = 0, //
8669 + DMAC_run_m = 0x00000001, //
8670 + DMAC_dm_b = 1, // done mask
8671 + DMAC_dm_m = 0x00000002, //
8672 + DMAC_mode_b = 2, //
8673 + DMAC_mode_m = 0x0000000c, //
8674 + DMAC_mode_auto_v = 0,
8675 + DMAC_mode_burst_v = 1,
8676 + DMAC_mode_transfer_v = 2, //usually used
8677 + DMAC_mode_reserved_v = 3,
8678 + DMAC_a_b = 4, //
8679 + DMAC_a_m = 0x00000010, //
8680 +
8681 + DMAS_f_b = 0, // finished (sticky)
8682 + DMAS_f_m = 0x00000001, //
8683 + DMAS_d_b = 1, // done (sticky)
8684 + DMAS_d_m = 0x00000002, //
8685 + DMAS_c_b = 2, // chain (sticky)
8686 + DMAS_c_m = 0x00000004, //
8687 + DMAS_e_b = 3, // error (sticky)
8688 + DMAS_e_m = 0x00000008, //
8689 + DMAS_h_b = 4, // halt (sticky)
8690 + DMAS_h_m = 0x00000010, //
8691 +
8692 + DMASM_f_b = 0, // finished (1=mask)
8693 + DMASM_f_m = 0x00000001, //
8694 + DMASM_d_b = 1, // done (1=mask)
8695 + DMASM_d_m = 0x00000002, //
8696 + DMASM_c_b = 2, // chain (1=mask)
8697 + DMASM_c_m = 0x00000004, //
8698 + DMASM_e_b = 3, // error (1=mask)
8699 + DMASM_e_m = 0x00000008, //
8700 + DMASM_h_b = 4, // halt (1=mask)
8701 + DMASM_h_m = 0x00000010, //
8702 +} ;
8703 +
8704 +/*
8705 + * DMA channel definitions
8706 + */
8707 +
8708 +enum
8709 +{
8710 + DMACH_extToMem0 = 0,
8711 + DMACH_memToExt0 = 0,
8712 + DMACH_extToMem1 = 1,
8713 + DMACH_memToExt1 = 1,
8714 + DMACH_ethRcv0 = 2,
8715 + DMACH_ethXmt0 = 3,
8716 + DMACH_ethRcv1 = 4,
8717 + DMACH_ethXmt2 = 5,
8718 + DMACH_memToFifo = 6,
8719 + DMACH_fifoToMem = 7,
8720 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8721 + DMACH_pciToMem = 8,
8722 + DMACH_memToPci = 9,
8723 + DMACH_securityInput = 10,
8724 + DMACH_securityOutput = 11,
8725 + DMACH_rng_se = 12, //randomNumberGenerator on SE
8726 +
8727 + DMACH_count //must be last
8728 +};
8729 +
8730 +
8731 +typedef struct DMAC_s
8732 +{
8733 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8734 +} volatile *DMA_t ;
8735 +
8736 +
8737 +/*
8738 + * External DMA parameters
8739 +*/
8740 +
8741 +enum
8742 +{
8743 + DMADEVCMD_ts_b = 0, // ts field in devcmd
8744 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
8745 + DMADEVCMD_ts_byte_v = 0,
8746 + DMADEVCMD_ts_halfword_v = 1,
8747 + DMADEVCMD_ts_word_v = 2,
8748 + DMADEVCMD_ts_2word_v = 3,
8749 + DMADEVCMD_ts_4word_v = 4,
8750 + DMADEVCMD_ts_6word_v = 5,
8751 + DMADEVCMD_ts_8word_v = 6,
8752 + DMADEVCMD_ts_16word_v = 7
8753 +};
8754 +
8755 +
8756 +#if 1 // aws - Compatibility.
8757 +# define EXTDMA_ts_b DMADEVCMD_ts_b
8758 +# define EXTDMA_ts_m DMADEVCMD_ts_m
8759 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
8760 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
8761 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
8762 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
8763 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
8764 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
8765 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
8766 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
8767 +#endif // aws - Compatibility.
8768 +
8769 +#endif //__IDT_RC32438_DMA_H__
8770 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8771 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
8772 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-03-20 14:25:10.000000000 +0100
8773 @@ -0,0 +1,82 @@
8774 +/**************************************************************************
8775 + *
8776 + * BRIEF MODULE DESCRIPTION
8777 + * DMA operations for IDT RC32438.
8778 + *
8779 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8780 + *
8781 + * This program is free software; you can redistribute it and/or modify it
8782 + * under the terms of the GNU General Public License as published by the
8783 + * Free Software Foundation; either version 2 of the License, or (at your
8784 + * option) any later version.
8785 + *
8786 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8787 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8788 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8789 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8790 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8791 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8792 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8793 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8794 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8795 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8796 + *
8797 + * You should have received a copy of the GNU General Public License along
8798 + * with this program; if not, write to the Free Software Foundation, Inc.,
8799 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8800 + *
8801 + *
8802 + **************************************************************************
8803 + * May 2004 P. Sadik.
8804 + *
8805 + * Initial Release
8806 + *
8807 + *
8808 + *
8809 + **************************************************************************
8810 + */
8811 +
8812 +#ifndef __IDT_RC32438_DMA_V_H__
8813 +#define __IDT_RC32438_DMA_V_H__
8814 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
8815 +
8816 +#define DMA_CHAN_OFFSET 0x14
8817 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8818 +#define DMA_COUNT(count) \
8819 + ((count) & DMAD_count_m)
8820 +
8821 +#define DMA_HALT_TIMEOUT 500
8822 +
8823 +
8824 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8825 +{
8826 + int timeout=1;
8827 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8828 + rc32438_writel(0, &ch->dmac);
8829 +
8830 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8831 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8832 + rc32438_writel(0, &ch->dmas);
8833 + break;
8834 + }
8835 + }
8836 +
8837 + }
8838 +
8839 + return timeout ? 0 : 1;
8840 +}
8841 +
8842 +
8843 +
8844 +
8845 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8846 +{
8847 + rc32438_writel(0, &ch->dmandptr);
8848 + rc32438_writel(dma_addr, &ch->dmadptr);
8849 +}
8850 +
8851 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8852 +{
8853 + rc32438_writel(dma_addr, &ch->dmandptr);
8854 +}
8855 +#endif //__IDT_RC32438_DMA_V_H__
8856 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8857 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
8858 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-03-20 14:25:10.000000000 +0100
8859 @@ -0,0 +1,328 @@
8860 +/**************************************************************************
8861 + *
8862 + * BRIEF MODULE DESCRIPTION
8863 + * Definitions for IDT EB438 ethernet
8864 + *
8865 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8866 + *
8867 + * This program is free software; you can redistribute it and/or modify it
8868 + * under the terms of the GNU General Public License as published by the
8869 + * Free Software Foundation; either version 2 of the License, or (at your
8870 + * option) any later version.
8871 + *
8872 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8873 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8874 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8875 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8876 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8877 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8878 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8879 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8880 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8881 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8882 + *
8883 + * You should have received a copy of the GNU General Public License along
8884 + * with this program; if not, write to the Free Software Foundation, Inc.,
8885 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8886 + *
8887 + *
8888 + **************************************************************************
8889 + * May 2004 P. Sadik.
8890 + *
8891 + * Initial Release
8892 + *
8893 + *
8894 + *
8895 + **************************************************************************
8896 + */
8897 +
8898 +#ifndef __IDT_RC32438_ETH_H__
8899 +#define __IDT_RC32438_ETH_H__
8900 +enum
8901 +{
8902 + ETH0_PhysicalAddress = 0x18058000,
8903 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
8904 +
8905 + ETH0_VirtualAddress = 0xb8058000,
8906 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
8907 + ETH1_PhysicalAddress = 0x18060000,
8908 + ETH1_VirtualAddress = 0xb8060000, // Default
8909 +} ;
8910 +
8911 +typedef struct
8912 +{
8913 + u32 ethintfc ;
8914 + u32 ethfifott ;
8915 + u32 etharc ;
8916 + u32 ethhash0 ;
8917 + u32 ethhash1 ;
8918 + u32 ethu0 [4] ; // Reserved.
8919 + u32 ethpfs ;
8920 + u32 ethmcp ;
8921 + u32 eth_u1 [10] ; // Reserved.
8922 + u32 ethspare ;
8923 + u32 eth_u2 [42] ; // Reserved.
8924 + u32 ethsal0 ;
8925 + u32 ethsah0 ;
8926 + u32 ethsal1 ;
8927 + u32 ethsah1 ;
8928 + u32 ethsal2 ;
8929 + u32 ethsah2 ;
8930 + u32 ethsal3 ;
8931 + u32 ethsah3 ;
8932 + u32 ethrbc ;
8933 + u32 ethrpc ;
8934 + u32 ethrupc ;
8935 + u32 ethrfc ;
8936 + u32 ethtbc ;
8937 + u32 ethgpf ;
8938 + u32 eth_u9 [50] ; // Reserved.
8939 + u32 ethmac1 ;
8940 + u32 ethmac2 ;
8941 + u32 ethipgt ;
8942 + u32 ethipgr ;
8943 + u32 ethclrt ;
8944 + u32 ethmaxf ;
8945 + u32 eth_u10 ; // Reserved.
8946 + u32 ethmtest ;
8947 + u32 miimcfg ;
8948 + u32 miimcmd ;
8949 + u32 miimaddr ;
8950 + u32 miimwtd ;
8951 + u32 miimrdd ;
8952 + u32 miimind ;
8953 + u32 eth_u11 ; // Reserved.
8954 + u32 eth_u12 ; // Reserved.
8955 + u32 ethcfsa0 ;
8956 + u32 ethcfsa1 ;
8957 + u32 ethcfsa2 ;
8958 +} volatile *ETH_t;
8959 +
8960 +enum
8961 +{
8962 + ETHINTFC_en_b = 0,
8963 + ETHINTFC_en_m = 0x00000001,
8964 + ETHINTFC_its_b = 1,
8965 + ETHINTFC_its_m = 0x00000002,
8966 + ETHINTFC_rip_b = 2,
8967 + ETHINTFC_rip_m = 0x00000004,
8968 + ETHINTFC_jam_b = 3,
8969 + ETHINTFC_jam_m = 0x00000008,
8970 + ETHINTFC_ovr_b = 4,
8971 + ETHINTFC_ovr_m = 0x00000010,
8972 + ETHINTFC_und_b = 5,
8973 + ETHINTFC_und_m = 0x00000020,
8974 +
8975 + ETHFIFOTT_tth_b = 0,
8976 + ETHFIFOTT_tth_m = 0x0000007f,
8977 +
8978 + ETHARC_pro_b = 0,
8979 + ETHARC_pro_m = 0x00000001,
8980 + ETHARC_am_b = 1,
8981 + ETHARC_am_m = 0x00000002,
8982 + ETHARC_afm_b = 2,
8983 + ETHARC_afm_m = 0x00000004,
8984 + ETHARC_ab_b = 3,
8985 + ETHARC_ab_m = 0x00000008,
8986 +
8987 + ETHSAL_byte5_b = 0,
8988 + ETHSAL_byte5_m = 0x000000ff,
8989 + ETHSAL_byte4_b = 8,
8990 + ETHSAL_byte4_m = 0x0000ff00,
8991 + ETHSAL_byte3_b = 16,
8992 + ETHSAL_byte3_m = 0x00ff0000,
8993 + ETHSAL_byte2_b = 24,
8994 + ETHSAL_byte2_m = 0xff000000,
8995 +
8996 + ETHSAH_byte1_b = 0,
8997 + ETHSAH_byte1_m = 0x000000ff,
8998 + ETHSAH_byte0_b = 8,
8999 + ETHSAH_byte0_m = 0x0000ff00,
9000 +
9001 + ETHGPF_ptv_b = 0,
9002 + ETHGPF_ptv_m = 0x0000ffff,
9003 +
9004 + ETHPFS_pfd_b = 0,
9005 + ETHPFS_pfd_m = 0x00000001,
9006 +
9007 + ETHCFSA0_cfsa4_b = 0,
9008 + ETHCFSA0_cfsa4_m = 0x000000ff,
9009 + ETHCFSA0_cfsa5_b = 8,
9010 + ETHCFSA0_cfsa5_m = 0x0000ff00,
9011 +
9012 + ETHCFSA1_cfsa2_b = 0,
9013 + ETHCFSA1_cfsa2_m = 0x000000ff,
9014 + ETHCFSA1_cfsa3_b = 8,
9015 + ETHCFSA1_cfsa3_m = 0x0000ff00,
9016 +
9017 + ETHCFSA2_cfsa0_b = 0,
9018 + ETHCFSA2_cfsa0_m = 0x000000ff,
9019 + ETHCFSA2_cfsa1_b = 8,
9020 + ETHCFSA2_cfsa1_m = 0x0000ff00,
9021 +
9022 + ETHMAC1_re_b = 0,
9023 + ETHMAC1_re_m = 0x00000001,
9024 + ETHMAC1_paf_b = 1,
9025 + ETHMAC1_paf_m = 0x00000002,
9026 + ETHMAC1_rfc_b = 2,
9027 + ETHMAC1_rfc_m = 0x00000004,
9028 + ETHMAC1_tfc_b = 3,
9029 + ETHMAC1_tfc_m = 0x00000008,
9030 + ETHMAC1_lb_b = 4,
9031 + ETHMAC1_lb_m = 0x00000010,
9032 + ETHMAC1_mr_b = 31,
9033 + ETHMAC1_mr_m = 0x80000000,
9034 +
9035 + ETHMAC2_fd_b = 0,
9036 + ETHMAC2_fd_m = 0x00000001,
9037 + ETHMAC2_flc_b = 1,
9038 + ETHMAC2_flc_m = 0x00000002,
9039 + ETHMAC2_hfe_b = 2,
9040 + ETHMAC2_hfe_m = 0x00000004,
9041 + ETHMAC2_dc_b = 3,
9042 + ETHMAC2_dc_m = 0x00000008,
9043 + ETHMAC2_cen_b = 4,
9044 + ETHMAC2_cen_m = 0x00000010,
9045 + ETHMAC2_pe_b = 5,
9046 + ETHMAC2_pe_m = 0x00000020,
9047 + ETHMAC2_vpe_b = 6,
9048 + ETHMAC2_vpe_m = 0x00000040,
9049 + ETHMAC2_ape_b = 7,
9050 + ETHMAC2_ape_m = 0x00000080,
9051 + ETHMAC2_ppe_b = 8,
9052 + ETHMAC2_ppe_m = 0x00000100,
9053 + ETHMAC2_lpe_b = 9,
9054 + ETHMAC2_lpe_m = 0x00000200,
9055 + ETHMAC2_nb_b = 12,
9056 + ETHMAC2_nb_m = 0x00001000,
9057 + ETHMAC2_bp_b = 13,
9058 + ETHMAC2_bp_m = 0x00002000,
9059 + ETHMAC2_ed_b = 14,
9060 + ETHMAC2_ed_m = 0x00004000,
9061 +
9062 + ETHIPGT_ipgt_b = 0,
9063 + ETHIPGT_ipgt_m = 0x0000007f,
9064 +
9065 + ETHIPGR_ipgr2_b = 0,
9066 + ETHIPGR_ipgr2_m = 0x0000007f,
9067 + ETHIPGR_ipgr1_b = 8,
9068 + ETHIPGR_ipgr1_m = 0x00007f00,
9069 +
9070 + ETHCLRT_maxret_b = 0,
9071 + ETHCLRT_maxret_m = 0x0000000f,
9072 + ETHCLRT_colwin_b = 8,
9073 + ETHCLRT_colwin_m = 0x00003f00,
9074 +
9075 + ETHMAXF_maxf_b = 0,
9076 + ETHMAXF_maxf_m = 0x0000ffff,
9077 +
9078 + ETHMTEST_tb_b = 2,
9079 + ETHMTEST_tb_m = 0x00000004,
9080 +
9081 + ETHMCP_div_b = 0,
9082 + ETHMCP_div_m = 0x000000ff,
9083 +
9084 + MIIMCFG_rsv_b = 0,
9085 + MIIMCFG_rsv_m = 0x0000000c,
9086 +
9087 + MIIMCMD_rd_b = 0,
9088 + MIIMCMD_rd_m = 0x00000001,
9089 + MIIMCMD_scn_b = 1,
9090 + MIIMCMD_scn_m = 0x00000002,
9091 +
9092 + MIIMADDR_regaddr_b = 0,
9093 + MIIMADDR_regaddr_m = 0x0000001f,
9094 + MIIMADDR_phyaddr_b = 8,
9095 + MIIMADDR_phyaddr_m = 0x00001f00,
9096 +
9097 + MIIMWTD_wdata_b = 0,
9098 + MIIMWTD_wdata_m = 0x0000ffff,
9099 +
9100 + MIIMRDD_rdata_b = 0,
9101 + MIIMRDD_rdata_m = 0x0000ffff,
9102 +
9103 + MIIMIND_bsy_b = 0,
9104 + MIIMIND_bsy_m = 0x00000001,
9105 + MIIMIND_scn_b = 1,
9106 + MIIMIND_scn_m = 0x00000002,
9107 + MIIMIND_nv_b = 2,
9108 + MIIMIND_nv_m = 0x00000004,
9109 +
9110 +} ;
9111 +
9112 +/*
9113 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9114 + */
9115 +enum
9116 +{
9117 + ETHRX_fd_b = 0,
9118 + ETHRX_fd_m = 0x00000001,
9119 + ETHRX_ld_b = 1,
9120 + ETHRX_ld_m = 0x00000002,
9121 + ETHRX_rok_b = 2,
9122 + ETHRX_rok_m = 0x00000004,
9123 + ETHRX_fm_b = 3,
9124 + ETHRX_fm_m = 0x00000008,
9125 + ETHRX_mp_b = 4,
9126 + ETHRX_mp_m = 0x00000010,
9127 + ETHRX_bp_b = 5,
9128 + ETHRX_bp_m = 0x00000020,
9129 + ETHRX_vlt_b = 6,
9130 + ETHRX_vlt_m = 0x00000040,
9131 + ETHRX_cf_b = 7,
9132 + ETHRX_cf_m = 0x00000080,
9133 + ETHRX_ovr_b = 8,
9134 + ETHRX_ovr_m = 0x00000100,
9135 + ETHRX_crc_b = 9,
9136 + ETHRX_crc_m = 0x00000200,
9137 + ETHRX_cv_b = 10,
9138 + ETHRX_cv_m = 0x00000400,
9139 + ETHRX_db_b = 11,
9140 + ETHRX_db_m = 0x00000800,
9141 + ETHRX_le_b = 12,
9142 + ETHRX_le_m = 0x00001000,
9143 + ETHRX_lor_b = 13,
9144 + ETHRX_lor_m = 0x00002000,
9145 + ETHRX_ces_b = 14,
9146 + ETHRX_ces_m = 0x00004000,
9147 + ETHRX_length_b = 16,
9148 + ETHRX_length_m = 0xffff0000,
9149 +
9150 + ETHTX_fd_b = 0,
9151 + ETHTX_fd_m = 0x00000001,
9152 + ETHTX_ld_b = 1,
9153 + ETHTX_ld_m = 0x00000002,
9154 + ETHTX_oen_b = 2,
9155 + ETHTX_oen_m = 0x00000004,
9156 + ETHTX_pen_b = 3,
9157 + ETHTX_pen_m = 0x00000008,
9158 + ETHTX_cen_b = 4,
9159 + ETHTX_cen_m = 0x00000010,
9160 + ETHTX_hen_b = 5,
9161 + ETHTX_hen_m = 0x00000020,
9162 + ETHTX_tok_b = 6,
9163 + ETHTX_tok_m = 0x00000040,
9164 + ETHTX_mp_b = 7,
9165 + ETHTX_mp_m = 0x00000080,
9166 + ETHTX_bp_b = 8,
9167 + ETHTX_bp_m = 0x00000100,
9168 + ETHTX_und_b = 9,
9169 + ETHTX_und_m = 0x00000200,
9170 + ETHTX_of_b = 10,
9171 + ETHTX_of_m = 0x00000400,
9172 + ETHTX_ed_b = 11,
9173 + ETHTX_ed_m = 0x00000800,
9174 + ETHTX_ec_b = 12,
9175 + ETHTX_ec_m = 0x00001000,
9176 + ETHTX_lc_b = 13,
9177 + ETHTX_lc_m = 0x00002000,
9178 + ETHTX_td_b = 14,
9179 + ETHTX_td_m = 0x00004000,
9180 + ETHTX_crc_b = 15,
9181 + ETHTX_crc_m = 0x00008000,
9182 + ETHTX_le_b = 16,
9183 + ETHTX_le_m = 0x00010000,
9184 + ETHTX_cc_b = 17,
9185 + ETHTX_cc_m = 0x001E0000,
9186 +} ;
9187 +#endif //__IDT_RC32438_ETH_H__
9188 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9189 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
9190 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-03-20 14:25:10.000000000 +0100
9191 @@ -0,0 +1,72 @@
9192 +/**************************************************************************
9193 + *
9194 + * BRIEF MODULE DESCRIPTION
9195 + * macros for IDT EB438 ethernet
9196 + *
9197 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9198 + *
9199 + * This program is free software; you can redistribute it and/or modify it
9200 + * under the terms of the GNU General Public License as published by the
9201 + * Free Software Foundation; either version 2 of the License, or (at your
9202 + * option) any later version.
9203 + *
9204 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9205 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9206 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9207 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9208 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9209 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9210 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9211 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9212 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9213 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9214 + *
9215 + * You should have received a copy of the GNU General Public License along
9216 + * with this program; if not, write to the Free Software Foundation, Inc.,
9217 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9218 + *
9219 + *
9220 + **************************************************************************
9221 + * May 2004 P. Sadik.
9222 + *
9223 + * Initial Release
9224 + *
9225 + *
9226 + *
9227 + **************************************************************************
9228 + */
9229 +
9230 +#ifndef __IDT_RC32438_ETH_V_H__
9231 +#define __IDT_RC32438_ETH_V_H__
9232 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
9233 +
9234 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
9235 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
9236 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
9237 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
9238 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
9239 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
9240 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
9241 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
9242 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
9243 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
9244 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
9245 +
9246 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
9247 +
9248 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
9249 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
9250 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
9251 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
9252 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
9253 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
9254 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
9255 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
9256 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
9257 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
9258 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
9259 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
9260 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
9261 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
9262 +
9263 +#endif //__IDT_RC32438_ETH_V_H__
9264 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9265 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
9266 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-03-20 14:25:10.000000000 +0100
9267 @@ -0,0 +1,257 @@
9268 +/**************************************************************************
9269 + *
9270 + * BRIEF MODULE DESCRIPTION
9271 + * Definitions for IDT RC32438 GPIO.
9272 + *
9273 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9274 + *
9275 + * This program is free software; you can redistribute it and/or modify it
9276 + * under the terms of the GNU General Public License as published by the
9277 + * Free Software Foundation; either version 2 of the License, or (at your
9278 + * option) any later version.
9279 + *
9280 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9281 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9282 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9283 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9284 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9285 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9286 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9287 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9288 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9289 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9290 + *
9291 + * You should have received a copy of the GNU General Public License along
9292 + * with this program; if not, write to the Free Software Foundation, Inc.,
9293 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9294 + *
9295 + *
9296 + **************************************************************************
9297 + * May 2004 P. Sadik.
9298 + *
9299 + * Initial Release
9300 + *
9301 + *
9302 + *
9303 + **************************************************************************
9304 + */
9305 +#ifndef __IDT_RC32438_GPIO_H__
9306 +#define __IDT_RC32438_GPIO_H__
9307 +enum
9308 +{
9309 + GPIO0_PhysicalAddress = 0x18048000,
9310 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
9311 +
9312 + GPIO0_VirtualAddress = 0xb8048000,
9313 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
9314 +} ;
9315 +
9316 +typedef struct
9317 +{
9318 + u32 gpiofunc; /* GPIO Function Register
9319 + * gpiofunc[x]==0 bit = gpio
9320 + * func[x]==1 bit = altfunc
9321 + */
9322 + u32 gpiocfg; /* GPIO Configuration Register
9323 + * gpiocfg[x]==0 bit = input
9324 + * gpiocfg[x]==1 bit = output
9325 + */
9326 + u32 gpiod; /* GPIO Data Register
9327 + * gpiod[x] read/write gpio pinX status
9328 + */
9329 + u32 gpioilevel; /* GPIO Interrupt Status Register
9330 + * interrupt level (see gpioistat)
9331 + */
9332 + u32 gpioistat; /* Gpio Interrupt Status Register
9333 + * istat[x] = (gpiod[x] == level[x])
9334 + * cleared in ISR (STICKY bits)
9335 + */
9336 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
9337 +} volatile * GPIO_t ;
9338 +
9339 +typedef enum
9340 +{
9341 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
9342 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
9343 + GPIO_input_v = 0, // gpiocfg use pin as input.
9344 + GPIO_output_v = 1, // gpiocfg use pin as output.
9345 + GPIO_pin0_b = 0,
9346 + GPIO_pin0_m = 0x00000001,
9347 + GPIO_pin1_b = 1,
9348 + GPIO_pin1_m = 0x00000002,
9349 + GPIO_pin2_b = 2,
9350 + GPIO_pin2_m = 0x00000004,
9351 + GPIO_pin3_b = 3,
9352 + GPIO_pin3_m = 0x00000008,
9353 + GPIO_pin4_b = 4,
9354 + GPIO_pin4_m = 0x00000010,
9355 + GPIO_pin5_b = 5,
9356 + GPIO_pin5_m = 0x00000020,
9357 + GPIO_pin6_b = 6,
9358 + GPIO_pin6_m = 0x00000040,
9359 + GPIO_pin7_b = 7,
9360 + GPIO_pin7_m = 0x00000080,
9361 + GPIO_pin8_b = 8,
9362 + GPIO_pin8_m = 0x00000100,
9363 + GPIO_pin9_b = 9,
9364 + GPIO_pin9_m = 0x00000200,
9365 + GPIO_pin10_b = 10,
9366 + GPIO_pin10_m = 0x00000400,
9367 + GPIO_pin11_b = 11,
9368 + GPIO_pin11_m = 0x00000800,
9369 + GPIO_pin12_b = 12,
9370 + GPIO_pin12_m = 0x00001000,
9371 + GPIO_pin13_b = 13,
9372 + GPIO_pin13_m = 0x00002000,
9373 + GPIO_pin14_b = 14,
9374 + GPIO_pin14_m = 0x00004000,
9375 + GPIO_pin15_b = 15,
9376 + GPIO_pin15_m = 0x00008000,
9377 + GPIO_pin16_b = 16,
9378 + GPIO_pin16_m = 0x00010000,
9379 + GPIO_pin17_b = 17,
9380 + GPIO_pin17_m = 0x00020000,
9381 + GPIO_pin18_b = 18,
9382 + GPIO_pin18_m = 0x00040000,
9383 + GPIO_pin19_b = 19,
9384 + GPIO_pin19_m = 0x00080000,
9385 + GPIO_pin20_b = 20,
9386 + GPIO_pin20_m = 0x00100000,
9387 + GPIO_pin21_b = 21,
9388 + GPIO_pin21_m = 0x00200000,
9389 + GPIO_pin22_b = 22,
9390 + GPIO_pin22_m = 0x00400000,
9391 + GPIO_pin23_b = 23,
9392 + GPIO_pin23_m = 0x00800000,
9393 + GPIO_pin24_b = 24,
9394 + GPIO_pin24_m = 0x01000000,
9395 + GPIO_pin25_b = 25,
9396 + GPIO_pin25_m = 0x02000000,
9397 + GPIO_pin26_b = 26,
9398 + GPIO_pin26_m = 0x04000000,
9399 + GPIO_pin27_b = 27,
9400 + GPIO_pin27_m = 0x08000000,
9401 + GPIO_pin28_b = 28,
9402 + GPIO_pin28_m = 0x10000000,
9403 + GPIO_pin29_b = 29,
9404 + GPIO_pin29_m = 0x20000000,
9405 + GPIO_pin30_b = 30,
9406 + GPIO_pin30_m = 0x40000000,
9407 + GPIO_pin31_b = 31,
9408 + GPIO_pin31_m = 0x80000000,
9409 +
9410 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
9411 +
9412 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
9413 + GPIO_u0sout_m = GPIO_pin0_m,
9414 + GPIO_u0sout_cfg_v = GPIO_output_v,
9415 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
9416 + GPIO_u0sinp_m = GPIO_pin1_m,
9417 + GPIO_u0sinp_cfg_v = GPIO_input_v,
9418 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
9419 + GPIO_u0rin_m = GPIO_pin2_m,
9420 + GPIO_u0rin_cfg_v = GPIO_input_v,
9421 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
9422 + GPIO_u0dcdn_m = GPIO_pin3_m,
9423 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
9424 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
9425 + GPIO_u0dtrn_m = GPIO_pin4_m,
9426 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
9427 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
9428 + GPIO_u0dsrn_m = GPIO_pin5_m,
9429 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
9430 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
9431 + GPIO_u0rtsn_m = GPIO_pin6_m,
9432 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
9433 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
9434 + GPIO_u0ctsn_m = GPIO_pin7_m,
9435 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
9436 +
9437 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
9438 + GPIO_u1sout_m = GPIO_pin8_m,
9439 + GPIO_u1sout_cfg_v = GPIO_output_v,
9440 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
9441 + GPIO_u1sinp_m = GPIO_pin9_m,
9442 + GPIO_u1sinp_cfg_v = GPIO_input_v,
9443 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
9444 + GPIO_u1dtrn_m = GPIO_pin10_m,
9445 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
9446 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
9447 + GPIO_u1dsrn_m = GPIO_pin11_m,
9448 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
9449 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
9450 + GPIO_u1rtsn_m = GPIO_pin12_m,
9451 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
9452 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
9453 + GPIO_u1ctsn_m = GPIO_pin13_m,
9454 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
9455 +
9456 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
9457 + GPIO_dmareqn0_m = GPIO_pin14_m,
9458 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
9459 +
9460 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
9461 + GPIO_dmareqn1_m = GPIO_pin15_m,
9462 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
9463 +
9464 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
9465 + GPIO_dmadonen0_m = GPIO_pin16_m,
9466 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
9467 +
9468 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
9469 + GPIO_dmadonen1_m = GPIO_pin17_m,
9470 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
9471 +
9472 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
9473 + GPIO_dmafinn0_m = GPIO_pin18_m,
9474 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
9475 +
9476 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
9477 + GPIO_dmafinn1_m = GPIO_pin19_m,
9478 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
9479 +
9480 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
9481 + GPIO_maddr22_m = GPIO_pin20_m,
9482 + GPIO_maddr22_cfg_v = GPIO_output_v,
9483 +
9484 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
9485 + GPIO_maddr23_m = GPIO_pin21_m,
9486 + GPIO_maddr23_cfg_v = GPIO_output_v,
9487 +
9488 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
9489 + GPIO_maddr24_m = GPIO_pin22_m,
9490 + GPIO_maddr24_cfg_v = GPIO_output_v,
9491 +
9492 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
9493 + GPIO_maddr25_m = GPIO_pin23_m,
9494 + GPIO_maddr25_cfg_v = GPIO_output_v,
9495 +
9496 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
9497 + GPIO_afspare6_m = GPIO_pin24_m,
9498 + GPIO_afspare6_cfg_v = GPIO_input_v,
9499 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
9500 + GPIO_afspare5_m = GPIO_pin25_m,
9501 + GPIO_afspare5_cfg_v = GPIO_input_v,
9502 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
9503 + GPIO_afspare4_m = GPIO_pin26_m,
9504 + GPIO_afspare4_cfg_v = GPIO_input_v,
9505 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
9506 + GPIO_afspare3_m = GPIO_pin27_m,
9507 + GPIO_afspare3_cfg_v = GPIO_input_v,
9508 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
9509 + GPIO_afspare2_m = GPIO_pin28_m,
9510 + GPIO_afspare2_cfg_v = GPIO_input_v,
9511 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
9512 + GPIO_afspare1_m = GPIO_pin29_m,
9513 + GPIO_afspare1_cfg_v = GPIO_input_v,
9514 +
9515 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
9516 + GPIO_pcimuintn_m = GPIO_pin30_m,
9517 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
9518 +
9519 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
9520 + GPIO_rngclk_m = GPIO_pin31_m,
9521 + GPIO_rncclk_cfg_v = GPIO_input_v,
9522 +} GPIO_DEFS_t;
9523 +
9524 +#endif //__IDT_RC32438_GPIO_H__
9525 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9526 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
9527 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-03-20 14:25:10.000000000 +0100
9528 @@ -0,0 +1,152 @@
9529 +/**************************************************************************
9530 + *
9531 + * BRIEF MODULE DESCRIPTION
9532 + * Definitions for IDT RC32438 CPU.
9533 + *
9534 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9535 + *
9536 + * This program is free software; you can redistribute it and/or modify it
9537 + * under the terms of the GNU General Public License as published by the
9538 + * Free Software Foundation; either version 2 of the License, or (at your
9539 + * option) any later version.
9540 + *
9541 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9542 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9543 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9544 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9545 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9546 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9547 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9548 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9549 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9550 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9551 + *
9552 + * You should have received a copy of the GNU General Public License along
9553 + * with this program; if not, write to the Free Software Foundation, Inc.,
9554 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9555 + *
9556 + *
9557 + **************************************************************************
9558 + * May 2004 P. Sadik.
9559 + *
9560 + * Initial Release
9561 + *
9562 + *
9563 + *
9564 + **************************************************************************
9565 + */
9566 +
9567 +#ifndef __IDT_RC32438_H__
9568 +#define __IDT_RC32438_H__
9569 +#include <linux/config.h>
9570 +#include <linux/delay.h>
9571 +#include <asm/io.h>
9572 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9573 +
9574 +#define RC32438_REG_BASE 0x18000000
9575 +
9576 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9577 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
9578 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
9579 +
9580 +#define IDT_CLOCK_MULT 2
9581 +#define MIPS_CPU_TIMER_IRQ 7
9582 +/* Interrupt Controller */
9583 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
9584 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
9585 +#define IC_GROUP_OFFSET 0x0C
9586 +#define RTC_BASE 0xAC0801FF0
9587 +
9588 +#define NUM_INTR_GROUPS 5
9589 +/* 16550 UARTs */
9590 +
9591 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
9592 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9593 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9594 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9595 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9596 +
9597 +#ifdef __MIPSEB__
9598 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9599 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9600 +#else
9601 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9602 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9603 +#endif
9604 +
9605 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
9606 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
9607 +
9608 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
9609 +
9610 +
9611 +
9612 +/* cpu pipeline flush */
9613 +static inline void rc32438_sync(void)
9614 +{
9615 + __asm__ volatile ("sync");
9616 +}
9617 +
9618 +static inline void rc32438_sync_udelay(int us)
9619 +{
9620 + __asm__ volatile ("sync");
9621 + udelay(us);
9622 +}
9623 +
9624 +static inline void rc32438_sync_delay(int ms)
9625 +{
9626 + __asm__ volatile ("sync");
9627 + mdelay(ms);
9628 +}
9629 +
9630 +/*
9631 + * Macros to access internal RC32438 registers. No byte
9632 + * swapping should be done when accessing the internal
9633 + * registers.
9634 + */
9635 +
9636 +#define rc32438_readb __raw_readb
9637 +#define rc32438_readw __raw_readw
9638 +#define rc32438_readl __raw_readl
9639 +
9640 +#define rc32438_writeb __raw_writeb
9641 +#define rc32438_writew __raw_writew
9642 +#define rc32438_writel __raw_writel
9643 +
9644 +/*
9645 + * C access to CLZ and CLO instructions
9646 + * (count leading zeroes/ones).
9647 + */
9648 +static inline int rc32438_clz(unsigned long val)
9649 +{
9650 + int ret;
9651 + __asm__ volatile (
9652 + ".set\tnoreorder\n\t"
9653 + ".set\tnoat\n\t"
9654 + ".set\tmips32\n\t"
9655 + "clz\t%0,%1\n\t"
9656 + ".set\tmips0\n\t"
9657 + ".set\tat\n\t"
9658 + ".set\treorder"
9659 + : "=r" (ret)
9660 + : "r" (val));
9661 +
9662 + return ret;
9663 +}
9664 +static inline int rc32438_clo(unsigned long val)
9665 +{
9666 + int ret;
9667 + __asm__ volatile (
9668 + ".set\tnoreorder\n\t"
9669 + ".set\tnoat\n\t"
9670 + ".set\tmips32\n\t"
9671 + "clo\t%0,%1\n\t"
9672 + ".set\tmips0\n\t"
9673 + ".set\tat\n\t"
9674 + ".set\treorder"
9675 + : "=r" (ret)
9676 + : "r" (val));
9677 +
9678 + return ret;
9679 +}
9680 +#endif //__IDT_RC32438_H__
9681 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9682 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
9683 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-03-20 14:25:10.000000000 +0100
9684 @@ -0,0 +1,510 @@
9685 +/**************************************************************************
9686 + *
9687 + * BRIEF MODULE DESCRIPTION
9688 + * Definitions for IDT RC32438 PCI.
9689 + *
9690 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9691 + *
9692 + * This program is free software; you can redistribute it and/or modify it
9693 + * under the terms of the GNU General Public License as published by the
9694 + * Free Software Foundation; either version 2 of the License, or (at your
9695 + * option) any later version.
9696 + *
9697 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9698 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9699 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9700 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9701 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9702 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9703 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9704 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9705 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9706 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9707 + *
9708 + * You should have received a copy of the GNU General Public License along
9709 + * with this program; if not, write to the Free Software Foundation, Inc.,
9710 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9711 + *
9712 + *
9713 + **************************************************************************
9714 + * May 2004 P. Sadik
9715 + *
9716 + * Initial Release
9717 + *
9718 + *
9719 + *
9720 + **************************************************************************
9721 + */
9722 +
9723 +enum
9724 +{
9725 + PCI0_PhysicalAddress = 0x18080000,
9726 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
9727 +
9728 + PCI0_VirtualAddress = 0xb8080000,
9729 + PCI_VirtualAddress = PCI0_VirtualAddress,
9730 +} ;
9731 +
9732 +enum
9733 +{
9734 + PCI_LbaCount = 4, // Local base addresses.
9735 +} ;
9736 +
9737 +typedef struct
9738 +{
9739 + u32 a ; // Address.
9740 + u32 c ; // Control.
9741 + u32 m ; // mapping.
9742 +} PCI_Map_s ;
9743 +
9744 +typedef struct
9745 +{
9746 + u32 pcic ;
9747 + u32 pcis ;
9748 + u32 pcism ;
9749 + u32 pcicfga ;
9750 + u32 pcicfgd ;
9751 + PCI_Map_s pcilba [PCI_LbaCount] ;
9752 + u32 pcidac ;
9753 + u32 pcidas ;
9754 + u32 pcidasm ;
9755 + u32 pcidad ;
9756 + u32 pcidma8c ;
9757 + u32 pcidma9c ;
9758 + u32 pcitc ;
9759 +} volatile *PCI_t ;
9760 +
9761 +// PCI messaging unit.
9762 +enum
9763 +{
9764 + PCIM_Count = 2,
9765 +} ;
9766 +typedef struct
9767 +{
9768 + u32 pciim [PCIM_Count] ;
9769 + u32 pciom [PCIM_Count] ;
9770 + u32 pciid ;
9771 + u32 pciiic ;
9772 + u32 pciiim ;
9773 + u32 pciiod ;
9774 + u32 pciioic ;
9775 + u32 pciioim ;
9776 +} volatile *PCIM_t ;
9777 +
9778 +/*******************************************************************************
9779 + *
9780 + * PCI Control Register
9781 + *
9782 + ******************************************************************************/
9783 +enum
9784 +{
9785 + PCIC_en_b = 0,
9786 + PCIC_en_m = 0x00000001,
9787 + PCIC_tnr_b = 1,
9788 + PCIC_tnr_m = 0x00000002,
9789 + PCIC_sce_b = 2,
9790 + PCIC_sce_m = 0x00000004,
9791 + PCIC_ien_b = 3,
9792 + PCIC_ien_m = 0x00000008,
9793 + PCIC_aaa_b = 4,
9794 + PCIC_aaa_m = 0x00000010,
9795 + PCIC_eap_b = 5,
9796 + PCIC_eap_m = 0x00000020,
9797 + PCIC_pcim_b = 6,
9798 + PCIC_pcim_m = 0x000001c0,
9799 + PCIC_pcim_disabled_v = 0,
9800 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
9801 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
9802 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
9803 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
9804 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
9805 + PCIC_pcim_reserved6_v = 6,
9806 + PCIC_pcim_reserved7_v = 7,
9807 + PCIC_igm_b = 9,
9808 + PCIC_igm_m = 0x00000200,
9809 +} ;
9810 +
9811 +/*******************************************************************************
9812 + *
9813 + * PCI Status Register
9814 + *
9815 + ******************************************************************************/
9816 +enum {
9817 + PCIS_eed_b = 0,
9818 + PCIS_eed_m = 0x00000001,
9819 + PCIS_wr_b = 1,
9820 + PCIS_wr_m = 0x00000002,
9821 + PCIS_nmi_b = 2,
9822 + PCIS_nmi_m = 0x00000004,
9823 + PCIS_ii_b = 3,
9824 + PCIS_ii_m = 0x00000008,
9825 + PCIS_cwe_b = 4,
9826 + PCIS_cwe_m = 0x00000010,
9827 + PCIS_cre_b = 5,
9828 + PCIS_cre_m = 0x00000020,
9829 + PCIS_mdpe_b = 6,
9830 + PCIS_mdpe_m = 0x00000040,
9831 + PCIS_sta_b = 7,
9832 + PCIS_sta_m = 0x00000080,
9833 + PCIS_rta_b = 8,
9834 + PCIS_rta_m = 0x00000100,
9835 + PCIS_rma_b = 9,
9836 + PCIS_rma_m = 0x00000200,
9837 + PCIS_sse_b = 10,
9838 + PCIS_sse_m = 0x00000400,
9839 + PCIS_ose_b = 11,
9840 + PCIS_ose_m = 0x00000800,
9841 + PCIS_pe_b = 12,
9842 + PCIS_pe_m = 0x00001000,
9843 + PCIS_tae_b = 13,
9844 + PCIS_tae_m = 0x00002000,
9845 + PCIS_rle_b = 14,
9846 + PCIS_rle_m = 0x00004000,
9847 + PCIS_bme_b = 15,
9848 + PCIS_bme_m = 0x00008000,
9849 + PCIS_prd_b = 16,
9850 + PCIS_prd_m = 0x00010000,
9851 + PCIS_rip_b = 17,
9852 + PCIS_rip_m = 0x00020000,
9853 +} ;
9854 +
9855 +/*******************************************************************************
9856 + *
9857 + * PCI Status Mask Register
9858 + *
9859 + ******************************************************************************/
9860 +enum {
9861 + PCISM_eed_b = 0,
9862 + PCISM_eed_m = 0x00000001,
9863 + PCISM_wr_b = 1,
9864 + PCISM_wr_m = 0x00000002,
9865 + PCISM_nmi_b = 2,
9866 + PCISM_nmi_m = 0x00000004,
9867 + PCISM_ii_b = 3,
9868 + PCISM_ii_m = 0x00000008,
9869 + PCISM_cwe_b = 4,
9870 + PCISM_cwe_m = 0x00000010,
9871 + PCISM_cre_b = 5,
9872 + PCISM_cre_m = 0x00000020,
9873 + PCISM_mdpe_b = 6,
9874 + PCISM_mdpe_m = 0x00000040,
9875 + PCISM_sta_b = 7,
9876 + PCISM_sta_m = 0x00000080,
9877 + PCISM_rta_b = 8,
9878 + PCISM_rta_m = 0x00000100,
9879 + PCISM_rma_b = 9,
9880 + PCISM_rma_m = 0x00000200,
9881 + PCISM_sse_b = 10,
9882 + PCISM_sse_m = 0x00000400,
9883 + PCISM_ose_b = 11,
9884 + PCISM_ose_m = 0x00000800,
9885 + PCISM_pe_b = 12,
9886 + PCISM_pe_m = 0x00001000,
9887 + PCISM_tae_b = 13,
9888 + PCISM_tae_m = 0x00002000,
9889 + PCISM_rle_b = 14,
9890 + PCISM_rle_m = 0x00004000,
9891 + PCISM_bme_b = 15,
9892 + PCISM_bme_m = 0x00008000,
9893 + PCISM_prd_b = 16,
9894 + PCISM_prd_m = 0x00010000,
9895 + PCISM_rip_b = 17,
9896 + PCISM_rip_m = 0x00020000,
9897 +} ;
9898 +
9899 +/*******************************************************************************
9900 + *
9901 + * PCI Configuration Address Register
9902 + *
9903 + ******************************************************************************/
9904 +enum {
9905 + PCICFGA_reg_b = 2,
9906 + PCICFGA_reg_m = 0x000000fc,
9907 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
9908 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
9909 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
9910 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
9911 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
9912 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
9913 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
9914 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
9915 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9916 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
9917 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
9918 + PCICFGA_reg_pba0m_v = 0x48>>2,
9919 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
9920 + PCICFGA_reg_pba1m_v = 0x50>>2,
9921 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
9922 + PCICFGA_reg_pba2m_v = 0x58>>2,
9923 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
9924 + PCICFGA_reg_pba3m_v = 0x60>>2,
9925 + PCICFGA_reg_pmgt_v = 0x64>>2,
9926 + PCICFGA_func_b = 8,
9927 + PCICFGA_func_m = 0x00000700,
9928 + PCICFGA_dev_b = 11,
9929 + PCICFGA_dev_m = 0x0000f800,
9930 + PCICFGA_dev_internal_v = 0,
9931 + PCICFGA_bus_b = 16,
9932 + PCICFGA_bus_m = 0x00ff0000,
9933 + PCICFGA_bus_type0_v = 0, //local bus
9934 + PCICFGA_en_b = 31, // read only
9935 + PCICFGA_en_m = 0x80000000,
9936 +} ;
9937 +
9938 +enum {
9939 + PCFGID_vendor_b = 0,
9940 + PCFGID_vendor_m = 0x0000ffff,
9941 + PCFGID_vendor_IDT_v = 0x111d,
9942 + PCFGID_device_b = 16,
9943 + PCFGID_device_m = 0xffff0000,
9944 + PCFGID_device_Acaciade_v = 0x0207,
9945 +
9946 + PCFG04_command_ioena_b = 1,
9947 + PCFG04_command_ioena_m = 0x00000001,
9948 + PCFG04_command_memena_b = 2,
9949 + PCFG04_command_memena_m = 0x00000002,
9950 + PCFG04_command_bmena_b = 3,
9951 + PCFG04_command_bmena_m = 0x00000004,
9952 + PCFG04_command_mwinv_b = 5,
9953 + PCFG04_command_mwinv_m = 0x00000010,
9954 + PCFG04_command_parena_b = 7,
9955 + PCFG04_command_parena_m = 0x00000040,
9956 + PCFG04_command_serrena_b = 9,
9957 + PCFG04_command_serrena_m = 0x00000100,
9958 + PCFG04_command_fastbbena_b = 10,
9959 + PCFG04_command_fastbbena_m = 0x00000200,
9960 + PCFG04_status_b = 16,
9961 + PCFG04_status_m = 0xffff0000,
9962 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
9963 + PCFG04_status_66MHz_m = 0x00200000,
9964 + PCFG04_status_fbb_b = 23,
9965 + PCFG04_status_fbb_m = 0x00800000,
9966 + PCFG04_status_mdpe_b = 24,
9967 + PCFG04_status_mdpe_m = 0x01000000,
9968 + PCFG04_status_dst_b = 25,
9969 + PCFG04_status_dst_m = 0x06000000,
9970 + PCFG04_status_sta_b = 27,
9971 + PCFG04_status_sta_m = 0x08000000,
9972 + PCFG04_status_rta_b = 28,
9973 + PCFG04_status_rta_m = 0x10000000,
9974 + PCFG04_status_rma_b = 29,
9975 + PCFG04_status_rma_m = 0x20000000,
9976 + PCFG04_status_sse_b = 30,
9977 + PCFG04_status_sse_m = 0x40000000,
9978 + PCFG04_status_pe_b = 31,
9979 + PCFG04_status_pe_m = 0x40000000,
9980 +
9981 + PCFG08_revId_b = 0,
9982 + PCFG08_revId_m = 0x000000ff,
9983 + PCFG08_classCode_b = 0,
9984 + PCFG08_classCode_m = 0xffffff00,
9985 + PCFG08_classCode_bridge_v = 06,
9986 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
9987 + PCFG0C_cacheline_b = 0,
9988 + PCFG0C_cacheline_m = 0x000000ff,
9989 + PCFG0C_masterLatency_b = 8,
9990 + PCFG0C_masterLatency_m = 0x0000ff00,
9991 + PCFG0C_headerType_b = 16,
9992 + PCFG0C_headerType_m = 0x00ff0000,
9993 + PCFG0C_bist_b = 24,
9994 + PCFG0C_bist_m = 0xff000000,
9995 +
9996 + PCIPBA_msi_b = 0,
9997 + PCIPBA_msi_m = 0x00000001,
9998 + PCIPBA_p_b = 3,
9999 + PCIPBA_p_m = 0x00000004,
10000 + PCIPBA_baddr_b = 8,
10001 + PCIPBA_baddr_m = 0xffffff00,
10002 +
10003 + PCFGSS_vendorId_b = 0,
10004 + PCFGSS_vendorId_m = 0x0000ffff,
10005 + PCFGSS_id_b = 16,
10006 + PCFGSS_id_m = 0xffff0000,
10007 +
10008 + PCFG3C_interruptLine_b = 0,
10009 + PCFG3C_interruptLine_m = 0x000000ff,
10010 + PCFG3C_interruptPin_b = 8,
10011 + PCFG3C_interruptPin_m = 0x0000ff00,
10012 + PCFG3C_minGrant_b = 16,
10013 + PCFG3C_minGrant_m = 0x00ff0000,
10014 + PCFG3C_maxLat_b = 24,
10015 + PCFG3C_maxLat_m = 0xff000000,
10016 +
10017 + PCIPBAC_msi_b = 0,
10018 + PCIPBAC_msi_m = 0x00000001,
10019 + PCIPBAC_p_b = 1,
10020 + PCIPBAC_p_m = 0x00000002,
10021 + PCIPBAC_size_b = 2,
10022 + PCIPBAC_size_m = 0x0000007c,
10023 + PCIPBAC_sb_b = 7,
10024 + PCIPBAC_sb_m = 0x00000080,
10025 + PCIPBAC_pp_b = 8,
10026 + PCIPBAC_pp_m = 0x00000100,
10027 + PCIPBAC_mr_b = 9,
10028 + PCIPBAC_mr_m = 0x00000600,
10029 + PCIPBAC_mr_read_v =0, //no prefetching
10030 + PCIPBAC_mr_readLine_v =1,
10031 + PCIPBAC_mr_readMult_v =2,
10032 + PCIPBAC_mrl_b = 11,
10033 + PCIPBAC_mrl_m = 0x00000800,
10034 + PCIPBAC_mrm_b = 12,
10035 + PCIPBAC_mrm_m = 0x00001000,
10036 + PCIPBAC_trp_b = 13,
10037 + PCIPBAC_trp_m = 0x00002000,
10038 +
10039 + PCFG40_trdyTimeout_b = 0,
10040 + PCFG40_trdyTimeout_m = 0x000000ff,
10041 + PCFG40_retryLim_b = 8,
10042 + PCFG40_retryLim_m = 0x0000ff00,
10043 +};
10044 +
10045 +/*******************************************************************************
10046 + *
10047 + * PCI Local Base Address [0|1|2|3] Register
10048 + *
10049 + ******************************************************************************/
10050 +enum {
10051 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
10052 + PCILBA_baddr_m = 0xffffff00,
10053 +} ;
10054 +/*******************************************************************************
10055 + *
10056 + * PCI Local Base Address Control Register
10057 + *
10058 + ******************************************************************************/
10059 +enum {
10060 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
10061 + PCILBAC_msi_m = 0x00000001,
10062 + PCILBAC_msi_mem_v = 0,
10063 + PCILBAC_msi_io_v = 1,
10064 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
10065 + PCILBAC_size_m = 0x0000007c,
10066 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
10067 + PCILBAC_sb_m = 0x00000080,
10068 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
10069 + PCILBAC_rt_m = 0x00000100,
10070 + PCILBAC_rt_noprefetch_v = 0, // mem read
10071 + PCILBAC_rt_prefetch_v = 1, // mem readline
10072 +} ;
10073 +
10074 +/*******************************************************************************
10075 + *
10076 + * PCI Local Base Address [0|1|2|3] Mapping Register
10077 + *
10078 + ******************************************************************************/
10079 +enum {
10080 + PCILBAM_maddr_b = 8,
10081 + PCILBAM_maddr_m = 0xffffff00,
10082 +} ;
10083 +
10084 +/*******************************************************************************
10085 + *
10086 + * PCI Decoupled Access Control Register
10087 + *
10088 + ******************************************************************************/
10089 +enum {
10090 + PCIDAC_den_b = 0,
10091 + PCIDAC_den_m = 0x00000001,
10092 +} ;
10093 +
10094 +/*******************************************************************************
10095 + *
10096 + * PCI Decoupled Access Status Register
10097 + *
10098 + ******************************************************************************/
10099 +enum {
10100 + PCIDAS_d_b = 0,
10101 + PCIDAS_d_m = 0x00000001,
10102 + PCIDAS_b_b = 1,
10103 + PCIDAS_b_m = 0x00000002,
10104 + PCIDAS_e_b = 2,
10105 + PCIDAS_e_m = 0x00000004,
10106 + PCIDAS_ofe_b = 3,
10107 + PCIDAS_ofe_m = 0x00000008,
10108 + PCIDAS_off_b = 4,
10109 + PCIDAS_off_m = 0x00000010,
10110 + PCIDAS_ife_b = 5,
10111 + PCIDAS_ife_m = 0x00000020,
10112 + PCIDAS_iff_b = 6,
10113 + PCIDAS_iff_m = 0x00000040,
10114 +} ;
10115 +
10116 +/*******************************************************************************
10117 + *
10118 + * PCI DMA Channel 8 Configuration Register
10119 + *
10120 + ******************************************************************************/
10121 +enum
10122 +{
10123 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
10124 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
10125 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
10126 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
10127 +} ;
10128 +
10129 +/*******************************************************************************
10130 + *
10131 + * PCI DMA Channel 9 Configuration Register
10132 + *
10133 + ******************************************************************************/
10134 +enum
10135 +{
10136 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
10137 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
10138 +} ;
10139 +
10140 +/*******************************************************************************
10141 + *
10142 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10143 + *
10144 + ******************************************************************************/
10145 +enum {
10146 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
10147 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
10148 + // These are for reads (DMA channel 8)
10149 + PCIDMAD_devcmd_mr_v = 0, //memory read
10150 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
10151 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
10152 + PCIDMAD_devcmd_ior_v = 3, //I/O read
10153 + // These are for writes (DMA channel 9)
10154 + PCIDMAD_devcmd_mw_v = 0, //memory write
10155 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
10156 + PCIDMAD_devcmd_iow_v = 3, //I/O write
10157 +
10158 + // Swap byte field applies to both DMA channel 8 and 9
10159 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
10160 + PCIDMAD_sb_m = 0x01000000, // swap byte field
10161 +} ;
10162 +
10163 +
10164 +/*******************************************************************************
10165 + *
10166 + * PCI Target Control Register
10167 + *
10168 + ******************************************************************************/
10169 +enum
10170 +{
10171 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
10172 + PCITC_rtimer_m = 0x000000ff,
10173 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
10174 + PCITC_dtimer_m = 0x0000ff00,
10175 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
10176 + PCITC_rdr_m = 0x00040000,
10177 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
10178 + PCITC_ddt_m = 0x00080000,
10179 +} ;
10180 +/*******************************************************************************
10181 + *
10182 + * PCI messaging unit [applies to both inbound and outbound registers ]
10183 + *
10184 + ******************************************************************************/
10185 +enum
10186 +{
10187 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10188 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
10189 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10190 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
10191 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10192 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
10193 +};
10194 +
10195 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10196 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
10197 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-03-20 14:25:10.000000000 +0100
10198 @@ -0,0 +1,190 @@
10199 +/**************************************************************************
10200 + *
10201 + * BRIEF MODULE DESCRIPTION
10202 + * Definitions for IDT RC32438 PCI setup.
10203 + *
10204 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10205 + *
10206 + * This program is free software; you can redistribute it and/or modify it
10207 + * under the terms of the GNU General Public License as published by the
10208 + * Free Software Foundation; either version 2 of the License, or (at your
10209 + * option) any later version.
10210 + *
10211 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10212 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10213 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10214 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10215 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10216 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10217 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10218 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10219 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10220 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10221 + *
10222 + * You should have received a copy of the GNU General Public License along
10223 + * with this program; if not, write to the Free Software Foundation, Inc.,
10224 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10225 + *
10226 + *
10227 + **************************************************************************
10228 + * May 2004 P. Sadik
10229 + *
10230 + * Initial Release
10231 + *
10232 + *
10233 + *
10234 + **************************************************************************
10235 + */
10236 +
10237 +#define PCI_MSG_VirtualAddress 0xB8088010
10238 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10239 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10240 +
10241 +#define PCIM_SHFT 0x6
10242 +#define PCIM_BIT_LEN 0x7
10243 +#define PCIM_H_EA 0x3
10244 +#define PCIM_H_IA_FIX 0x4
10245 +#define PCIM_H_IA_RR 0x5
10246 +
10247 +#define PCI_ADDR_START 0x50000000
10248 +
10249 +#define CPUTOPCI_MEM_WIN 0x02000000
10250 +#define CPUTOPCI_IO_WIN 0x00100000
10251 +#define PCILBA_SIZE_SHFT 2
10252 +#define PCILBA_SIZE_MASK 0x1F
10253 +#define SIZE_256MB 0x1C
10254 +#define SIZE_128MB 0x1B
10255 +#define SIZE_64MB 0x1A
10256 +#define SIZE_32MB 0x19
10257 +#define SIZE_16MB 0x18
10258 +#define SIZE_4MB 0x16
10259 +#define SIZE_2MB 0x15
10260 +#define SIZE_1MB 0x14
10261 +#define ACACIA_CONFIG0_ADDR 0x80000000
10262 +#define ACACIA_CONFIG1_ADDR 0x80000004
10263 +#define ACACIA_CONFIG2_ADDR 0x80000008
10264 +#define ACACIA_CONFIG3_ADDR 0x8000000C
10265 +#define ACACIA_CONFIG4_ADDR 0x80000010
10266 +#define ACACIA_CONFIG5_ADDR 0x80000014
10267 +#define ACACIA_CONFIG6_ADDR 0x80000018
10268 +#define ACACIA_CONFIG7_ADDR 0x8000001C
10269 +#define ACACIA_CONFIG8_ADDR 0x80000020
10270 +#define ACACIA_CONFIG9_ADDR 0x80000024
10271 +#define ACACIA_CONFIG10_ADDR 0x80000028
10272 +#define ACACIA_CONFIG11_ADDR 0x8000002C
10273 +#define ACACIA_CONFIG12_ADDR 0x80000030
10274 +#define ACACIA_CONFIG13_ADDR 0x80000034
10275 +#define ACACIA_CONFIG14_ADDR 0x80000038
10276 +#define ACACIA_CONFIG15_ADDR 0x8000003C
10277 +#define ACACIA_CONFIG16_ADDR 0x80000040
10278 +#define ACACIA_CONFIG17_ADDR 0x80000044
10279 +#define ACACIA_CONFIG18_ADDR 0x80000048
10280 +#define ACACIA_CONFIG19_ADDR 0x8000004C
10281 +#define ACACIA_CONFIG20_ADDR 0x80000050
10282 +#define ACACIA_CONFIG21_ADDR 0x80000054
10283 +#define ACACIA_CONFIG22_ADDR 0x80000058
10284 +#define ACACIA_CONFIG23_ADDR 0x8000005C
10285 +#define ACACIA_CONFIG24_ADDR 0x80000060
10286 +#define ACACIA_CONFIG25_ADDR 0x80000064
10287 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
10288 + PCFG04_command_memena_m | \
10289 + PCFG04_command_bmena_m | \
10290 + PCFG04_command_mwinv_m | \
10291 + PCFG04_command_parena_m | \
10292 + PCFG04_command_serrena_m )
10293 +
10294 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
10295 + PCFG04_status_sta_m | \
10296 + PCFG04_status_rta_m | \
10297 + PCFG04_status_rma_m | \
10298 + PCFG04_status_sse_m | \
10299 + PCFG04_status_pe_m)
10300 +
10301 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
10302 +
10303 +#define ACACIA_REVID 0
10304 +#define ACACIA_CLASS_CODE 0
10305 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
10306 + ACACIA_REVID)
10307 +
10308 +#define ACACIA_CACHE_LINE_SIZE 4
10309 +#define ACACIA_MASTER_LAT 0x3c
10310 +#define ACACIA_HEADER_TYPE 0
10311 +#define ACACIA_BIST 0
10312 +
10313 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10314 + (ACACIA_HEADER_TYPE<<16) | \
10315 + (ACACIA_MASTER_LAT<<8) | \
10316 + ACACIA_CACHE_LINE_SIZE )
10317 +
10318 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
10319 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
10320 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
10321 + internal Registers */
10322 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
10323 +
10324 +#define ACACIA_CNFG4 ACACIA_BAR0
10325 +#define ACACIA_CNFG5 ACACIA_BAR1
10326 +#define ACACIA_CNFG6 ACACIA_BAR2
10327 +#define ACACIA_CNFG7 ACACIA_BAR3
10328 +
10329 +#define ACACIA_SUBSYS_VENDOR_ID 0
10330 +#define ACACIA_SUBSYSTEM_ID 0
10331 +#define ACACIA_CNFG8 0
10332 +#define ACACIA_CNFG9 0
10333 +#define ACACIA_CNFG10 0
10334 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10335 + ACACIA_SUBSYSTEM_ID)
10336 +#define ACACIA_INT_LINE 1
10337 +#define ACACIA_INT_PIN 1
10338 +#define ACACIA_MIN_GNT 8
10339 +#define ACACIA_MAX_LAT 0x38
10340 +#define ACACIA_CNFG12 0
10341 +#define ACACIA_CNFG13 0
10342 +#define ACACIA_CNFG14 0
10343 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
10344 + (ACACIA_MIN_GNT<<16) | \
10345 + (ACACIA_INT_PIN<<8) | \
10346 + ACACIA_INT_LINE)
10347 +#define ACACIA_RETRY_LIMIT 0x80
10348 +#define ACACIA_TRDY_LIMIT 0x80
10349 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10350 + ACACIA_TRDY_LIMIT)
10351 +#define PCI_PBAxC_R 0x0
10352 +#define PCI_PBAxC_RL 0x1
10353 +#define PCI_PBAxC_RM 0x2
10354 +#define SIZE_SHFT 2
10355 +
10356 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10357 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10358 + PCIPBAC_pp_m | \
10359 + (SIZE_128MB<<SIZE_SHFT) | \
10360 + PCIPBAC_p_m)
10361 +
10362 +#define ACACIA_CNFG17 ACACIA_PBA0C
10363 +#define ACACIA_PBA0M 0x0
10364 +#define ACACIA_CNFG18 ACACIA_PBA0M
10365 +
10366 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10367 + PCIPBAC_msi_m)
10368 +
10369 +#define ACACIA_CNFG19 ACACIA_PBA1C
10370 +#define ACACIA_PBA1M 0x0
10371 +#define ACACIA_CNFG20 ACACIA_PBA1M
10372 +
10373 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10374 + PCIPBAC_msi_m)
10375 +
10376 +#define ACACIA_CNFG21 ACACIA_PBA2C
10377 +#define ACACIA_PBA2M 0x18000000
10378 +#define ACACIA_CNFG22 ACACIA_PBA2M
10379 +#define ACACIA_PBA3C 0
10380 +#define ACACIA_CNFG23 ACACIA_PBA3C
10381 +#define ACACIA_PBA3M 0
10382 +#define ACACIA_CNFG24 ACACIA_PBA3M
10383 +
10384 +
10385 +
10386 +#define PCITC_DTIMER_VAL 8
10387 +#define PCITC_RTIMER_VAL 0x10
10388 +
10389 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10390 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
10391 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-03-20 14:25:10.000000000 +0100
10392 @@ -0,0 +1,91 @@
10393 +/**************************************************************************
10394 + *
10395 + * BRIEF MODULE DESCRIPTION
10396 + * Timer register definition IDT RC32438 CPU.
10397 + *
10398 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10399 + *
10400 + * This program is free software; you can redistribute it and/or modify it
10401 + * under the terms of the GNU General Public License as published by the
10402 + * Free Software Foundation; either version 2 of the License, or (at your
10403 + * option) any later version.
10404 + *
10405 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10406 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10407 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10408 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10409 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10410 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10411 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10412 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10413 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10414 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10415 + *
10416 + * You should have received a copy of the GNU General Public License along
10417 + * with this program; if not, write to the Free Software Foundation, Inc.,
10418 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10419 + *
10420 + *
10421 + **************************************************************************
10422 + * May 2004 P. Sadik.
10423 + *
10424 + * Initial Release
10425 + *
10426 + *
10427 + *
10428 + **************************************************************************
10429 + */
10430 +
10431 +#ifndef __IDT_RC32438_TIM_H__
10432 +#define __IDT_RC32438_TIM_H__
10433 +
10434 +enum
10435 +{
10436 + TIM0_PhysicalAddress = 0x18028000,
10437 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
10438 +
10439 + TIM0_VirtualAddress = 0xb8028000,
10440 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
10441 +} ;
10442 +
10443 +enum
10444 +{
10445 + TIM_Count = 3,
10446 +} ;
10447 +
10448 +struct TIM_CNTR_s
10449 +{
10450 + u32 count ;
10451 + u32 compare ;
10452 + u32 ctc ; //use CTC_
10453 +} ;
10454 +
10455 +typedef struct TIM_s
10456 +{
10457 + struct TIM_CNTR_s tim [TIM_Count] ;
10458 + u32 rcount ; //use RCOUNT_
10459 + u32 rcompare ; //use RCOMPARE_
10460 + u32 rtc ; //use RTC_
10461 +} volatile * TIM_t ;
10462 +
10463 +enum
10464 +{
10465 + CTC_en_b = 0,
10466 + CTC_en_m = 0x00000001,
10467 + CTC_to_b = 1,
10468 + CTC_to_m = 0x00000002,
10469 +
10470 + RCOUNT_count_b = 0,
10471 + RCOUNT_count_m = 0x0000ffff,
10472 + RCOMPARE_compare_b = 0,
10473 + RCOMPARE_compare_m = 0x0000ffff,
10474 + RTC_ce_b = 0,
10475 + RTC_ce_m = 0x00000001,
10476 + RTC_to_b = 1,
10477 + RTC_to_m = 0x00000002,
10478 + RTC_rqe_b = 2,
10479 + RTC_rqe_m = 0x00000004,
10480 +
10481 +} ;
10482 +#endif //__IDT_RC32438_TIM_H__
10483 +
10484 diff -Nur linux-2.6.16/include/asm-mips/mach-generic/irq.h linux-2.6.16-owrt/include/asm-mips/mach-generic/irq.h
10485 --- linux-2.6.16/include/asm-mips/mach-generic/irq.h 2006-03-20 06:53:29.000000000 +0100
10486 +++ linux-2.6.16-owrt/include/asm-mips/mach-generic/irq.h 2006-03-20 14:25:10.000000000 +0100
10487 @@ -8,6 +8,6 @@
10488 #ifndef __ASM_MACH_GENERIC_IRQ_H
10489 #define __ASM_MACH_GENERIC_IRQ_H
10490
10491 -#define NR_IRQS 128
10492 +#define NR_IRQS 256
10493
10494 #endif /* __ASM_MACH_GENERIC_IRQ_H */
10495 diff -Nur linux-2.6.16/include/linux/kernel.h linux-2.6.16-owrt/include/linux/kernel.h
10496 --- linux-2.6.16/include/linux/kernel.h 2006-03-20 06:53:29.000000000 +0100
10497 +++ linux-2.6.16-owrt/include/linux/kernel.h 2006-03-20 14:25:10.000000000 +0100
10498 @@ -324,6 +324,7 @@
10499 };
10500
10501 /* Force a compilation error if condition is true */
10502 +extern void BUILD_BUG(void);
10503 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10504
10505 /* Trap pasters of __FUNCTION__ at compile-time */
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