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Merge bcm43xx-mac80211 driver from tree at bu3sch.de, pulled 24/6
[openwrt/openwrt.git] / package / bcm43xx-mac80211 / src / bcm43xx / bcm43xx_main.c
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42
43 #include "bcm43xx.h"
44 #include "bcm43xx_main.h"
45 #include "bcm43xx_debugfs.h"
46 #include "bcm43xx_phy.h"
47 #include "bcm43xx_dma.h"
48 #include "bcm43xx_pio.h"
49 #include "bcm43xx_power.h"
50 #include "bcm43xx_sysfs.h"
51 #include "bcm43xx_xmit.h"
52 #include "bcm43xx_sysfs.h"
53 #include "bcm43xx_lo.h"
54 #include "bcm43xx_pcmcia.h"
55
56
57 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63
64 extern char *nvram_get(char *name);
65
66
67 #if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
68 static int modparam_pio;
69 module_param_named(pio, modparam_pio, int, 0444);
70 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
71 #elif defined(CONFIG_BCM43XX_MAC80211_DMA)
72 # define modparam_pio 0
73 #elif defined(CONFIG_BCM43XX_MAC80211_PIO)
74 # define modparam_pio 1
75 #endif
76
77 static int modparam_bad_frames_preempt;
78 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
80
81 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
82 module_param_named(short_retry, modparam_short_retry, int, 0444);
83 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
84
85 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
86 module_param_named(long_retry, modparam_long_retry, int, 0444);
87 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
88
89 static int modparam_noleds;
90 module_param_named(noleds, modparam_noleds, int, 0444);
91 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
92
93 static char modparam_fwpostfix[16];
94 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
95 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
96
97 static int modparam_mon_keep_bad;
98 module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444);
99 MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode");
100
101 static int modparam_mon_keep_badplcp;
102 module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444);
103 MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode");
104
105
106 static const struct ssb_device_id bcm43xx_ssb_tbl[] = {
107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),
108 SSB_DEVTABLE_END
109 };
110 MODULE_DEVICE_TABLE(ssb, bcm43xx_ssb_tbl);
111
112
113 /* Channel and ratetables are shared for all devices.
114 * They can't be const, because ieee80211 puts some precalculated
115 * data in there. This data is the same for all devices, so we don't
116 * get concurrency issues */
117 #define RATETAB_ENT(_rateid, _flags) \
118 { \
119 .rate = BCM43xx_RATE_TO_BASE100KBPS(_rateid), \
120 .val = (_rateid), \
121 .val2 = (_rateid), \
122 .flags = (_flags), \
123 }
124 static struct ieee80211_rate __bcm43xx_ratetable[] = {
125 RATETAB_ENT(BCM43xx_CCK_RATE_1MB, IEEE80211_RATE_CCK),
126 RATETAB_ENT(BCM43xx_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
127 RATETAB_ENT(BCM43xx_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
128 RATETAB_ENT(BCM43xx_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
129 RATETAB_ENT(BCM43xx_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
130 RATETAB_ENT(BCM43xx_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
131 RATETAB_ENT(BCM43xx_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
132 RATETAB_ENT(BCM43xx_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
133 RATETAB_ENT(BCM43xx_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
134 RATETAB_ENT(BCM43xx_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
135 RATETAB_ENT(BCM43xx_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
136 RATETAB_ENT(BCM43xx_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
137 };
138 #define bcm43xx_a_ratetable (__bcm43xx_ratetable + 4)
139 #define bcm43xx_a_ratetable_size 8
140 #define bcm43xx_b_ratetable (__bcm43xx_ratetable + 0)
141 #define bcm43xx_b_ratetable_size 4
142 #define bcm43xx_g_ratetable (__bcm43xx_ratetable + 0)
143 #define bcm43xx_g_ratetable_size 12
144
145 #define CHANTAB_ENT(_chanid, _freq) \
146 { \
147 .chan = (_chanid), \
148 .freq = (_freq), \
149 .val = (_chanid), \
150 .flag = IEEE80211_CHAN_W_SCAN | \
151 IEEE80211_CHAN_W_ACTIVE_SCAN | \
152 IEEE80211_CHAN_W_IBSS, \
153 .power_level = 0xFF, \
154 .antenna_max = 0xFF, \
155 }
156 static struct ieee80211_channel bcm43xx_bg_chantable[] = {
157 CHANTAB_ENT(1, 2412),
158 CHANTAB_ENT(2, 2417),
159 CHANTAB_ENT(3, 2422),
160 CHANTAB_ENT(4, 2427),
161 CHANTAB_ENT(5, 2432),
162 CHANTAB_ENT(6, 2437),
163 CHANTAB_ENT(7, 2442),
164 CHANTAB_ENT(8, 2447),
165 CHANTAB_ENT(9, 2452),
166 CHANTAB_ENT(10, 2457),
167 CHANTAB_ENT(11, 2462),
168 CHANTAB_ENT(12, 2467),
169 CHANTAB_ENT(13, 2472),
170 CHANTAB_ENT(14, 2484),
171 };
172 #define bcm43xx_bg_chantable_size ARRAY_SIZE(bcm43xx_bg_chantable)
173 static struct ieee80211_channel bcm43xx_a_chantable[] = {
174 CHANTAB_ENT(36, 5180),
175 CHANTAB_ENT(40, 5200),
176 CHANTAB_ENT(44, 5220),
177 CHANTAB_ENT(48, 5240),
178 CHANTAB_ENT(52, 5260),
179 CHANTAB_ENT(56, 5280),
180 CHANTAB_ENT(60, 5300),
181 CHANTAB_ENT(64, 5320),
182 CHANTAB_ENT(149, 5745),
183 CHANTAB_ENT(153, 5765),
184 CHANTAB_ENT(157, 5785),
185 CHANTAB_ENT(161, 5805),
186 CHANTAB_ENT(165, 5825),
187 };
188 #define bcm43xx_a_chantable_size ARRAY_SIZE(bcm43xx_a_chantable)
189
190
191 static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev);
192 static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev);
193 static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev);
194 static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev);
195
196
197 static void bcm43xx_ram_write(struct bcm43xx_wldev *dev, u16 offset, u32 val)
198 {
199 u32 status;
200
201 assert(offset % 4 == 0);
202
203 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
204 if (status & BCM43xx_SBF_XFER_REG_BYTESWAP)
205 val = swab32(val);
206
207 bcm43xx_write32(dev, BCM43xx_MMIO_RAM_CONTROL, offset);
208 mmiowb();
209 bcm43xx_write32(dev, BCM43xx_MMIO_RAM_DATA, val);
210 }
211
212 static inline
213 void bcm43xx_shm_control_word(struct bcm43xx_wldev *dev,
214 u16 routing, u16 offset)
215 {
216 u32 control;
217
218 /* "offset" is the WORD offset. */
219
220 control = routing;
221 control <<= 16;
222 control |= offset;
223 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_CONTROL, control);
224 }
225
226 u32 bcm43xx_shm_read32(struct bcm43xx_wldev *dev,
227 u16 routing, u16 offset)
228 {
229 u32 ret;
230
231 if (routing == BCM43xx_SHM_SHARED) {
232 assert((offset & 0x0001) == 0);
233 if (offset & 0x0003) {
234 /* Unaligned access */
235 bcm43xx_shm_control_word(dev, routing, offset >> 2);
236 ret = bcm43xx_read16(dev,
237 BCM43xx_MMIO_SHM_DATA_UNALIGNED);
238 ret <<= 16;
239 bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
240 ret |= bcm43xx_read16(dev,
241 BCM43xx_MMIO_SHM_DATA);
242
243 return ret;
244 }
245 offset >>= 2;
246 }
247 bcm43xx_shm_control_word(dev, routing, offset);
248 ret = bcm43xx_read32(dev, BCM43xx_MMIO_SHM_DATA);
249
250 return ret;
251 }
252
253 u16 bcm43xx_shm_read16(struct bcm43xx_wldev *dev,
254 u16 routing, u16 offset)
255 {
256 u16 ret;
257
258 if (routing == BCM43xx_SHM_SHARED) {
259 assert((offset & 0x0001) == 0);
260 if (offset & 0x0003) {
261 /* Unaligned access */
262 bcm43xx_shm_control_word(dev, routing, offset >> 2);
263 ret = bcm43xx_read16(dev,
264 BCM43xx_MMIO_SHM_DATA_UNALIGNED);
265
266 return ret;
267 }
268 offset >>= 2;
269 }
270 bcm43xx_shm_control_word(dev, routing, offset);
271 ret = bcm43xx_read16(dev, BCM43xx_MMIO_SHM_DATA);
272
273 return ret;
274 }
275
276 void bcm43xx_shm_write32(struct bcm43xx_wldev *dev,
277 u16 routing, u16 offset,
278 u32 value)
279 {
280 if (routing == BCM43xx_SHM_SHARED) {
281 assert((offset & 0x0001) == 0);
282 if (offset & 0x0003) {
283 /* Unaligned access */
284 bcm43xx_shm_control_word(dev, routing, offset >> 2);
285 mmiowb();
286 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
287 (value >> 16) & 0xffff);
288 mmiowb();
289 bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
290 mmiowb();
291 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA,
292 value & 0xffff);
293 return;
294 }
295 offset >>= 2;
296 }
297 bcm43xx_shm_control_word(dev, routing, offset);
298 mmiowb();
299 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, value);
300 }
301
302 void bcm43xx_shm_write16(struct bcm43xx_wldev *dev,
303 u16 routing, u16 offset,
304 u16 value)
305 {
306 if (routing == BCM43xx_SHM_SHARED) {
307 assert((offset & 0x0001) == 0);
308 if (offset & 0x0003) {
309 /* Unaligned access */
310 bcm43xx_shm_control_word(dev, routing, offset >> 2);
311 mmiowb();
312 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
313 value);
314 return;
315 }
316 offset >>= 2;
317 }
318 bcm43xx_shm_control_word(dev, routing, offset);
319 mmiowb();
320 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA, value);
321 }
322
323 /* Read HostFlags */
324 u32 bcm43xx_hf_read(struct bcm43xx_wldev *dev)
325 {
326 u32 ret;
327
328 ret = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
329 BCM43xx_SHM_SH_HOSTFHI);
330 ret <<= 16;
331 ret |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
332 BCM43xx_SHM_SH_HOSTFLO);
333
334 return ret;
335 }
336
337 /* Write HostFlags */
338 void bcm43xx_hf_write(struct bcm43xx_wldev *dev, u32 value)
339 {
340 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
341 BCM43xx_SHM_SH_HOSTFLO,
342 (value & 0x0000FFFF));
343 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
344 BCM43xx_SHM_SH_HOSTFHI,
345 ((value & 0xFFFF0000) >> 16));
346 }
347
348 void bcm43xx_tsf_read(struct bcm43xx_wldev *dev, u64 *tsf)
349 {
350 /* We need to be careful. As we read the TSF from multiple
351 * registers, we should take care of register overflows.
352 * In theory, the whole tsf read process should be atomic.
353 * We try to be atomic here, by restaring the read process,
354 * if any of the high registers changed (overflew).
355 */
356 if (dev->dev->id.revision >= 3) {
357 u32 low, high, high2;
358
359 do {
360 high = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
361 low = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
362 high2 = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
363 } while (unlikely(high != high2));
364
365 *tsf = high;
366 *tsf <<= 32;
367 *tsf |= low;
368 } else {
369 u64 tmp;
370 u16 v0, v1, v2, v3;
371 u16 test1, test2, test3;
372
373 do {
374 v3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
375 v2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
376 v1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
377 v0 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_0);
378
379 test3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
380 test2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
381 test1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
382 } while (v3 != test3 || v2 != test2 || v1 != test1);
383
384 *tsf = v3;
385 *tsf <<= 48;
386 tmp = v2;
387 tmp <<= 32;
388 *tsf |= tmp;
389 tmp = v1;
390 tmp <<= 16;
391 *tsf |= tmp;
392 *tsf |= v0;
393 }
394 }
395
396 static void bcm43xx_time_lock(struct bcm43xx_wldev *dev)
397 {
398 u32 status;
399
400 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
401 status |= BCM43xx_SBF_TIME_UPDATE;
402 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
403 mmiowb();
404 }
405
406 static void bcm43xx_time_unlock(struct bcm43xx_wldev *dev)
407 {
408 u32 status;
409
410 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
411 status &= ~BCM43xx_SBF_TIME_UPDATE;
412 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
413 }
414
415 static void bcm43xx_tsf_write_locked(struct bcm43xx_wldev *dev, u64 tsf)
416 {
417 /* Be careful with the in-progress timer.
418 * First zero out the low register, so we have a full
419 * register-overflow duration to complete the operation.
420 */
421 if (dev->dev->id.revision >= 3) {
422 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
423 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
424
425 bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
426 mmiowb();
427 bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
428 mmiowb();
429 bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
430 } else {
431 u16 v0 = (tsf & 0x000000000000FFFFULL);
432 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
433 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
434 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
435
436 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, 0);
437 mmiowb();
438 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_3, v3);
439 mmiowb();
440 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_2, v2);
441 mmiowb();
442 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_1, v1);
443 mmiowb();
444 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, v0);
445 }
446 }
447
448 void bcm43xx_tsf_write(struct bcm43xx_wldev *dev, u64 tsf)
449 {
450 bcm43xx_time_lock(dev);
451 bcm43xx_tsf_write_locked(dev, tsf);
452 bcm43xx_time_unlock(dev);
453 }
454
455 static
456 void bcm43xx_macfilter_set(struct bcm43xx_wldev *dev,
457 u16 offset,
458 const u8 *mac)
459 {
460 static const u8 zero_addr[ETH_ALEN] = { 0 };
461 u16 data;
462
463 if (!mac)
464 mac = zero_addr;
465
466 offset |= 0x0020;
467 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
468
469 data = mac[0];
470 data |= mac[1] << 8;
471 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
472 data = mac[2];
473 data |= mac[3] << 8;
474 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
475 data = mac[4];
476 data |= mac[5] << 8;
477 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
478 }
479
480 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_wldev *dev)
481 {
482 static const u8 zero_addr[ETH_ALEN] = { 0 };
483 const u8 *mac;
484 const u8 *bssid;
485 u8 mac_bssid[ETH_ALEN * 2];
486 int i;
487 u32 tmp;
488
489 bssid = dev->wl->bssid;
490 if (!bssid)
491 bssid = zero_addr;
492 mac = dev->wl->mac_addr;
493 if (!mac)
494 mac = zero_addr;
495
496 bcm43xx_macfilter_set(dev, BCM43xx_MACFILTER_BSSID, bssid);
497
498 memcpy(mac_bssid, mac, ETH_ALEN);
499 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
500
501 /* Write our MAC address and BSSID to template ram */
502 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
503 tmp = (u32)(mac_bssid[i + 0]);
504 tmp |= (u32)(mac_bssid[i + 1]) << 8;
505 tmp |= (u32)(mac_bssid[i + 2]) << 16;
506 tmp |= (u32)(mac_bssid[i + 3]) << 24;
507 bcm43xx_ram_write(dev, 0x20 + i, tmp);
508 }
509 }
510
511 static void bcm43xx_upload_card_macaddress(struct bcm43xx_wldev *dev,
512 const u8 *mac_addr)
513 {
514 dev->wl->mac_addr = mac_addr;
515 bcm43xx_write_mac_bssid_templates(dev);
516 bcm43xx_macfilter_set(dev, BCM43xx_MACFILTER_SELF, mac_addr);
517 }
518
519 static void bcm43xx_set_slot_time(struct bcm43xx_wldev *dev, u16 slot_time)
520 {
521 /* slot_time is in usec. */
522 if (dev->phy.type != BCM43xx_PHYTYPE_G)
523 return;
524 bcm43xx_write16(dev, 0x684, 510 + slot_time);
525 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0010, slot_time);
526 }
527
528 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_wldev *dev)
529 {
530 bcm43xx_set_slot_time(dev, 9);
531 dev->short_slot = 1;
532 }
533
534 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_wldev *dev)
535 {
536 bcm43xx_set_slot_time(dev, 20);
537 dev->short_slot = 0;
538 }
539
540 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
541 * Returns the _previously_ enabled IRQ mask.
542 */
543 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_wldev *dev, u32 mask)
544 {
545 u32 old_mask;
546
547 old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
548 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
549
550 return old_mask;
551 }
552
553 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
554 * Returns the _previously_ enabled IRQ mask.
555 */
556 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_wldev *dev, u32 mask)
557 {
558 u32 old_mask;
559
560 old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
561 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
562
563 return old_mask;
564 }
565
566 /* Synchronize IRQ top- and bottom-half.
567 * IRQs must be masked before calling this.
568 * This must not be called with the irq_lock held.
569 */
570 static void bcm43xx_synchronize_irq(struct bcm43xx_wldev *dev)
571 {
572 synchronize_irq(dev->dev->irq);
573 tasklet_kill(&dev->isr_tasklet);
574 }
575
576 /* DummyTransmission function, as documented on
577 * http://bcm-specs.sipsolutions.net/DummyTransmission
578 */
579 void bcm43xx_dummy_transmission(struct bcm43xx_wldev *dev)
580 {
581 struct bcm43xx_phy *phy = &dev->phy;
582 unsigned int i, max_loop;
583 u16 value;
584 u32 buffer[5] = {
585 0x00000000,
586 0x00D40000,
587 0x00000000,
588 0x01000000,
589 0x00000000,
590 };
591
592 switch (phy->type) {
593 case BCM43xx_PHYTYPE_A:
594 max_loop = 0x1E;
595 buffer[0] = 0x000201CC;
596 break;
597 case BCM43xx_PHYTYPE_B:
598 case BCM43xx_PHYTYPE_G:
599 max_loop = 0xFA;
600 buffer[0] = 0x000B846E;
601 break;
602 default:
603 assert(0);
604 return;
605 }
606
607 for (i = 0; i < 5; i++)
608 bcm43xx_ram_write(dev, i * 4, buffer[i]);
609
610 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
611
612 bcm43xx_write16(dev, 0x0568, 0x0000);
613 bcm43xx_write16(dev, 0x07C0, 0x0000);
614 value = ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0);
615 bcm43xx_write16(dev, 0x050C, value);
616 bcm43xx_write16(dev, 0x0508, 0x0000);
617 bcm43xx_write16(dev, 0x050A, 0x0000);
618 bcm43xx_write16(dev, 0x054C, 0x0000);
619 bcm43xx_write16(dev, 0x056A, 0x0014);
620 bcm43xx_write16(dev, 0x0568, 0x0826);
621 bcm43xx_write16(dev, 0x0500, 0x0000);
622 bcm43xx_write16(dev, 0x0502, 0x0030);
623
624 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
625 bcm43xx_radio_write16(dev, 0x0051, 0x0017);
626 for (i = 0x00; i < max_loop; i++) {
627 value = bcm43xx_read16(dev, 0x050E);
628 if (value & 0x0080)
629 break;
630 udelay(10);
631 }
632 for (i = 0x00; i < 0x0A; i++) {
633 value = bcm43xx_read16(dev, 0x050E);
634 if (value & 0x0400)
635 break;
636 udelay(10);
637 }
638 for (i = 0x00; i < 0x0A; i++) {
639 value = bcm43xx_read16(dev, 0x0690);
640 if (!(value & 0x0100))
641 break;
642 udelay(10);
643 }
644 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
645 bcm43xx_radio_write16(dev, 0x0051, 0x0037);
646 }
647
648 static void key_write(struct bcm43xx_wldev *dev,
649 u8 index, u8 algorithm, const u8 *key)
650 {
651 unsigned int i;
652 u32 offset;
653 u16 value;
654 u16 kidx;
655
656 /* Key index/algo block */
657 kidx = bcm43xx_kidx_to_fw(dev, index);
658 value = ((kidx << 4) | algorithm);
659 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
660 BCM43xx_SHM_SH_KEYIDXBLOCK +
661 (kidx * 2), value);
662
663 /* Write the key to the Key Table Pointer offset */
664 offset = dev->ktp + (index * BCM43xx_SEC_KEYSIZE);
665 for (i = 0; i < BCM43xx_SEC_KEYSIZE; i += 2) {
666 value = key[i];
667 value |= (u16)(key[i + 1]) << 8;
668 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
669 offset + i, value);
670 }
671 }
672
673 static void keymac_write(struct bcm43xx_wldev *dev,
674 u8 index, const u8 *addr)
675 {
676 u32 addrtmp[2];
677
678 assert(index >= 4 + 4);
679 memcpy(dev->key[index].address, addr, 6);
680 /* We have two default TX keys and two default RX keys.
681 * Physical mac 0 is mapped to physical key 8.
682 * So we must adjust the index here.
683 */
684 index -= 8;
685
686 addrtmp[0] = addr[0];
687 addrtmp[0] |= ((u32)(addr[1]) << 8);
688 addrtmp[0] |= ((u32)(addr[2]) << 16);
689 addrtmp[0] |= ((u32)(addr[3]) << 24);
690 addrtmp[1] = addr[4];
691 addrtmp[1] |= ((u32)(addr[5]) << 8);
692
693 if (dev->dev->id.revision >= 5) {
694 /* Receive match transmitter address mechanism */
695 bcm43xx_shm_write32(dev, BCM43xx_SHM_RCMTA,
696 (index * 2) + 0, addrtmp[0]);
697 bcm43xx_shm_write16(dev, BCM43xx_SHM_RCMTA,
698 (index * 2) + 1, addrtmp[1]);
699 } else {
700 /* RXE (Receive Engine) and
701 * PSM (Programmable State Machine) mechanism
702 */
703 if (index < 8) {
704 /* TODO write to RCM 16, 19, 22 and 25 */
705 TODO();
706 } else {
707 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
708 BCM43xx_SHM_SH_PSM + (index * 6) + 0,
709 addrtmp[0]);
710 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
711 BCM43xx_SHM_SH_PSM + (index * 6) + 4,
712 addrtmp[1]);
713 }
714 }
715 }
716
717 static void do_key_write(struct bcm43xx_wldev *dev,
718 u8 index, u8 algorithm,
719 const u8 *key, size_t key_len,
720 const u8 *mac_addr)
721 {
722 u8 buf[BCM43xx_SEC_KEYSIZE];
723
724 assert(index < dev->max_nr_keys);
725 assert(key_len <= BCM43xx_SEC_KEYSIZE);
726
727 memset(buf, 0, sizeof(buf));
728 if (index >= 8)
729 keymac_write(dev, index, buf); /* First zero out mac. */
730 memcpy(buf, key, key_len);
731 key_write(dev, index, algorithm, buf);
732 if (index >= 8)
733 keymac_write(dev, index, mac_addr);
734
735 dev->key[index].algorithm = algorithm;
736 }
737
738 static int bcm43xx_key_write(struct bcm43xx_wldev *dev,
739 int index, u8 algorithm,
740 const u8 *key, size_t key_len,
741 const u8 *mac_addr,
742 struct ieee80211_key_conf *keyconf)
743 {
744 int i;
745 int sta_keys_start;
746
747 if (key_len > BCM43xx_SEC_KEYSIZE)
748 return -EINVAL;
749 if (index < 0) {
750 /* Per station key with associated MAC address.
751 * Look if it already exists, if yes update, otherwise
752 * allocate a new key.
753 */
754 if (bcm43xx_new_kidx_api(dev))
755 sta_keys_start = 4;
756 else
757 sta_keys_start = 8;
758 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
759 if (compare_ether_addr(dev->key[i].address, mac_addr) == 0) {
760 /* found existing */
761 index = i;
762 break;
763 }
764 }
765 if (index < 0) {
766 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
767 if (!dev->key[i].enabled) {
768 /* found empty */
769 index = i;
770 break;
771 }
772 }
773 }
774 if (index < 0) {
775 dprintk(KERN_ERR PFX "Out of hw key memory\n");
776 return -ENOBUFS;
777 }
778 } else
779 assert(index <= 3);
780
781 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
782 if ((index <= 3) && !bcm43xx_new_kidx_api(dev)) {
783 /* Default RX key */
784 assert(mac_addr == NULL);
785 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
786 }
787 keyconf->hw_key_idx = index;
788
789 return 0;
790 }
791
792 static void bcm43xx_clear_keys(struct bcm43xx_wldev *dev)
793 {
794 static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
795 unsigned int i;
796
797 BUILD_BUG_ON(BCM43xx_SEC_KEYSIZE < ETH_ALEN);
798 for (i = 0; i < dev->max_nr_keys; i++) {
799 do_key_write(dev, i, BCM43xx_SEC_ALGO_NONE,
800 zero, BCM43xx_SEC_KEYSIZE,
801 zero);
802 dev->key[i].enabled = 0;
803 }
804 }
805
806 /* Turn the Analog ON/OFF */
807 static void bcm43xx_switch_analog(struct bcm43xx_wldev *dev, int on)
808 {
809 bcm43xx_write16(dev, BCM43xx_MMIO_PHY0, on ? 0 : 0xF4);
810 }
811
812 void bcm43xx_wireless_core_reset(struct bcm43xx_wldev *dev, u32 flags)
813 {
814 u32 tmslow;
815 u32 macctl;
816
817 flags |= BCM43xx_TMSLOW_PHYCLKEN;
818 flags |= BCM43xx_TMSLOW_PHYRESET;
819 ssb_device_enable(dev->dev, flags);
820 msleep(2); /* Wait for the PLL to turn on. */
821
822 /* Now take the PHY out of Reset again */
823 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
824 tmslow |= SSB_TMSLOW_FGC;
825 tmslow &= ~BCM43xx_TMSLOW_PHYRESET;
826 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
827 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
828 msleep(1);
829 tmslow &= ~SSB_TMSLOW_FGC;
830 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
831 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
832 msleep(1);
833
834 /* Turn Analog ON */
835 bcm43xx_switch_analog(dev, 1);
836
837 macctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
838 macctl &= ~BCM43xx_MACCTL_GMODE;
839 if (flags & BCM43xx_TMSLOW_GMODE)
840 macctl |= BCM43xx_MACCTL_GMODE;
841 macctl |= BCM43xx_MACCTL_IHR_ENABLED;
842 bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, macctl);
843 }
844
845 static void handle_irq_transmit_status(struct bcm43xx_wldev *dev)
846 {
847 u32 v0, v1;
848 u16 tmp;
849 struct bcm43xx_txstatus stat;
850
851 while (1) {
852 v0 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
853 if (!(v0 & 0x00000001))
854 break;
855 v1 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
856
857 stat.cookie = (v0 >> 16);
858 stat.seq = (v1 & 0x0000FFFF);
859 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
860 tmp = (v0 & 0x0000FFFF);
861 stat.frame_count = ((tmp & 0xF000) >> 12);
862 stat.rts_count = ((tmp & 0x0F00) >> 8);
863 stat.supp_reason = ((tmp & 0x001C) >> 2);
864 stat.pm_indicated = !!(tmp & 0x0080);
865 stat.intermediate = !!(tmp & 0x0040);
866 stat.for_ampdu = !!(tmp & 0x0020);
867 stat.acked = !!(tmp & 0x0002);
868
869 bcm43xx_handle_txstatus(dev, &stat);
870 }
871 }
872
873 static void drain_txstatus_queue(struct bcm43xx_wldev *dev)
874 {
875 u32 dummy;
876
877 if (dev->dev->id.revision < 5)
878 return;
879 /* Read all entries from the microcode TXstatus FIFO
880 * and throw them away.
881 */
882 while (1) {
883 dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
884 if (!(dummy & 0x00000001))
885 break;
886 dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
887 }
888 }
889
890 static u32 bcm43xx_jssi_read(struct bcm43xx_wldev *dev)
891 {
892 u32 val = 0;
893
894 val = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x08A);
895 val <<= 16;
896 val |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x088);
897
898 return val;
899 }
900
901 static void bcm43xx_jssi_write(struct bcm43xx_wldev *dev, u32 jssi)
902 {
903 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x088,
904 (jssi & 0x0000FFFF));
905 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x08A,
906 (jssi & 0xFFFF0000) >> 16);
907 }
908
909 static void bcm43xx_generate_noise_sample(struct bcm43xx_wldev *dev)
910 {
911 bcm43xx_jssi_write(dev, 0x7F7F7F7F);
912 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
913 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
914 | (1 << 4));
915 assert(dev->noisecalc.channel_at_start == dev->phy.channel);
916 }
917
918 static void bcm43xx_calculate_link_quality(struct bcm43xx_wldev *dev)
919 {
920 /* Top half of Link Quality calculation. */
921
922 if (dev->noisecalc.calculation_running)
923 return;
924 dev->noisecalc.channel_at_start = dev->phy.channel;
925 dev->noisecalc.calculation_running = 1;
926 dev->noisecalc.nr_samples = 0;
927
928 bcm43xx_generate_noise_sample(dev);
929 }
930
931 static void handle_irq_noise(struct bcm43xx_wldev *dev)
932 {
933 struct bcm43xx_phy *phy = &dev->phy;
934 u16 tmp;
935 u8 noise[4];
936 u8 i, j;
937 s32 average;
938
939 /* Bottom half of Link Quality calculation. */
940
941 assert(dev->noisecalc.calculation_running);
942 if (dev->noisecalc.channel_at_start != phy->channel)
943 goto drop_calculation;
944 *((u32 *)noise) = cpu_to_le32(bcm43xx_jssi_read(dev));
945 if (noise[0] == 0x7F || noise[1] == 0x7F ||
946 noise[2] == 0x7F || noise[3] == 0x7F)
947 goto generate_new;
948
949 /* Get the noise samples. */
950 assert(dev->noisecalc.nr_samples < 8);
951 i = dev->noisecalc.nr_samples;
952 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
953 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
954 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
955 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
956 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
957 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
958 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
959 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
960 dev->noisecalc.nr_samples++;
961 if (dev->noisecalc.nr_samples == 8) {
962 /* Calculate the Link Quality by the noise samples. */
963 average = 0;
964 for (i = 0; i < 8; i++) {
965 for (j = 0; j < 4; j++)
966 average += dev->noisecalc.samples[i][j];
967 }
968 average /= (8 * 4);
969 average *= 125;
970 average += 64;
971 average /= 128;
972 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x40C);
973 tmp = (tmp / 128) & 0x1F;
974 if (tmp >= 8)
975 average += 2;
976 else
977 average -= 25;
978 if (tmp == 8)
979 average -= 72;
980 else
981 average -= 48;
982
983 dev->stats.link_noise = average;
984 drop_calculation:
985 dev->noisecalc.calculation_running = 0;
986 return;
987 }
988 generate_new:
989 bcm43xx_generate_noise_sample(dev);
990 }
991
992 static void handle_irq_tbtt_indication(struct bcm43xx_wldev *dev)
993 {
994 if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
995 ///TODO: PS TBTT
996 } else {
997 if (1/*FIXME: the last PSpoll frame was sent successfully */)
998 bcm43xx_power_saving_ctl_bits(dev, -1, -1);
999 }
1000 dev->reg124_set_0x4 = 0;
1001 if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1002 dev->reg124_set_0x4 = 1;
1003 }
1004
1005 static void handle_irq_atim_end(struct bcm43xx_wldev *dev)
1006 {
1007 if (!dev->reg124_set_0x4 /*FIXME rename this variable*/)
1008 return;
1009 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
1010 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
1011 | 0x4);
1012 }
1013
1014 static void handle_irq_pmq(struct bcm43xx_wldev *dev)
1015 {
1016 u32 tmp;
1017
1018 //TODO: AP mode.
1019
1020 while (1) {
1021 tmp = bcm43xx_read32(dev, BCM43xx_MMIO_PS_STATUS);
1022 if (!(tmp & 0x00000008))
1023 break;
1024 }
1025 /* 16bit write is odd, but correct. */
1026 bcm43xx_write16(dev, BCM43xx_MMIO_PS_STATUS, 0x0002);
1027 }
1028
1029 static void bcm43xx_write_template_common(struct bcm43xx_wldev *dev,
1030 const u8* data, u16 size,
1031 u16 ram_offset,
1032 u16 shm_size_offset, u8 rate)
1033 {
1034 u32 i, tmp;
1035 struct bcm43xx_plcp_hdr4 plcp;
1036
1037 plcp.data = 0;
1038 bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1039 bcm43xx_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1040 ram_offset += sizeof(u32);
1041 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1042 * So leave the first two bytes of the next write blank.
1043 */
1044 tmp = (u32)(data[0]) << 16;
1045 tmp |= (u32)(data[1]) << 24;
1046 bcm43xx_ram_write(dev, ram_offset, tmp);
1047 ram_offset += sizeof(u32);
1048 for (i = 2; i < size; i += sizeof(u32)) {
1049 tmp = (u32)(data[i + 0]);
1050 if (i + 1 < size)
1051 tmp |= (u32)(data[i + 1]) << 8;
1052 if (i + 2 < size)
1053 tmp |= (u32)(data[i + 2]) << 16;
1054 if (i + 3 < size)
1055 tmp |= (u32)(data[i + 3]) << 24;
1056 bcm43xx_ram_write(dev, ram_offset + i - 2, tmp);
1057 }
1058 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_size_offset,
1059 size + sizeof(struct bcm43xx_plcp_hdr6));
1060 }
1061
1062 static void bcm43xx_write_beacon_template(struct bcm43xx_wldev *dev,
1063 u16 ram_offset,
1064 u16 shm_size_offset, u8 rate)
1065 {
1066 int len;
1067 const u8 *data;
1068
1069 assert(dev->cached_beacon);
1070 len = min((size_t)dev->cached_beacon->len,
1071 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
1072 data = (const u8 *)(dev->cached_beacon->data);
1073 bcm43xx_write_template_common(dev, data,
1074 len, ram_offset,
1075 shm_size_offset, rate);
1076 }
1077
1078 static void bcm43xx_write_probe_resp_plcp(struct bcm43xx_wldev *dev,
1079 u16 shm_offset, u16 size, u8 rate)
1080 {
1081 struct bcm43xx_plcp_hdr4 plcp;
1082 u32 tmp;
1083 u16 packet_time;
1084
1085 plcp.data = 0;
1086 bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1087 /*
1088 * 144 + 48 + 10 = preamble + PLCP + SIFS,
1089 * taken from mac80211 timings calculation.
1090 *
1091 * FIXME: long preamble assumed!
1092 *
1093 */
1094 packet_time = 202 + (size + FCS_LEN) * 16 / rate;
1095 if ((size + FCS_LEN) * 16 % rate >= rate / 2)
1096 ++packet_time;
1097
1098 /* Write PLCP in two parts and timing for packet transfer */
1099 tmp = le32_to_cpu(plcp.data);
1100 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset,
1101 tmp & 0xFFFF);
1102 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 2,
1103 tmp >> 16);
1104 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 6,
1105 packet_time);
1106 }
1107
1108 /* Instead of using custom probe response template, this function
1109 * just patches custom beacon template by:
1110 * 1) Changing packet type
1111 * 2) Patching duration field
1112 * 3) Stripping TIM
1113 */
1114 static u8 * bcm43xx_generate_probe_resp(struct bcm43xx_wldev *dev,
1115 u16* dest_size, u8 rate)
1116 {
1117 const u8 *src_data;
1118 u8 *dest_data;
1119 u16 src_size, elem_size, src_pos, dest_pos, tmp;
1120
1121 assert(dev->cached_beacon);
1122 src_size = dev->cached_beacon->len;
1123 src_data = (const u8*)dev->cached_beacon->data;
1124
1125 if (unlikely(src_size < 0x24)) {
1126 dprintk(KERN_ERR PFX "bcm43xx_generate_probe_resp: "
1127 "invalid beacon\n");
1128 return NULL;
1129 }
1130
1131 dest_data = kmalloc(src_size, GFP_ATOMIC);
1132 if (unlikely(!dest_data))
1133 return NULL;
1134
1135 /* 0x24 is offset of first variable-len Information-Element
1136 * in beacon frame.
1137 */
1138 memcpy(dest_data, src_data, 0x24);
1139 src_pos = dest_pos = 0x24;
1140 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1141 elem_size = src_data[src_pos + 1] + 2;
1142 if (src_data[src_pos] != 0x05) { /* TIM */
1143 memcpy(dest_data + dest_pos, src_data + src_pos,
1144 elem_size);
1145 dest_pos += elem_size;
1146 }
1147 }
1148 *dest_size = dest_pos;
1149
1150 /* Set the frame control. */
1151 dest_data[0] = (IEEE80211_FTYPE_MGMT |
1152 IEEE80211_STYPE_PROBE_RESP);
1153 dest_data[1] = 0;
1154
1155 /* Set the duration field.
1156 *
1157 * 144 + 48 + 10 = preamble + PLCP + SIFS,
1158 * taken from mac80211 timings calculation.
1159 *
1160 * FIXME: long preamble assumed!
1161 *
1162 */
1163 tmp = 202 + (14 + FCS_LEN) * 16 / rate;
1164 if ((14 + FCS_LEN) * 16 % rate >= rate / 2)
1165 ++tmp;
1166
1167 dest_data[2] = tmp & 0xFF;
1168 dest_data[3] = (tmp >> 8) & 0xFF;
1169
1170 return dest_data;
1171 }
1172
1173 static void bcm43xx_write_probe_resp_template(struct bcm43xx_wldev *dev,
1174 u16 ram_offset,
1175 u16 shm_size_offset, u8 rate)
1176 {
1177 u8* probe_resp_data;
1178 u16 size;
1179
1180 assert(dev->cached_beacon);
1181 size = dev->cached_beacon->len;
1182 probe_resp_data = bcm43xx_generate_probe_resp(dev, &size, rate);
1183 if (unlikely(!probe_resp_data))
1184 return;
1185
1186 /* Looks like PLCP headers plus packet timings are stored for
1187 * all possible basic rates
1188 */
1189 bcm43xx_write_probe_resp_plcp(dev, 0x31A, size,
1190 BCM43xx_CCK_RATE_1MB);
1191 bcm43xx_write_probe_resp_plcp(dev, 0x32C, size,
1192 BCM43xx_CCK_RATE_2MB);
1193 bcm43xx_write_probe_resp_plcp(dev, 0x33E, size,
1194 BCM43xx_CCK_RATE_5MB);
1195 bcm43xx_write_probe_resp_plcp(dev, 0x350, size,
1196 BCM43xx_CCK_RATE_11MB);
1197
1198 size = min((size_t)size,
1199 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
1200 bcm43xx_write_template_common(dev, probe_resp_data,
1201 size, ram_offset,
1202 shm_size_offset, rate);
1203 kfree(probe_resp_data);
1204 }
1205
1206 static int bcm43xx_refresh_cached_beacon(struct bcm43xx_wldev *dev,
1207 struct sk_buff *beacon)
1208 {
1209 if (dev->cached_beacon)
1210 kfree_skb(dev->cached_beacon);
1211 dev->cached_beacon = beacon;
1212
1213 return 0;
1214 }
1215
1216 static void bcm43xx_update_templates(struct bcm43xx_wldev *dev)
1217 {
1218 u32 status;
1219
1220 assert(dev->cached_beacon);
1221
1222 bcm43xx_write_beacon_template(dev, 0x68, 0x18,
1223 BCM43xx_CCK_RATE_1MB);
1224 bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
1225 BCM43xx_CCK_RATE_1MB);
1226 bcm43xx_write_probe_resp_template(dev, 0x268, 0x4A,
1227 BCM43xx_CCK_RATE_11MB);
1228
1229 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
1230 status |= 0x03;
1231 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1232 }
1233
1234 static void bcm43xx_refresh_templates(struct bcm43xx_wldev *dev,
1235 struct sk_buff *beacon)
1236 {
1237 int err;
1238
1239 err = bcm43xx_refresh_cached_beacon(dev, beacon);
1240 if (unlikely(err))
1241 return;
1242 bcm43xx_update_templates(dev);
1243 }
1244
1245 static void bcm43xx_set_ssid(struct bcm43xx_wldev *dev,
1246 const u8 *ssid, u8 ssid_len)
1247 {
1248 u32 tmp;
1249 u16 i, len;
1250
1251 len = min((u16)ssid_len, (u16)0x100);
1252 for (i = 0; i < len; i += sizeof(u32)) {
1253 tmp = (u32)(ssid[i + 0]);
1254 if (i + 1 < len)
1255 tmp |= (u32)(ssid[i + 1]) << 8;
1256 if (i + 2 < len)
1257 tmp |= (u32)(ssid[i + 2]) << 16;
1258 if (i + 3 < len)
1259 tmp |= (u32)(ssid[i + 3]) << 24;
1260 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
1261 0x380 + i, tmp);
1262 }
1263 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
1264 0x48, len);
1265 }
1266
1267 static void bcm43xx_set_beacon_int(struct bcm43xx_wldev *dev, u16 beacon_int)
1268 {
1269 bcm43xx_time_lock(dev);
1270 if (dev->dev->id.revision >= 3) {
1271 bcm43xx_write32(dev, 0x188, (beacon_int << 16));
1272 } else {
1273 bcm43xx_write16(dev, 0x606, (beacon_int >> 6));
1274 bcm43xx_write16(dev, 0x610, beacon_int);
1275 }
1276 bcm43xx_time_unlock(dev);
1277 }
1278
1279 static void handle_irq_beacon(struct bcm43xx_wldev *dev)
1280 {
1281 u32 status;
1282
1283 if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1284 return;
1285
1286 dev->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1287 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
1288
1289 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1290 /* ACK beacon IRQ. */
1291 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
1292 BCM43xx_IRQ_BEACON);
1293 dev->irq_savedstate |= BCM43xx_IRQ_BEACON;
1294 if (dev->cached_beacon)
1295 kfree_skb(dev->cached_beacon);
1296 dev->cached_beacon = NULL;
1297 return;
1298 }
1299 if (!(status & 0x1)) {
1300 bcm43xx_write_beacon_template(dev, 0x68, 0x18,
1301 BCM43xx_CCK_RATE_1MB);
1302 status |= 0x1;
1303 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
1304 status);
1305 }
1306 if (!(status & 0x2)) {
1307 bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
1308 BCM43xx_CCK_RATE_1MB);
1309 status |= 0x2;
1310 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
1311 status);
1312 }
1313 }
1314
1315 static void handle_irq_ucode_debug(struct bcm43xx_wldev *dev)
1316 {
1317 //TODO
1318 }
1319
1320 /* Interrupt handler bottom-half */
1321 static void bcm43xx_interrupt_tasklet(struct bcm43xx_wldev *dev)
1322 {
1323 u32 reason;
1324 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1325 u32 merged_dma_reason = 0;
1326 int i, activity = 0;
1327 unsigned long flags;
1328
1329 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1330
1331 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
1332 assert(dev->started);
1333
1334 reason = dev->irq_reason;
1335 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1336 dma_reason[i] = dev->dma_reason[i];
1337 merged_dma_reason |= dma_reason[i];
1338 }
1339
1340 if (unlikely(reason & BCM43xx_IRQ_MAC_TXERR))
1341 printkl(KERN_ERR PFX "MAC transmission error\n");
1342
1343 if (unlikely(reason & BCM43xx_IRQ_PHY_TXERR))
1344 printkl(KERN_ERR PFX "PHY transmission error\n");
1345
1346 if (unlikely(merged_dma_reason & (BCM43xx_DMAIRQ_FATALMASK |
1347 BCM43xx_DMAIRQ_NONFATALMASK))) {
1348 if (merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK) {
1349 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1350 "0x%08X, 0x%08X, 0x%08X, "
1351 "0x%08X, 0x%08X, 0x%08X\n",
1352 dma_reason[0], dma_reason[1],
1353 dma_reason[2], dma_reason[3],
1354 dma_reason[4], dma_reason[5]);
1355 bcm43xx_controller_restart(dev, "DMA error");
1356 mmiowb();
1357 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1358 return;
1359 }
1360 if (merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK) {
1361 printkl(KERN_ERR PFX "DMA error: "
1362 "0x%08X, 0x%08X, 0x%08X, "
1363 "0x%08X, 0x%08X, 0x%08X\n",
1364 dma_reason[0], dma_reason[1],
1365 dma_reason[2], dma_reason[3],
1366 dma_reason[4], dma_reason[5]);
1367 }
1368 }
1369
1370 if (unlikely(reason & BCM43xx_IRQ_UCODE_DEBUG))
1371 handle_irq_ucode_debug(dev);
1372 if (reason & BCM43xx_IRQ_TBTT_INDI)
1373 handle_irq_tbtt_indication(dev);
1374 if (reason & BCM43xx_IRQ_ATIM_END)
1375 handle_irq_atim_end(dev);
1376 if (reason & BCM43xx_IRQ_BEACON)
1377 handle_irq_beacon(dev);
1378 if (reason & BCM43xx_IRQ_PMQ)
1379 handle_irq_pmq(dev);
1380 if (reason & BCM43xx_IRQ_TXFIFO_FLUSH_OK)
1381 ;/*TODO*/
1382 if (reason & BCM43xx_IRQ_NOISESAMPLE_OK)
1383 handle_irq_noise(dev);
1384
1385 /* Check the DMA reason registers for received data. */
1386 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1387 if (bcm43xx_using_pio(dev))
1388 bcm43xx_pio_rx(dev->pio.queue0);
1389 else
1390 bcm43xx_dma_rx(dev->dma.rx_ring0);
1391 /* We intentionally don't set "activity" to 1, here. */
1392 }
1393 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1394 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1395 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1396 if (bcm43xx_using_pio(dev))
1397 bcm43xx_pio_rx(dev->pio.queue3);
1398 else
1399 bcm43xx_dma_rx(dev->dma.rx_ring3);
1400 activity = 1;
1401 }
1402 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1403 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1404
1405 if (reason & BCM43xx_IRQ_TX_OK) {
1406 handle_irq_transmit_status(dev);
1407 activity = 1;
1408 //TODO: In AP mode, this also causes sending of powersave responses.
1409 }
1410
1411 if (!modparam_noleds)
1412 bcm43xx_leds_update(dev, activity);
1413 bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
1414 mmiowb();
1415 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1416 }
1417
1418 static void pio_irq_workaround(struct bcm43xx_wldev *dev,
1419 u16 base, int queueidx)
1420 {
1421 u16 rxctl;
1422
1423 rxctl = bcm43xx_read16(dev, base + BCM43xx_PIO_RXCTL);
1424 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1425 dev->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1426 else
1427 dev->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1428 }
1429
1430 static void bcm43xx_interrupt_ack(struct bcm43xx_wldev *dev, u32 reason)
1431 {
1432 if (bcm43xx_using_pio(dev) &&
1433 (dev->dev->id.revision < 3) &&
1434 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1435 /* Apply a PIO specific workaround to the dma_reasons */
1436 pio_irq_workaround(dev, BCM43xx_MMIO_PIO1_BASE, 0);
1437 pio_irq_workaround(dev, BCM43xx_MMIO_PIO2_BASE, 1);
1438 pio_irq_workaround(dev, BCM43xx_MMIO_PIO3_BASE, 2);
1439 pio_irq_workaround(dev, BCM43xx_MMIO_PIO4_BASE, 3);
1440 }
1441
1442 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1443
1444 bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_REASON,
1445 dev->dma_reason[0]);
1446 bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_REASON,
1447 dev->dma_reason[1]);
1448 bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_REASON,
1449 dev->dma_reason[2]);
1450 bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_REASON,
1451 dev->dma_reason[3]);
1452 bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_REASON,
1453 dev->dma_reason[4]);
1454 bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_REASON,
1455 dev->dma_reason[5]);
1456 }
1457
1458 /* Interrupt handler top-half */
1459 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
1460 {
1461 irqreturn_t ret = IRQ_HANDLED;
1462 struct bcm43xx_wldev *dev = dev_id;
1463 u32 reason;
1464
1465 if (!dev)
1466 return IRQ_NONE;
1467
1468 spin_lock(&dev->wl->irq_lock);
1469
1470 reason = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
1471 if (reason == 0xffffffff) {
1472 /* irq not for us (shared irq) */
1473 ret = IRQ_NONE;
1474 goto out;
1475 }
1476 reason &= bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
1477 if (!reason)
1478 goto out;
1479
1480 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
1481 assert(dev->started);
1482
1483 dev->dma_reason[0] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA0_REASON)
1484 & 0x0001DC00;
1485 dev->dma_reason[1] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA1_REASON)
1486 & 0x0000DC00;
1487 dev->dma_reason[2] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA2_REASON)
1488 & 0x0000DC00;
1489 dev->dma_reason[3] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA3_REASON)
1490 & 0x0001DC00;
1491 dev->dma_reason[4] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA4_REASON)
1492 & 0x0000DC00;
1493 dev->dma_reason[5] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA5_REASON)
1494 & 0x0000DC00;
1495
1496 bcm43xx_interrupt_ack(dev, reason);
1497 /* disable all IRQs. They are enabled again in the bottom half. */
1498 dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
1499 /* save the reason code and call our bottom half. */
1500 dev->irq_reason = reason;
1501 tasklet_schedule(&dev->isr_tasklet);
1502 out:
1503 mmiowb();
1504 spin_unlock(&dev->wl->irq_lock);
1505
1506 return ret;
1507 }
1508
1509 static void bcm43xx_release_firmware(struct bcm43xx_wldev *dev)
1510 {
1511 release_firmware(dev->fw.ucode);
1512 dev->fw.ucode = NULL;
1513 release_firmware(dev->fw.pcm);
1514 dev->fw.pcm = NULL;
1515 release_firmware(dev->fw.initvals0);
1516 dev->fw.initvals0 = NULL;
1517 release_firmware(dev->fw.initvals1);
1518 dev->fw.initvals1 = NULL;
1519 }
1520
1521 static int bcm43xx_request_firmware(struct bcm43xx_wldev *dev)
1522 {
1523 u8 rev = dev->dev->id.revision;
1524 int err = 0;
1525 int nr;
1526 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1527
1528 if (!dev->fw.ucode) {
1529 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1530 (rev >= 5 ? 5 : rev),
1531 modparam_fwpostfix);
1532 err = request_firmware(&dev->fw.ucode, buf, dev->dev->dev);
1533 if (err) {
1534 printk(KERN_ERR PFX
1535 "Error: Microcode \"%s\" not available or load failed.\n",
1536 buf);
1537 goto error;
1538 }
1539 }
1540
1541 if (!dev->fw.pcm) {
1542 snprintf(buf, ARRAY_SIZE(buf),
1543 "bcm43xx_pcm%d%s.fw",
1544 (rev < 5 ? 4 : 5),
1545 modparam_fwpostfix);
1546 err = request_firmware(&dev->fw.pcm, buf, dev->dev->dev);
1547 if (err) {
1548 printk(KERN_ERR PFX
1549 "Error: PCM \"%s\" not available or load failed.\n",
1550 buf);
1551 goto error;
1552 }
1553 }
1554
1555 if (!dev->fw.initvals0) {
1556 if (rev == 2 || rev == 4) {
1557 switch (dev->phy.type) {
1558 case BCM43xx_PHYTYPE_A:
1559 nr = 3;
1560 break;
1561 case BCM43xx_PHYTYPE_B:
1562 case BCM43xx_PHYTYPE_G:
1563 nr = 1;
1564 break;
1565 default:
1566 goto err_noinitval;
1567 }
1568
1569 } else if (rev >= 5) {
1570 switch (dev->phy.type) {
1571 case BCM43xx_PHYTYPE_A:
1572 nr = 7;
1573 break;
1574 case BCM43xx_PHYTYPE_B:
1575 case BCM43xx_PHYTYPE_G:
1576 nr = 5;
1577 break;
1578 default:
1579 goto err_noinitval;
1580 }
1581 } else
1582 goto err_noinitval;
1583 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1584 nr, modparam_fwpostfix);
1585
1586 err = request_firmware(&dev->fw.initvals0, buf, dev->dev->dev);
1587 if (err) {
1588 printk(KERN_ERR PFX
1589 "Error: InitVals \"%s\" not available or load failed.\n",
1590 buf);
1591 goto error;
1592 }
1593 if (dev->fw.initvals0->size % sizeof(struct bcm43xx_initval)) {
1594 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1595 goto error;
1596 }
1597 }
1598
1599 if (!dev->fw.initvals1) {
1600 if (rev >= 5) {
1601 u32 sbtmstatehigh;
1602
1603 switch (dev->phy.type) {
1604 case BCM43xx_PHYTYPE_A:
1605 sbtmstatehigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1606 if (sbtmstatehigh & 0x00010000)
1607 nr = 9;
1608 else
1609 nr = 10;
1610 break;
1611 case BCM43xx_PHYTYPE_B:
1612 case BCM43xx_PHYTYPE_G:
1613 nr = 6;
1614 break;
1615 default:
1616 goto err_noinitval;
1617 }
1618 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1619 nr, modparam_fwpostfix);
1620
1621 err = request_firmware(&dev->fw.initvals1, buf, dev->dev->dev);
1622 if (err) {
1623 printk(KERN_ERR PFX
1624 "Error: InitVals \"%s\" not available or load failed.\n",
1625 buf);
1626 goto error;
1627 }
1628 if (dev->fw.initvals1->size % sizeof(struct bcm43xx_initval)) {
1629 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1630 goto error;
1631 }
1632 }
1633 }
1634
1635 out:
1636 return err;
1637 error:
1638 bcm43xx_release_firmware(dev);
1639 goto out;
1640 err_noinitval:
1641 printk(KERN_ERR PFX "Error: No InitVals available!\n");
1642 err = -ENOENT;
1643 goto error;
1644 }
1645
1646 static int bcm43xx_upload_microcode(struct bcm43xx_wldev *dev)
1647 {
1648 const __be32 *data;
1649 unsigned int i, len;
1650 u16 fwrev, fwpatch, fwdate, fwtime;
1651 u32 tmp;
1652 int err = 0;
1653
1654 /* Upload Microcode. */
1655 data = (__be32 *)(dev->fw.ucode->data);
1656 len = dev->fw.ucode->size / sizeof(__be32);
1657 bcm43xx_shm_control_word(dev,
1658 BCM43xx_SHM_UCODE | BCM43xx_SHM_AUTOINC_W,
1659 0x0000);
1660 for (i = 0; i < len; i++) {
1661 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
1662 be32_to_cpu(data[i]));
1663 udelay(10);
1664 }
1665
1666 /* Upload PCM data. */
1667 data = (__be32 *)(dev->fw.pcm->data);
1668 len = dev->fw.pcm->size / sizeof(__be32);
1669 bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EA);
1670 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, 0x00004000);
1671 /* No need for autoinc bit in SHM_HW */
1672 bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EB);
1673 for (i = 0; i < len; i++) {
1674 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
1675 be32_to_cpu(data[i]));
1676 udelay(10);
1677 }
1678
1679 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_ALL);
1680 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
1681
1682 /* Wait for the microcode to load and respond */
1683 i = 0;
1684 while (1) {
1685 tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
1686 if (tmp == BCM43xx_IRQ_MAC_SUSPENDED)
1687 break;
1688 i++;
1689 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
1690 printk(KERN_ERR PFX "Microcode not responding\n");
1691 err = -ENODEV;
1692 goto out;
1693 }
1694 udelay(10);
1695 }
1696 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
1697
1698 /* Get and check the revisions. */
1699 fwrev = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1700 BCM43xx_SHM_SH_UCODEREV);
1701 fwpatch = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1702 BCM43xx_SHM_SH_UCODEPATCH);
1703 fwdate = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1704 BCM43xx_SHM_SH_UCODEDATE);
1705 fwtime = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1706 BCM43xx_SHM_SH_UCODETIME);
1707
1708 if (fwrev <= 0x128) {
1709 printk(KERN_ERR PFX "YOUR FIRMWARE IS TOO OLD. Firmware from "
1710 "binary drivers older than version 4.x is unsupported. "
1711 "You must upgrade your firmware files.\n");
1712 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0);
1713 err = -EOPNOTSUPP;
1714 goto out;
1715 }
1716 printk(KERN_DEBUG PFX "Loading firmware version %u.%u "
1717 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1718 fwrev, fwpatch,
1719 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1720 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1721
1722 dev->fw.rev = fwrev;
1723 dev->fw.patch = fwpatch;
1724
1725 out:
1726 return err;
1727 }
1728
1729 static int bcm43xx_write_initvals(struct bcm43xx_wldev *dev,
1730 const struct bcm43xx_initval *data,
1731 const unsigned int len)
1732 {
1733 u16 offset, size;
1734 u32 value;
1735 unsigned int i;
1736
1737 for (i = 0; i < len; i++) {
1738 offset = be16_to_cpu(data[i].offset);
1739 size = be16_to_cpu(data[i].size);
1740 value = be32_to_cpu(data[i].value);
1741
1742 if (unlikely(offset >= 0x1000))
1743 goto err_format;
1744 if (size == 2) {
1745 if (unlikely(value & 0xFFFF0000))
1746 goto err_format;
1747 bcm43xx_write16(dev, offset, (u16)value);
1748 } else if (size == 4) {
1749 bcm43xx_write32(dev, offset, value);
1750 } else
1751 goto err_format;
1752 }
1753
1754 return 0;
1755
1756 err_format:
1757 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
1758 "Please fix your bcm43xx firmware files.\n");
1759 return -EPROTO;
1760 }
1761
1762 static int bcm43xx_upload_initvals(struct bcm43xx_wldev *dev)
1763 {
1764 int err;
1765
1766 err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals0->data,
1767 dev->fw.initvals0->size / sizeof(struct bcm43xx_initval));
1768 if (err)
1769 goto out;
1770 if (dev->fw.initvals1) {
1771 err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals1->data,
1772 dev->fw.initvals1->size / sizeof(struct bcm43xx_initval));
1773 if (err)
1774 goto out;
1775 }
1776 out:
1777 return err;
1778 }
1779
1780 /* Initialize the GPIOs
1781 * http://bcm-specs.sipsolutions.net/GPIO
1782 */
1783 static int bcm43xx_gpio_init(struct bcm43xx_wldev *dev)
1784 {
1785 struct ssb_bus *bus = dev->dev->bus;
1786 struct ssb_device *gpiodev, *pcidev = NULL;
1787 u32 mask, set;
1788
1789 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
1790 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
1791 & 0xFFFF3FFF);
1792
1793 bcm43xx_leds_switch_all(dev, 0);
1794 bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
1795 bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
1796 | 0x000F);
1797
1798 mask = 0x0000001F;
1799 set = 0x0000000F;
1800 if (dev->dev->bus->chip_id == 0x4301) {
1801 mask |= 0x0060;
1802 set |= 0x0060;
1803 }
1804 if (0 /* FIXME: conditional unknown */) {
1805 bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
1806 bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
1807 | 0x0100);
1808 mask |= 0x0180;
1809 set |= 0x0180;
1810 }
1811 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) {
1812 bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
1813 bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
1814 | 0x0200);
1815 mask |= 0x0200;
1816 set |= 0x0200;
1817 }
1818 if (dev->dev->id.revision >= 2)
1819 mask |= 0x0010; /* FIXME: This is redundant. */
1820
1821 #ifdef CONFIG_SSB_DRIVER_PCICORE
1822 pcidev = bus->pcicore.dev;
1823 #endif
1824 gpiodev = bus->chipco.dev ? : pcidev;
1825 if (!gpiodev)
1826 return 0;
1827 ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL,
1828 (ssb_read32(gpiodev, BCM43xx_GPIO_CONTROL)
1829 & mask) | set);
1830
1831 return 0;
1832 }
1833
1834 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1835 static void bcm43xx_gpio_cleanup(struct bcm43xx_wldev *dev)
1836 {
1837 struct ssb_bus *bus = dev->dev->bus;
1838 struct ssb_device *gpiodev, *pcidev = NULL;
1839
1840 #ifdef CONFIG_SSB_DRIVER_PCICORE
1841 pcidev = bus->pcicore.dev;
1842 #endif
1843 gpiodev = bus->chipco.dev ? : pcidev;
1844 if (!gpiodev)
1845 return;
1846 ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL, 0);
1847 }
1848
1849 /* http://bcm-specs.sipsolutions.net/EnableMac */
1850 void bcm43xx_mac_enable(struct bcm43xx_wldev *dev)
1851 {
1852 dev->mac_suspended--;
1853 assert(dev->mac_suspended >= 0);
1854 if (dev->mac_suspended == 0) {
1855 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
1856 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
1857 | BCM43xx_SBF_MAC_ENABLED);
1858 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
1859 BCM43xx_IRQ_MAC_SUSPENDED);
1860 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1861 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
1862 bcm43xx_power_saving_ctl_bits(dev, -1, -1);
1863 }
1864 }
1865
1866 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1867 void bcm43xx_mac_suspend(struct bcm43xx_wldev *dev)
1868 {
1869 int i;
1870 u32 tmp;
1871
1872 assert(dev->mac_suspended >= 0);
1873 if (dev->mac_suspended == 0) {
1874 bcm43xx_power_saving_ctl_bits(dev, -1, 1);
1875 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
1876 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
1877 & ~BCM43xx_SBF_MAC_ENABLED);
1878 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
1879 for (i = 10000; i; i--) {
1880 tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
1881 if (tmp & BCM43xx_IRQ_MAC_SUSPENDED)
1882 goto out;
1883 udelay(1);
1884 }
1885 printkl(KERN_ERR PFX "MAC suspend failed\n");
1886 }
1887 out:
1888 dev->mac_suspended++;
1889 }
1890
1891 static void bcm43xx_adjust_opmode(struct bcm43xx_wldev *dev)
1892 {
1893 struct bcm43xx_wl *wl = dev->wl;
1894 u32 ctl;
1895 u16 cfp_pretbtt;
1896
1897 ctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
1898 /* Reset status to STA infrastructure mode. */
1899 ctl &= ~BCM43xx_MACCTL_AP;
1900 ctl &= ~BCM43xx_MACCTL_KEEP_CTL;
1901 ctl &= ~BCM43xx_MACCTL_KEEP_BADPLCP;
1902 ctl &= ~BCM43xx_MACCTL_KEEP_BAD;
1903 ctl &= ~BCM43xx_MACCTL_PROMISC;
1904 ctl |= BCM43xx_MACCTL_INFRA;
1905
1906 if (wl->operating) {
1907 switch (wl->if_type) {
1908 case IEEE80211_IF_TYPE_AP:
1909 ctl |= BCM43xx_MACCTL_AP;
1910 break;
1911 case IEEE80211_IF_TYPE_IBSS:
1912 ctl &= ~BCM43xx_MACCTL_INFRA;
1913 break;
1914 case IEEE80211_IF_TYPE_STA:
1915 case IEEE80211_IF_TYPE_MNTR:
1916 case IEEE80211_IF_TYPE_WDS:
1917 break;
1918 default:
1919 assert(0);
1920 }
1921 }
1922 if (wl->monitor) {
1923 ctl |= BCM43xx_MACCTL_KEEP_CTL;
1924 if (modparam_mon_keep_bad)
1925 ctl |= BCM43xx_MACCTL_KEEP_BAD;
1926 if (modparam_mon_keep_badplcp)
1927 ctl |= BCM43xx_MACCTL_KEEP_BADPLCP;
1928 }
1929 if (wl->promisc)
1930 ctl |= BCM43xx_MACCTL_PROMISC;
1931
1932 bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, ctl);
1933
1934 cfp_pretbtt = 2;
1935 if ((ctl & BCM43xx_MACCTL_INFRA) &&
1936 !(ctl & BCM43xx_MACCTL_AP)) {
1937 if (dev->dev->bus->chip_id == 0x4306 &&
1938 dev->dev->bus->chip_rev == 3)
1939 cfp_pretbtt = 100;
1940 else
1941 cfp_pretbtt = 50;
1942 }
1943 bcm43xx_write16(dev, 0x612, cfp_pretbtt);
1944 }
1945
1946 static void bcm43xx_rate_memory_write(struct bcm43xx_wldev *dev,
1947 u16 rate,
1948 int is_ofdm)
1949 {
1950 u16 offset;
1951
1952 if (is_ofdm) {
1953 offset = 0x480;
1954 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
1955 } else {
1956 offset = 0x4C0;
1957 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
1958 }
1959 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, offset + 0x20,
1960 bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, offset));
1961 }
1962
1963 static void bcm43xx_rate_memory_init(struct bcm43xx_wldev *dev)
1964 {
1965 switch (dev->phy.type) {
1966 case BCM43xx_PHYTYPE_A:
1967 case BCM43xx_PHYTYPE_G:
1968 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_6MB, 1);
1969 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_12MB, 1);
1970 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_18MB, 1);
1971 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_24MB, 1);
1972 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_36MB, 1);
1973 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_48MB, 1);
1974 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_54MB, 1);
1975 if (dev->phy.type == BCM43xx_PHYTYPE_A)
1976 break;
1977 /* fallthrough */
1978 case BCM43xx_PHYTYPE_B:
1979 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_1MB, 0);
1980 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_2MB, 0);
1981 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_5MB, 0);
1982 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_11MB, 0);
1983 break;
1984 default:
1985 assert(0);
1986 }
1987 }
1988
1989 /* Set the TX-Antenna for management frames sent by firmware. */
1990 static void bcm43xx_mgmtframe_txantenna(struct bcm43xx_wldev *dev,
1991 int antenna)
1992 {
1993 u16 ant = 0;
1994 u16 tmp;
1995
1996 switch (antenna) {
1997 case BCM43xx_ANTENNA0:
1998 ant |= BCM43xx_TX4_PHY_ANT0;
1999 break;
2000 case BCM43xx_ANTENNA1:
2001 ant |= BCM43xx_TX4_PHY_ANT1;
2002 break;
2003 case BCM43xx_ANTENNA_AUTO:
2004 ant |= BCM43xx_TX4_PHY_ANTLAST;
2005 break;
2006 default:
2007 assert(0);
2008 }
2009
2010 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2011
2012 /* For Beacons */
2013 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2014 BCM43xx_SHM_SH_BEACPHYCTL);
2015 tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
2016 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
2017 BCM43xx_SHM_SH_BEACPHYCTL, tmp);
2018 /* For ACK/CTS */
2019 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2020 BCM43xx_SHM_SH_ACKCTSPHYCTL);
2021 tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
2022 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
2023 BCM43xx_SHM_SH_ACKCTSPHYCTL, tmp);
2024 /* For Probe Resposes */
2025 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2026 BCM43xx_SHM_SH_PRPHYCTL);
2027 tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
2028 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
2029 BCM43xx_SHM_SH_PRPHYCTL, tmp);
2030 }
2031
2032 /* This is the opposite of bcm43xx_chip_init() */
2033 static void bcm43xx_chip_exit(struct bcm43xx_wldev *dev)
2034 {
2035 bcm43xx_radio_turn_off(dev);
2036 if (!modparam_noleds)
2037 bcm43xx_leds_exit(dev);
2038 bcm43xx_gpio_cleanup(dev);
2039 /* firmware is released later */
2040 }
2041
2042 /* Initialize the chip
2043 * http://bcm-specs.sipsolutions.net/ChipInit
2044 */
2045 static int bcm43xx_chip_init(struct bcm43xx_wldev *dev)
2046 {
2047 struct bcm43xx_phy *phy = &dev->phy;
2048 int err, tmp;
2049 u32 value32;
2050 u16 value16;
2051
2052 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
2053 BCM43xx_SBF_CORE_READY
2054 | BCM43xx_SBF_400);
2055
2056 err = bcm43xx_request_firmware(dev);
2057 if (err)
2058 goto out;
2059 err = bcm43xx_upload_microcode(dev);
2060 if (err)
2061 goto out; /* firmware is released later */
2062
2063 err = bcm43xx_gpio_init(dev);
2064 if (err)
2065 goto out; /* firmware is released later */
2066 err = bcm43xx_upload_initvals(dev);
2067 if (err)
2068 goto err_gpio_cleanup;
2069 bcm43xx_radio_turn_on(dev);
2070 dev->radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
2071 dprintk(KERN_INFO PFX "Radio %s by hardware\n",
2072 (dev->radio_hw_enable == 0) ? "disabled" : "enabled");
2073
2074 bcm43xx_write16(dev, 0x03E6, 0x0000);
2075 err = bcm43xx_phy_init(dev);
2076 if (err)
2077 goto err_radio_off;
2078
2079 /* Select initial Interference Mitigation. */
2080 tmp = phy->interfmode;
2081 phy->interfmode = BCM43xx_INTERFMODE_NONE;
2082 bcm43xx_radio_set_interference_mitigation(dev, tmp);
2083
2084 bcm43xx_set_rx_antenna(dev, BCM43xx_ANTENNA_DEFAULT);
2085 bcm43xx_mgmtframe_txantenna(dev, BCM43xx_ANTENNA_DEFAULT);
2086
2087 if (phy->type == BCM43xx_PHYTYPE_B) {
2088 value16 = bcm43xx_read16(dev, 0x005E);
2089 value16 |= 0x0004;
2090 bcm43xx_write16(dev, 0x005E, value16);
2091 }
2092 bcm43xx_write32(dev, 0x0100, 0x01000000);
2093 if (dev->dev->id.revision < 5)
2094 bcm43xx_write32(dev, 0x010C, 0x01000000);
2095
2096 value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2097 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2098 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2099 value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2100 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2101 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2102
2103 value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2104 value32 |= 0x100000;
2105 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2106
2107 if (bcm43xx_using_pio(dev)) {
2108 bcm43xx_write32(dev, 0x0210, 0x00000100);
2109 bcm43xx_write32(dev, 0x0230, 0x00000100);
2110 bcm43xx_write32(dev, 0x0250, 0x00000100);
2111 bcm43xx_write32(dev, 0x0270, 0x00000100);
2112 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2113 }
2114
2115 /* Probe Response Timeout value */
2116 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2117 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2118
2119 /* Initially set the wireless operation mode. */
2120 bcm43xx_adjust_opmode(dev);
2121
2122 if (dev->dev->id.revision < 3) {
2123 bcm43xx_write16(dev, 0x060E, 0x0000);
2124 bcm43xx_write16(dev, 0x0610, 0x8000);
2125 bcm43xx_write16(dev, 0x0604, 0x0000);
2126 bcm43xx_write16(dev, 0x0606, 0x0200);
2127 } else {
2128 bcm43xx_write32(dev, 0x0188, 0x80000000);
2129 bcm43xx_write32(dev, 0x018C, 0x02000000);
2130 }
2131 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2132 bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2133 bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2134 bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2135 bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2136 bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2137 bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2138
2139 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2140 value32 |= 0x00100000;
2141 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2142
2143 bcm43xx_write16(dev, BCM43xx_MMIO_POWERUP_DELAY,
2144 dev->dev->bus->chipco.fast_pwrup_delay);
2145
2146 assert(err == 0);
2147 dprintk(KERN_INFO PFX "Chip initialized\n");
2148 out:
2149 return err;
2150
2151 err_radio_off:
2152 bcm43xx_radio_turn_off(dev);
2153 err_gpio_cleanup:
2154 bcm43xx_gpio_cleanup(dev);
2155 goto out;
2156 }
2157
2158 static void bcm43xx_periodic_every120sec(struct bcm43xx_wldev *dev)
2159 {
2160 struct bcm43xx_phy *phy = &dev->phy;
2161
2162 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
2163 return;
2164
2165 bcm43xx_mac_suspend(dev);
2166 bcm43xx_lo_g_measure(dev);
2167 bcm43xx_mac_enable(dev);
2168 }
2169
2170 static void bcm43xx_periodic_every60sec(struct bcm43xx_wldev *dev)
2171 {
2172 bcm43xx_lo_g_ctl_mark_all_unused(dev);
2173 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
2174 bcm43xx_mac_suspend(dev);
2175 bcm43xx_calc_nrssi_slope(dev);
2176 bcm43xx_mac_enable(dev);
2177 }
2178 }
2179
2180 static void bcm43xx_periodic_every30sec(struct bcm43xx_wldev *dev)
2181 {
2182 /* Update device statistics. */
2183 bcm43xx_calculate_link_quality(dev);
2184 }
2185
2186 static void bcm43xx_periodic_every15sec(struct bcm43xx_wldev *dev)
2187 {
2188 struct bcm43xx_phy *phy = &dev->phy;
2189
2190 if (phy->type == BCM43xx_PHYTYPE_G) {
2191 //TODO: update_aci_moving_average
2192 if (phy->aci_enable && phy->aci_wlan_automatic) {
2193 bcm43xx_mac_suspend(dev);
2194 if (!phy->aci_enable && 1 /*TODO: not scanning? */) {
2195 if (0 /*TODO: bunch of conditions*/) {
2196 bcm43xx_radio_set_interference_mitigation(dev,
2197 BCM43xx_INTERFMODE_MANUALWLAN);
2198 }
2199 } else if (1/*TODO*/) {
2200 /*
2201 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(dev))) {
2202 bcm43xx_radio_set_interference_mitigation(dev,
2203 BCM43xx_INTERFMODE_NONE);
2204 }
2205 */
2206 }
2207 bcm43xx_mac_enable(dev);
2208 } else if (phy->interfmode == BCM43xx_INTERFMODE_NONWLAN &&
2209 phy->rev == 1) {
2210 //TODO: implement rev1 workaround
2211 }
2212 }
2213 bcm43xx_phy_xmitpower(dev); //FIXME: unless scanning?
2214 //TODO for APHY (temperature?)
2215 }
2216
2217 static void bcm43xx_periodic_every1sec(struct bcm43xx_wldev *dev)
2218 {
2219 int radio_hw_enable;
2220
2221 /* check if radio hardware enabled status changed */
2222 radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
2223 if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
2224 dev->radio_hw_enable = radio_hw_enable;
2225 dprintk(KERN_INFO PFX "Radio hardware status changed to %s\n",
2226 (radio_hw_enable == 0) ? "disabled" : "enabled");
2227 bcm43xx_leds_update(dev, 0);
2228 }
2229 }
2230
2231 static void do_periodic_work(struct bcm43xx_wldev *dev)
2232 {
2233 unsigned int state;
2234
2235 state = dev->periodic_state;
2236 if (state % 120 == 0)
2237 bcm43xx_periodic_every120sec(dev);
2238 if (state % 60 == 0)
2239 bcm43xx_periodic_every60sec(dev);
2240 if (state % 30 == 0)
2241 bcm43xx_periodic_every30sec(dev);
2242 if (state % 15 == 0)
2243 bcm43xx_periodic_every15sec(dev);
2244 bcm43xx_periodic_every1sec(dev);
2245 }
2246
2247 /* Estimate a "Badness" value based on the periodic work
2248 * state-machine state. "Badness" is worse (bigger), if the
2249 * periodic work will take longer.
2250 */
2251 static int estimate_periodic_work_badness(unsigned int state)
2252 {
2253 int badness = 0;
2254
2255 if (state % 120 == 0) /* every 120 sec */
2256 badness += 10;
2257 if (state % 60 == 0) /* every 60 sec */
2258 badness += 5;
2259 if (state % 30 == 0) /* every 30 sec */
2260 badness += 1;
2261 if (state % 15 == 0) /* every 15 sec */
2262 badness += 1;
2263
2264 #define BADNESS_LIMIT 4
2265 return badness;
2266 }
2267
2268 static void bcm43xx_periodic_work_handler(struct work_struct *work)
2269 {
2270 struct bcm43xx_wldev *dev =
2271 container_of(work, struct bcm43xx_wldev, periodic_work.work);
2272 unsigned long flags, delay;
2273 u32 savedirqs = 0;
2274 int badness;
2275
2276 mutex_lock(&dev->wl->mutex);
2277
2278 if (unlikely(bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED))
2279 goto out;
2280 if (unlikely(!dev->started))
2281 goto out;
2282 if (bcm43xx_debug(dev, BCM43xx_DBG_PWORK_STOP))
2283 goto out_requeue;
2284
2285 badness = estimate_periodic_work_badness(dev->periodic_state);
2286 if (badness > BADNESS_LIMIT) {
2287 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2288 /* Suspend TX as we don't want to transmit packets while
2289 * we recalibrate the hardware. */
2290 bcm43xx_tx_suspend(dev);
2291 savedirqs = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
2292 /* Periodic work will take a long time, so we want it to
2293 * be preemtible and release the spinlock. */
2294 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2295 bcm43xx_synchronize_irq(dev);
2296
2297 do_periodic_work(dev);
2298
2299 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2300 bcm43xx_interrupt_enable(dev, savedirqs);
2301 bcm43xx_tx_resume(dev);
2302 mmiowb();
2303 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2304 } else {
2305 /* Take the global driver lock. This will lock any operation. */
2306 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2307
2308 do_periodic_work(dev);
2309
2310 mmiowb();
2311 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2312 }
2313 dev->periodic_state++;
2314 out_requeue:
2315 if (bcm43xx_debug(dev, BCM43xx_DBG_PWORK_FAST))
2316 delay = msecs_to_jiffies(50);
2317 else
2318 delay = round_jiffies(HZ);
2319 queue_delayed_work(dev->wl->hw->workqueue,
2320 &dev->periodic_work, delay);
2321 out:
2322 mutex_unlock(&dev->wl->mutex);
2323 }
2324
2325 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_wldev *dev)
2326 {
2327 cancel_rearming_delayed_work(&dev->periodic_work);
2328 }
2329
2330 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_wldev *dev)
2331 {
2332 struct delayed_work *work = &dev->periodic_work;
2333
2334 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
2335 dev->periodic_state = 0;
2336 INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
2337 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2338 }
2339
2340 /* Validate access to the chip (SHM) */
2341 static int bcm43xx_validate_chipaccess(struct bcm43xx_wldev *dev)
2342 {
2343 u32 value;
2344 u32 shm_backup;
2345
2346 shm_backup = bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0);
2347 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0xAA5555AA);
2348 if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0xAA5555AA)
2349 goto error;
2350 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0x55AAAA55);
2351 if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0x55AAAA55)
2352 goto error;
2353 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, shm_backup);
2354
2355 value = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
2356 if ((value | BCM43xx_MACCTL_GMODE) !=
2357 (BCM43xx_MACCTL_GMODE | BCM43xx_MACCTL_IHR_ENABLED))
2358 goto error;
2359
2360 value = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
2361 if (value)
2362 goto error;
2363
2364 return 0;
2365 error:
2366 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2367 return -ENODEV;
2368 }
2369
2370 static void bcm43xx_security_init(struct bcm43xx_wldev *dev)
2371 {
2372 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2373 assert(dev->max_nr_keys <= ARRAY_SIZE(dev->key));
2374 dev->ktp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2375 BCM43xx_SHM_SH_KTP);
2376 /* KTP is a word address, but we address SHM bytewise.
2377 * So multiply by two.
2378 */
2379 dev->ktp *= 2;
2380 if (dev->dev->id.revision >= 5) {
2381 /* Number of RCMTA address slots */
2382 bcm43xx_write16(dev, BCM43xx_MMIO_RCMTA_COUNT,
2383 dev->max_nr_keys - 8);
2384 }
2385 bcm43xx_clear_keys(dev);
2386 }
2387
2388 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
2389 {
2390 struct bcm43xx_wl *wl = (struct bcm43xx_wl *)rng->priv;
2391 unsigned long flags;
2392
2393 /* Don't take wl->mutex here, as it could deadlock with
2394 * hwrng internal locking. It's not needed to take
2395 * wl->mutex here, anyway. */
2396
2397 spin_lock_irqsave(&wl->irq_lock, flags);
2398 *data = bcm43xx_read16(wl->current_dev, BCM43xx_MMIO_RNG);
2399 spin_unlock_irqrestore(&wl->irq_lock, flags);
2400
2401 return (sizeof(u16));
2402 }
2403
2404 static void bcm43xx_rng_exit(struct bcm43xx_wl *wl)
2405 {
2406 if (wl->rng_initialized)
2407 hwrng_unregister(&wl->rng);
2408 }
2409
2410 static int bcm43xx_rng_init(struct bcm43xx_wl *wl)
2411 {
2412 int err;
2413
2414 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2415 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2416 wl->rng.name = wl->rng_name;
2417 wl->rng.data_read = bcm43xx_rng_read;
2418 wl->rng.priv = (unsigned long)wl;
2419 wl->rng_initialized = 1;
2420 err = hwrng_register(&wl->rng);
2421 if (err) {
2422 wl->rng_initialized = 0;
2423 printk(KERN_ERR PFX "Failed to register the random "
2424 "number generator (%d)\n", err);
2425 }
2426
2427 return err;
2428 }
2429
2430 static int bcm43xx_tx(struct ieee80211_hw *hw,
2431 struct sk_buff *skb,
2432 struct ieee80211_tx_control *ctl)
2433 {
2434 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2435 struct bcm43xx_wldev *dev = wl->current_dev;
2436 int err = -ENODEV;
2437 unsigned long flags;
2438
2439 /* DMA-TX is done without a global lock. */
2440 if (unlikely(!dev))
2441 goto out;
2442 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
2443 assert(dev->started);
2444 if (bcm43xx_using_pio(dev)) {
2445 spin_lock_irqsave(&wl->irq_lock, flags);
2446 err = bcm43xx_pio_tx(dev, skb, ctl);
2447 spin_unlock_irqrestore(&wl->irq_lock, flags);
2448 } else
2449 err = bcm43xx_dma_tx(dev, skb, ctl);
2450 out:
2451 if (unlikely(err))
2452 return NETDEV_TX_BUSY;
2453 return NETDEV_TX_OK;
2454 }
2455
2456 static int bcm43xx_conf_tx(struct ieee80211_hw *hw,
2457 int queue,
2458 const struct ieee80211_tx_queue_params *params)
2459 {
2460 return 0;
2461 }
2462
2463 static int bcm43xx_get_tx_stats(struct ieee80211_hw *hw,
2464 struct ieee80211_tx_queue_stats *stats)
2465 {
2466 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2467 struct bcm43xx_wldev *dev = wl->current_dev;
2468 unsigned long flags;
2469 int err = -ENODEV;
2470
2471 if (!dev)
2472 goto out;
2473 spin_lock_irqsave(&wl->irq_lock, flags);
2474 if (likely(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)) {
2475 if (bcm43xx_using_pio(dev))
2476 bcm43xx_pio_get_tx_stats(dev, stats);
2477 else
2478 bcm43xx_dma_get_tx_stats(dev, stats);
2479 err = 0;
2480 }
2481 spin_unlock_irqrestore(&wl->irq_lock, flags);
2482 out:
2483 return err;
2484 }
2485
2486 static int bcm43xx_get_stats(struct ieee80211_hw *hw,
2487 struct ieee80211_low_level_stats *stats)
2488 {
2489 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2490 unsigned long flags;
2491
2492 spin_lock_irqsave(&wl->irq_lock, flags);
2493 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2494 spin_unlock_irqrestore(&wl->irq_lock, flags);
2495
2496 return 0;
2497 }
2498
2499 static int bcm43xx_dev_reset(struct ieee80211_hw *hw)
2500 {
2501 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2502 struct bcm43xx_wldev *dev = wl->current_dev;
2503 unsigned long flags;
2504
2505 if (!dev)
2506 return -ENODEV;
2507 spin_lock_irqsave(&wl->irq_lock, flags);
2508 bcm43xx_controller_restart(dev, "Reset by ieee80211 subsystem");
2509 spin_unlock_irqrestore(&wl->irq_lock, flags);
2510
2511 return 0;
2512 }
2513
2514 static const char * phymode_to_string(unsigned int phymode)
2515 {
2516 switch (phymode) {
2517 case BCM43xx_PHYMODE_A:
2518 return "A";
2519 case BCM43xx_PHYMODE_B:
2520 return "B";
2521 case BCM43xx_PHYMODE_G:
2522 return "G";
2523 default:
2524 assert(0);
2525 }
2526 return "";
2527 }
2528
2529 static int find_wldev_for_phymode(struct bcm43xx_wl *wl,
2530 unsigned int phymode,
2531 struct bcm43xx_wldev **dev,
2532 int *gmode)
2533 {
2534 struct bcm43xx_wldev *d;
2535
2536 list_for_each_entry(d, &wl->devlist, list) {
2537 if (d->phy.possible_phymodes & phymode) {
2538 /* Ok, this device supports the PHY-mode.
2539 * Now figure out how the gmode bit has to be
2540 * set to support it. */
2541 if (phymode == BCM43xx_PHYMODE_A)
2542 *gmode = 0;
2543 else
2544 *gmode = 1;
2545 *dev = d;
2546
2547 return 0;
2548 }
2549 }
2550
2551 return -ESRCH;
2552 }
2553
2554 static void bcm43xx_put_phy_into_reset(struct bcm43xx_wldev *dev)
2555 {
2556 struct ssb_device *sdev = dev->dev;
2557 u32 tmslow;
2558
2559 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2560 tmslow &= ~BCM43xx_TMSLOW_GMODE;
2561 tmslow |= BCM43xx_TMSLOW_PHYRESET;
2562 tmslow |= SSB_TMSLOW_FGC;
2563 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2564 msleep(1);
2565
2566 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2567 tmslow &= ~SSB_TMSLOW_FGC;
2568 tmslow |= BCM43xx_TMSLOW_PHYRESET;
2569 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2570 msleep(1);
2571 }
2572
2573 static int bcm43xx_switch_phymode(struct bcm43xx_wl *wl,
2574 unsigned int new_mode)
2575 {
2576 struct bcm43xx_wldev *up_dev;
2577 struct bcm43xx_wldev *down_dev;
2578 int err;
2579 int gmode = -1;
2580 int old_was_started = 0;
2581 int old_was_inited = 0;
2582
2583 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2584 if (err) {
2585 printk(KERN_INFO PFX "Could not find a device for %s-PHY mode\n",
2586 phymode_to_string(new_mode));
2587 return err;
2588 }
2589 assert(gmode == 0 || gmode == 1);
2590 if ((up_dev == wl->current_dev) &&
2591 (wl->current_dev->phy.gmode == gmode)) {
2592 /* This device is already running. */
2593 return 0;
2594 }
2595 dprintk(KERN_INFO PFX "Reconfiguring PHYmode to %s-PHY\n",
2596 phymode_to_string(new_mode));
2597 down_dev = wl->current_dev;
2598
2599 /* Shutdown the currently running core. */
2600 if (down_dev->started) {
2601 old_was_started = 1;
2602 bcm43xx_wireless_core_stop(down_dev);
2603 }
2604 if (bcm43xx_status(down_dev) == BCM43xx_STAT_INITIALIZED) {
2605 old_was_inited = 1;
2606 bcm43xx_wireless_core_exit(down_dev);
2607 }
2608
2609 if (down_dev != up_dev) {
2610 /* We switch to a different core, so we put PHY into
2611 * RESET on the old core. */
2612 bcm43xx_put_phy_into_reset(down_dev);
2613 }
2614
2615 /* Now start the new core. */
2616 up_dev->phy.gmode = gmode;
2617 if (old_was_inited) {
2618 err = bcm43xx_wireless_core_init(up_dev);
2619 if (err) {
2620 printk(KERN_INFO PFX "Fatal: Could not initialize device for "
2621 "new selected %s-PHY mode\n",
2622 phymode_to_string(new_mode));
2623 return err;
2624 }
2625 }
2626 if (old_was_started) {
2627 assert(old_was_inited);
2628 err = bcm43xx_wireless_core_start(up_dev);
2629 if (err) {
2630 printk(KERN_INFO PFX "Fatal: Coult not start device for "
2631 "new selected %s-PHY mode\n",
2632 phymode_to_string(new_mode));
2633 bcm43xx_wireless_core_exit(up_dev);
2634 return err;
2635 }
2636 }
2637
2638 wl->current_dev = up_dev;
2639
2640 return 0;
2641 }
2642
2643 static int bcm43xx_antenna_from_ieee80211(u8 antenna)
2644 {
2645 switch (antenna) {
2646 case 0: /* default/diversity */
2647 return BCM43xx_ANTENNA_DEFAULT;
2648 case 1: /* Antenna 0 */
2649 return BCM43xx_ANTENNA0;
2650 case 2: /* Antenna 1 */
2651 return BCM43xx_ANTENNA1;
2652 default:
2653 return BCM43xx_ANTENNA_DEFAULT;
2654 }
2655 }
2656
2657 static int bcm43xx_dev_config(struct ieee80211_hw *hw,
2658 struct ieee80211_conf *conf)
2659 {
2660 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2661 struct bcm43xx_wldev *dev;
2662 struct bcm43xx_phy *phy;
2663 unsigned long flags;
2664 unsigned int new_phymode = 0xFFFF;
2665 int antenna_tx;
2666 int antenna_rx;
2667 int err = 0;
2668 u32 savedirqs;
2669
2670 antenna_tx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_tx);
2671 antenna_rx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_rx);
2672
2673 mutex_lock(&wl->mutex);
2674
2675 /* Switch the PHY mode (if necessary). */
2676 switch (conf->phymode) {
2677 case MODE_IEEE80211A:
2678 new_phymode = BCM43xx_PHYMODE_A;
2679 break;
2680 case MODE_IEEE80211B:
2681 new_phymode = BCM43xx_PHYMODE_B;
2682 break;
2683 case MODE_IEEE80211G:
2684 new_phymode = BCM43xx_PHYMODE_G;
2685 break;
2686 default:
2687 assert(0);
2688 }
2689 err = bcm43xx_switch_phymode(wl, new_phymode);
2690 if (err)
2691 goto out_unlock_mutex;
2692 dev = wl->current_dev;
2693 phy = &dev->phy;
2694
2695 /* Disable IRQs while reconfiguring the device.
2696 * This makes it possible to drop the spinlock throughout
2697 * the reconfiguration process. */
2698 spin_lock_irqsave(&wl->irq_lock, flags);
2699 if ((bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) ||
2700 !dev->started) {
2701 spin_unlock_irqrestore(&wl->irq_lock, flags);
2702 goto out_unlock_mutex;
2703 }
2704 savedirqs = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
2705 spin_unlock_irqrestore(&wl->irq_lock, flags);
2706 bcm43xx_synchronize_irq(dev);
2707
2708 /* Switch to the requested channel.
2709 * The firmware takes care of races with the TX handler. */
2710 if (conf->channel_val != phy->channel)
2711 bcm43xx_radio_selectchannel(dev, conf->channel_val, 0);
2712
2713 /* Enable/Disable ShortSlot timing. */
2714 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != dev->short_slot) {
2715 assert(phy->type == BCM43xx_PHYTYPE_G);
2716 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2717 bcm43xx_short_slot_timing_enable(dev);
2718 else
2719 bcm43xx_short_slot_timing_disable(dev);
2720 }
2721
2722 /* Adjust the desired TX power level. */
2723 if (conf->power_level != 0) {
2724 if (conf->power_level != phy->power_level) {
2725 phy->power_level = conf->power_level;
2726 bcm43xx_phy_xmitpower(dev);
2727 }
2728 }
2729
2730 /* Hide/Show the SSID (AP mode only). */
2731 if (conf->flags & IEEE80211_CONF_SSID_HIDDEN) {
2732 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
2733 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
2734 | BCM43xx_SBF_NO_SSID_BCAST);
2735 } else {
2736 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
2737 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
2738 & ~BCM43xx_SBF_NO_SSID_BCAST);
2739 }
2740
2741 /* Antennas for RX and management frame TX. */
2742 bcm43xx_mgmtframe_txantenna(dev, antenna_tx);
2743 bcm43xx_set_rx_antenna(dev, antenna_rx);
2744
2745 /* Update templates for AP mode. */
2746 if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP))
2747 bcm43xx_set_beacon_int(dev, conf->beacon_int);
2748
2749
2750 spin_lock_irqsave(&wl->irq_lock, flags);
2751 bcm43xx_interrupt_enable(dev, savedirqs);
2752 mmiowb();
2753 spin_unlock_irqrestore(&wl->irq_lock, flags);
2754 out_unlock_mutex:
2755 mutex_unlock(&wl->mutex);
2756
2757 return err;
2758 }
2759
2760 static int bcm43xx_dev_set_key(struct ieee80211_hw *hw,
2761 set_key_cmd cmd,
2762 u8 *addr,
2763 struct ieee80211_key_conf *key,
2764 int aid)
2765 {
2766 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2767 struct bcm43xx_wldev *dev = wl->current_dev;
2768 unsigned long flags;
2769 u8 algorithm;
2770 u8 index;
2771 int err = -EINVAL;
2772
2773 if (!dev)
2774 return -ENODEV;
2775 switch (key->alg) {
2776 case ALG_NONE:
2777 case ALG_NULL:
2778 algorithm = BCM43xx_SEC_ALGO_NONE;
2779 break;
2780 case ALG_WEP:
2781 if (key->keylen == 5)
2782 algorithm = BCM43xx_SEC_ALGO_WEP40;
2783 else
2784 algorithm = BCM43xx_SEC_ALGO_WEP104;
2785 break;
2786 case ALG_TKIP:
2787 algorithm = BCM43xx_SEC_ALGO_TKIP;
2788 break;
2789 case ALG_CCMP:
2790 algorithm = BCM43xx_SEC_ALGO_AES;
2791 break;
2792 default:
2793 assert(0);
2794 goto out;
2795 }
2796
2797 index = (u8)(key->keyidx);
2798 if (index > 3)
2799 goto out;
2800
2801 mutex_lock(&wl->mutex);
2802 spin_lock_irqsave(&wl->irq_lock, flags);
2803
2804 if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
2805 err = -ENODEV;
2806 goto out_unlock;
2807 }
2808
2809 switch (cmd) {
2810 case SET_KEY:
2811 key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT;
2812
2813 if (algorithm == BCM43xx_SEC_ALGO_TKIP) {
2814 /* FIXME: No TKIP hardware encryption for now. */
2815 key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
2816 }
2817
2818 if (is_broadcast_ether_addr(addr)) {
2819 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2820 err = bcm43xx_key_write(dev, index, algorithm,
2821 key->key, key->keylen,
2822 NULL, key);
2823 } else {
2824 err = bcm43xx_key_write(dev, -1, algorithm,
2825 key->key, key->keylen,
2826 addr, key);
2827 }
2828 if (err) {
2829 key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
2830 goto out_unlock;
2831 }
2832 dev->key[key->hw_key_idx].enabled = 1;
2833
2834 if (algorithm == BCM43xx_SEC_ALGO_WEP40 ||
2835 algorithm == BCM43xx_SEC_ALGO_WEP104) {
2836 bcm43xx_hf_write(dev,
2837 bcm43xx_hf_read(dev) |
2838 BCM43xx_HF_USEDEFKEYS);
2839 } else {
2840 bcm43xx_hf_write(dev,
2841 bcm43xx_hf_read(dev) &
2842 ~BCM43xx_HF_USEDEFKEYS);
2843 }
2844 break;
2845 case DISABLE_KEY: {
2846 static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
2847
2848 algorithm = BCM43xx_SEC_ALGO_NONE;
2849 if (is_broadcast_ether_addr(addr)) {
2850 err = bcm43xx_key_write(dev, index, algorithm,
2851 zero, BCM43xx_SEC_KEYSIZE,
2852 NULL, key);
2853 } else {
2854 err = bcm43xx_key_write(dev, -1, algorithm,
2855 zero, BCM43xx_SEC_KEYSIZE,
2856 addr, key);
2857 }
2858 dev->key[key->hw_key_idx].enabled = 0;
2859 break;
2860 }
2861 case REMOVE_ALL_KEYS:
2862 bcm43xx_clear_keys(dev);
2863 err = 0;
2864 break;
2865 default:
2866 assert(0);
2867 }
2868 out_unlock:
2869 spin_unlock_irqrestore(&wl->irq_lock, flags);
2870 mutex_unlock(&wl->mutex);
2871 out:
2872 if (!err) {
2873 dprintk(KERN_DEBUG PFX "Using %s based encryption for keyidx: %d, "
2874 "mac: " MAC_FMT "\n",
2875 (key->flags & IEEE80211_KEY_FORCE_SW_ENCRYPT) ?
2876 "software" : "hardware",
2877 key->keyidx, MAC_ARG(addr));
2878 }
2879 return err;
2880 }
2881
2882 static void bcm43xx_set_multicast_list(struct ieee80211_hw *hw,
2883 unsigned short netflags,
2884 int mc_count)
2885 {
2886 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2887 struct bcm43xx_wldev *dev = wl->current_dev;
2888 unsigned long flags;
2889
2890 if (!dev)
2891 return;
2892 spin_lock_irqsave(&wl->irq_lock, flags);
2893 if (wl->promisc != !!(netflags & IFF_PROMISC)) {
2894 wl->promisc = !!(netflags & IFF_PROMISC);
2895 if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)
2896 bcm43xx_adjust_opmode(dev);
2897 }
2898 spin_unlock_irqrestore(&wl->irq_lock, flags);
2899 }
2900
2901 static int bcm43xx_config_interface(struct ieee80211_hw *hw,
2902 int if_id,
2903 struct ieee80211_if_conf *conf)
2904 {
2905 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2906 struct bcm43xx_wldev *dev = wl->current_dev;
2907 unsigned long flags;
2908
2909 if (!dev)
2910 return -ENODEV;
2911 mutex_lock(&wl->mutex);
2912 spin_lock_irqsave(&wl->irq_lock, flags);
2913 if (conf->type != IEEE80211_IF_TYPE_MNTR) {
2914 assert(wl->if_id == if_id);
2915 wl->bssid = conf->bssid;
2916 if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2917 assert(conf->type == IEEE80211_IF_TYPE_AP);
2918 bcm43xx_set_ssid(dev, conf->ssid, conf->ssid_len);
2919 if (conf->beacon)
2920 bcm43xx_refresh_templates(dev, conf->beacon);
2921 }
2922 bcm43xx_write_mac_bssid_templates(dev);
2923 }
2924 spin_unlock_irqrestore(&wl->irq_lock, flags);
2925 mutex_unlock(&wl->mutex);
2926
2927 return 0;
2928 }
2929
2930 /* Locking: wl->mutex */
2931 static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev)
2932 {
2933 struct bcm43xx_wl *wl = dev->wl;
2934 unsigned long flags;
2935
2936 if (!dev->started)
2937 return;
2938 dev->started = 0;
2939
2940 mutex_unlock(&wl->mutex);
2941 /* Must unlock as it would otherwise deadlock. No races here. */
2942 bcm43xx_periodic_tasks_delete(dev);
2943 flush_workqueue(dev->wl->hw->workqueue);
2944 mutex_lock(&wl->mutex);
2945
2946 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2947
2948 /* Disable and sync interrupts. */
2949 spin_lock_irqsave(&wl->irq_lock, flags);
2950 dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
2951 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
2952 spin_unlock_irqrestore(&wl->irq_lock, flags);
2953 bcm43xx_synchronize_irq(dev);
2954
2955 bcm43xx_mac_suspend(dev);
2956 free_irq(dev->dev->irq, dev);
2957 dprintk(KERN_INFO PFX "Wireless interface stopped\n");
2958 }
2959
2960 /* Locking: wl->mutex */
2961 static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev)
2962 {
2963 struct bcm43xx_wl *wl = dev->wl;
2964 int err;
2965
2966 assert(!dev->started);
2967
2968 drain_txstatus_queue(dev);
2969 err = request_irq(dev->dev->irq, bcm43xx_interrupt_handler,
2970 IRQF_SHARED, KBUILD_MODNAME, dev);
2971 if (err) {
2972 printk(KERN_ERR PFX "Cannot request IRQ-%d\n",
2973 dev->dev->irq);
2974 goto out;
2975 }
2976 dev->started = 1;
2977 bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
2978 bcm43xx_mac_enable(dev);
2979
2980 ieee80211_start_queues(wl->hw);
2981 bcm43xx_periodic_tasks_setup(dev);
2982 dprintk(KERN_INFO PFX "Wireless interface started\n");
2983 out:
2984 return err;
2985 }
2986
2987 /* Get PHY and RADIO versioning numbers */
2988 static int bcm43xx_phy_versioning(struct bcm43xx_wldev *dev)
2989 {
2990 struct bcm43xx_phy *phy = &dev->phy;
2991 u32 tmp;
2992 u8 analog_type;
2993 u8 phy_type;
2994 u8 phy_rev;
2995 u16 radio_manuf;
2996 u16 radio_ver;
2997 u16 radio_rev;
2998 int unsupported = 0;
2999
3000 /* Get PHY versioning */
3001 tmp = bcm43xx_read16(dev, BCM43xx_MMIO_PHY_VER);
3002 analog_type = (tmp & BCM43xx_PHYVER_ANALOG) >> BCM43xx_PHYVER_ANALOG_SHIFT;
3003 phy_type = (tmp & BCM43xx_PHYVER_TYPE) >> BCM43xx_PHYVER_TYPE_SHIFT;
3004 phy_rev = (tmp & BCM43xx_PHYVER_VERSION);
3005 switch (phy_type) {
3006 case BCM43xx_PHYTYPE_A:
3007 if (phy_rev >= 4)
3008 unsupported = 1;
3009 break;
3010 case BCM43xx_PHYTYPE_B:
3011 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3012 unsupported = 1;
3013 break;
3014 case BCM43xx_PHYTYPE_G:
3015 if (phy_rev > 8)
3016 unsupported = 1;
3017 break;
3018 default:
3019 unsupported = 1;
3020 };
3021 if (unsupported) {
3022 printk(KERN_ERR PFX "FOUND UNSUPPORTED PHY "
3023 "(Analog %u, Type %u, Revision %u)\n",
3024 analog_type, phy_type, phy_rev);
3025 return -EOPNOTSUPP;
3026 }
3027 dprintk(KERN_INFO PFX "Found PHY: Analog %u, Type %u, Revision %u\n",
3028 analog_type, phy_type, phy_rev);
3029
3030
3031 /* Get RADIO versioning */
3032 if (dev->dev->bus->chip_id == 0x4317) {
3033 if (dev->dev->bus->chip_rev == 0)
3034 tmp = 0x3205017F;
3035 else if (dev->dev->bus->chip_rev == 1)
3036 tmp = 0x4205017F;
3037 else
3038 tmp = 0x5205017F;
3039 } else {
3040 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL,
3041 BCM43xx_RADIOCTL_ID);
3042 tmp = bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_HIGH);
3043 tmp <<= 16;
3044 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL,
3045 BCM43xx_RADIOCTL_ID);
3046 tmp |= bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_LOW);
3047 }
3048 radio_manuf = (tmp & 0x00000FFF);
3049 radio_ver = (tmp & 0x0FFFF000) >> 12;
3050 radio_rev = (tmp & 0xF0000000) >> 28;
3051 switch (phy_type) {
3052 case BCM43xx_PHYTYPE_A:
3053 if (radio_ver != 0x2060)
3054 unsupported = 1;
3055 if (radio_rev != 1)
3056 unsupported = 1;
3057 if (radio_manuf != 0x17F)
3058 unsupported = 1;
3059 break;
3060 case BCM43xx_PHYTYPE_B:
3061 if ((radio_ver & 0xFFF0) != 0x2050)
3062 unsupported = 1;
3063 break;
3064 case BCM43xx_PHYTYPE_G:
3065 if (radio_ver != 0x2050)
3066 unsupported = 1;
3067 break;
3068 default:
3069 assert(0);
3070 }
3071 if (unsupported) {
3072 printk(KERN_ERR PFX "FOUND UNSUPPORTED RADIO "
3073 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3074 radio_manuf, radio_ver, radio_rev);
3075 return -EOPNOTSUPP;
3076 }
3077 dprintk(KERN_INFO PFX "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3078 radio_manuf, radio_ver, radio_rev);
3079
3080
3081 phy->radio_manuf = radio_manuf;
3082 phy->radio_ver = radio_ver;
3083 phy->radio_rev = radio_rev;
3084
3085 phy->analog = analog_type;
3086 phy->type = phy_type;
3087 phy->rev = phy_rev;
3088
3089 return 0;
3090 }
3091
3092 static void setup_struct_phy_for_init(struct bcm43xx_wldev *dev,
3093 struct bcm43xx_phy *phy)
3094 {
3095 struct bcm43xx_txpower_lo_control *lo;
3096 int i;
3097
3098 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3099 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3100
3101 /* Flags */
3102 phy->locked = 0;
3103
3104 phy->aci_enable = 0;
3105 phy->aci_wlan_automatic = 0;
3106 phy->aci_hw_rssi = 0;
3107
3108 lo = phy->lo_control;
3109 if (lo) {
3110 memset(lo, 0, sizeof(*(phy->lo_control)));
3111 lo->rebuild = 1;
3112 lo->tx_bias = 0xFF;
3113 }
3114 phy->max_lb_gain = 0;
3115 phy->trsw_rx_gain = 0;
3116 phy->txpwr_offset = 0;
3117
3118 /* NRSSI */
3119 phy->nrssislope = 0;
3120 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3121 phy->nrssi[i] = -1000;
3122 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3123 phy->nrssi_lt[i] = i;
3124
3125 phy->lofcal = 0xFFFF;
3126 phy->initval = 0xFFFF;
3127
3128 spin_lock_init(&phy->lock);
3129 phy->interfmode = BCM43xx_INTERFMODE_NONE;
3130 phy->channel = 0xFF;
3131 }
3132
3133 static void setup_struct_wldev_for_init(struct bcm43xx_wldev *dev)
3134 {
3135 /* Flags */
3136 dev->reg124_set_0x4 = 0;
3137
3138 /* Stats */
3139 memset(&dev->stats, 0, sizeof(dev->stats));
3140
3141 setup_struct_phy_for_init(dev, &dev->phy);
3142
3143 /* IRQ related flags */
3144 dev->irq_reason = 0;
3145 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3146 dev->irq_savedstate = BCM43xx_IRQ_MASKTEMPLATE;
3147
3148 dev->mac_suspended = 1;
3149
3150 /* Noise calculation context */
3151 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3152 }
3153
3154 static void bcm43xx_bluetooth_coext_enable(struct bcm43xx_wldev *dev)
3155 {
3156 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3157 u32 hf;
3158
3159 if (!(sprom->r1.boardflags_lo & BCM43xx_BFL_BTCOEXIST))
3160 return;
3161 if (dev->phy.type != BCM43xx_PHYTYPE_B && !dev->phy.gmode)
3162 return;
3163
3164 hf = bcm43xx_hf_read(dev);
3165 if (sprom->r1.boardflags_lo & BCM43xx_BFL_BTCMOD)
3166 hf |= BCM43xx_HF_BTCOEXALT;
3167 else
3168 hf |= BCM43xx_HF_BTCOEX;
3169 bcm43xx_hf_write(dev, hf);
3170 //TODO
3171 }
3172
3173 static void bcm43xx_bluetooth_coext_disable(struct bcm43xx_wldev *dev)
3174 {//TODO
3175 }
3176
3177 static void bcm43xx_imcfglo_timeouts_workaround(struct bcm43xx_wldev *dev)
3178 {
3179 #ifdef CONFIG_SSB_DRIVER_PCICORE
3180 struct ssb_bus *bus = dev->dev->bus;
3181 u32 tmp;
3182
3183 if (bus->pcicore.dev &&
3184 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3185 bus->pcicore.dev->id.revision <= 5) {
3186 /* IMCFGLO timeouts workaround. */
3187 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3188 tmp &= ~SSB_IMCFGLO_REQTO;
3189 tmp &= ~SSB_IMCFGLO_SERTO;
3190 switch (bus->bustype) {
3191 case SSB_BUSTYPE_PCI:
3192 case SSB_BUSTYPE_PCMCIA:
3193 tmp |= 0x32;
3194 break;
3195 case SSB_BUSTYPE_SSB:
3196 tmp |= 0x53;
3197 break;
3198 }
3199 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3200 }
3201 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3202 }
3203
3204 /* Shutdown a wireless core */
3205 static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev)
3206 {
3207 struct bcm43xx_phy *phy = &dev->phy;
3208
3209 if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
3210 return;
3211
3212 bcm43xx_rng_exit(dev->wl);
3213 bcm43xx_pio_free(dev);
3214 bcm43xx_dma_free(dev);
3215 bcm43xx_chip_exit(dev);
3216 bcm43xx_radio_turn_off(dev);
3217 bcm43xx_switch_analog(dev, 0);
3218 if (phy->dyn_tssi_tbl)
3219 kfree(phy->tssi2dbm);
3220 kfree(phy->lo_control);
3221 phy->lo_control = NULL;
3222 ssb_device_disable(dev->dev, 0);
3223 ssb_bus_may_powerdown(dev->dev->bus);
3224 bcm43xx_set_status(dev, BCM43xx_STAT_UNINIT);
3225 }
3226
3227 /* Initialize a wireless core */
3228 static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev)
3229 {
3230 struct bcm43xx_wl *wl = dev->wl;
3231 struct ssb_bus *bus = dev->dev->bus;
3232 struct ssb_sprom *sprom = &bus->sprom;
3233 struct bcm43xx_phy *phy = &dev->phy;
3234 int err;
3235 u32 hf, tmp;
3236
3237 assert(bcm43xx_status(dev) == BCM43xx_STAT_UNINIT);
3238 bcm43xx_set_status(dev, BCM43xx_STAT_INITIALIZING);
3239
3240 err = ssb_bus_powerup(bus, 0);
3241 if (err)
3242 goto out;
3243 if (!ssb_device_is_enabled(dev->dev)) {
3244 tmp = phy->gmode ? BCM43xx_TMSLOW_GMODE : 0;
3245 bcm43xx_wireless_core_reset(dev, tmp);
3246 }
3247
3248 if ((phy->type == BCM43xx_PHYTYPE_B) || (phy->type == BCM43xx_PHYTYPE_G)) {
3249 phy->lo_control = kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3250 if (!phy->lo_control) {
3251 err = -ENOMEM;
3252 goto err_busdown;
3253 }
3254 }
3255 setup_struct_wldev_for_init(dev);
3256
3257 err = bcm43xx_phy_init_tssi2dbm_table(dev);
3258 if (err)
3259 goto err_kfree_lo_control;
3260
3261 /* Enable IRQ routing to this device. */
3262 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3263
3264 bcm43xx_imcfglo_timeouts_workaround(dev);
3265 bcm43xx_bluetooth_coext_disable(dev);
3266 bcm43xx_phy_early_init(dev);
3267 err = bcm43xx_chip_init(dev);
3268 if (err)
3269 goto err_kfree_tssitbl;
3270 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
3271 BCM43xx_SHM_SH_WLCOREREV,
3272 dev->dev->id.revision);
3273 hf = bcm43xx_hf_read(dev);
3274 if (phy->type == BCM43xx_PHYTYPE_G) {
3275 hf |= BCM43xx_HF_SYMW;
3276 if (phy->rev == 1)
3277 hf |= BCM43xx_HF_GDCW;
3278 if (sprom->r1.boardflags_lo & BCM43xx_BFL_PACTRL)
3279 hf |= BCM43xx_HF_OFDMPABOOST;
3280 } else if (phy->type == BCM43xx_PHYTYPE_B) {
3281 hf |= BCM43xx_HF_SYMW;
3282 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3283 hf &= ~BCM43xx_HF_GDCW;
3284 }
3285 bcm43xx_hf_write(dev, hf);
3286
3287 /* Short/Long Retry Limit.
3288 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3289 * the chip-internal counter.
3290 */
3291 tmp = limit_value(modparam_short_retry, 0, 0xF);
3292 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3293 BCM43xx_SHM_SC_SRLIMIT, tmp);
3294 tmp = limit_value(modparam_long_retry, 0, 0xF);
3295 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3296 BCM43xx_SHM_SC_LRLIMIT, tmp);
3297
3298 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
3299 BCM43xx_SHM_SH_SFFBLIM, 3);
3300 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
3301 BCM43xx_SHM_SH_LFFBLIM, 2);
3302
3303 bcm43xx_rate_memory_init(dev);
3304
3305 /* Minimum Contention Window */
3306 if (phy->type == BCM43xx_PHYTYPE_B) {
3307 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3308 BCM43xx_SHM_SC_MINCONT, 0x1F);
3309 } else {
3310 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3311 BCM43xx_SHM_SC_MINCONT, 0xF);
3312 }
3313 /* Maximum Contention Window */
3314 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3315 BCM43xx_SHM_SC_MAXCONT, 0x3FF);
3316
3317 do {
3318 if (bcm43xx_using_pio(dev)) {
3319 err = bcm43xx_pio_init(dev);
3320 } else {
3321 err = bcm43xx_dma_init(dev);
3322 if (!err)
3323 bcm43xx_qos_init(dev);
3324 }
3325 } while (err == -EAGAIN);
3326 if (err)
3327 goto err_chip_exit;
3328
3329 //FIXME
3330 #if 1
3331 bcm43xx_write16(dev, 0x0612, 0x0050);
3332 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
3333 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
3334 #endif
3335
3336 bcm43xx_bluetooth_coext_enable(dev);
3337
3338 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3339 wl->bssid = NULL;
3340 bcm43xx_upload_card_macaddress(dev, NULL);
3341 bcm43xx_security_init(dev);
3342 bcm43xx_rng_init(wl);
3343
3344 bcm43xx_set_status(dev, BCM43xx_STAT_INITIALIZED);
3345
3346 out:
3347 return err;
3348
3349 err_chip_exit:
3350 bcm43xx_chip_exit(dev);
3351 err_kfree_tssitbl:
3352 if (phy->dyn_tssi_tbl)
3353 kfree(phy->tssi2dbm);
3354 err_kfree_lo_control:
3355 kfree(phy->lo_control);
3356 phy->lo_control = NULL;
3357 err_busdown:
3358 ssb_bus_may_powerdown(bus);
3359 bcm43xx_set_status(dev, BCM43xx_STAT_UNINIT);
3360 return err;
3361 }
3362
3363 static int bcm43xx_add_interface(struct ieee80211_hw *hw,
3364 struct ieee80211_if_init_conf *conf)
3365 {
3366 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
3367 struct bcm43xx_wldev *dev;
3368 unsigned long flags;
3369 int err = -EOPNOTSUPP;
3370 int did_init = 0;
3371
3372 mutex_lock(&wl->mutex);
3373 if ((conf->type != IEEE80211_IF_TYPE_MNTR) &&
3374 wl->operating)
3375 goto out_mutex_unlock;
3376
3377 dprintk(KERN_INFO PFX "Adding Interface type %d\n", conf->type);
3378
3379 dev = wl->current_dev;
3380 if (bcm43xx_status(dev) == BCM43xx_STAT_UNINIT) {
3381 err = bcm43xx_wireless_core_init(dev);
3382 if (err)
3383 goto out_mutex_unlock;
3384 did_init = 1;
3385 }
3386 if (!dev->started) {
3387 err = bcm43xx_wireless_core_start(dev);
3388 if (err) {
3389 if (did_init)
3390 bcm43xx_wireless_core_exit(dev);
3391 goto out_mutex_unlock;
3392 }
3393 }
3394
3395 spin_lock_irqsave(&wl->irq_lock, flags);
3396 switch (conf->type) {
3397 case IEEE80211_IF_TYPE_MNTR:
3398 wl->monitor++;
3399 break;
3400 default:
3401 wl->operating = 1;
3402 wl->if_id = conf->if_id;
3403 wl->if_type = conf->type;
3404 bcm43xx_upload_card_macaddress(dev, conf->mac_addr);
3405 }
3406 bcm43xx_adjust_opmode(dev);
3407 spin_unlock_irqrestore(&wl->irq_lock, flags);
3408
3409 err = 0;
3410 out_mutex_unlock:
3411 mutex_unlock(&wl->mutex);
3412
3413 return err;
3414 }
3415
3416 static void bcm43xx_remove_interface(struct ieee80211_hw *hw,
3417 struct ieee80211_if_init_conf *conf)
3418 {
3419 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
3420 struct bcm43xx_wldev *dev;
3421 unsigned long flags;
3422
3423 dprintk(KERN_INFO PFX "Removing Interface type %d\n", conf->type);
3424
3425 mutex_lock(&wl->mutex);
3426 if (conf->type == IEEE80211_IF_TYPE_MNTR) {
3427 wl->monitor--;
3428 assert(wl->monitor >= 0);
3429 } else {
3430 assert(wl->operating);
3431 wl->operating = 0;
3432 }
3433
3434 dev = wl->current_dev;
3435 if (!wl->operating && wl->monitor == 0) {
3436 /* No interface left. */
3437 if (dev->started)
3438 bcm43xx_wireless_core_stop(dev);
3439 bcm43xx_wireless_core_exit(dev);
3440 } else {
3441 /* Just monitor interfaces left. */
3442 spin_lock_irqsave(&wl->irq_lock, flags);
3443 bcm43xx_adjust_opmode(dev);
3444 if (!wl->operating)
3445 bcm43xx_upload_card_macaddress(dev, NULL);
3446 spin_unlock_irqrestore(&wl->irq_lock, flags);
3447 }
3448 mutex_unlock(&wl->mutex);
3449 }
3450
3451
3452 static const struct ieee80211_ops bcm43xx_hw_ops = {
3453 .tx = bcm43xx_tx,
3454 .conf_tx = bcm43xx_conf_tx,
3455 .add_interface = bcm43xx_add_interface,
3456 .remove_interface = bcm43xx_remove_interface,
3457 .reset = bcm43xx_dev_reset,
3458 .config = bcm43xx_dev_config,
3459 .config_interface = bcm43xx_config_interface,
3460 .set_multicast_list = bcm43xx_set_multicast_list,
3461 .set_key = bcm43xx_dev_set_key,
3462 .get_stats = bcm43xx_get_stats,
3463 .get_tx_stats = bcm43xx_get_tx_stats,
3464 };
3465
3466 /* Hard-reset the chip. Do not call this directly.
3467 * Use bcm43xx_controller_restart()
3468 */
3469 static void bcm43xx_chip_reset(struct work_struct *work)
3470 {
3471 struct bcm43xx_wldev *dev =
3472 container_of(work, struct bcm43xx_wldev, restart_work);
3473 struct bcm43xx_wl *wl = dev->wl;
3474 int err;
3475 int was_started = 0;
3476 int was_inited = 0;
3477
3478 mutex_lock(&wl->mutex);
3479
3480 /* Bring the device down... */
3481 if (dev->started) {
3482 was_started = 1;
3483 bcm43xx_wireless_core_stop(dev);
3484 }
3485 if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED) {
3486 was_inited = 1;
3487 bcm43xx_wireless_core_exit(dev);
3488 }
3489
3490 /* ...and up again. */
3491 if (was_inited) {
3492 err = bcm43xx_wireless_core_init(dev);
3493 if (err)
3494 goto out;
3495 }
3496 if (was_started) {
3497 assert(was_inited);
3498 err = bcm43xx_wireless_core_start(dev);
3499 if (err) {
3500 bcm43xx_wireless_core_exit(dev);
3501 goto out;
3502 }
3503 }
3504 out:
3505 mutex_unlock(&wl->mutex);
3506 if (err)
3507 printk(KERN_ERR PFX "Controller restart FAILED\n");
3508 else
3509 printk(KERN_INFO PFX "Controller restarted\n");
3510 }
3511
3512 static int bcm43xx_setup_modes(struct bcm43xx_wldev *dev,
3513 int have_aphy,
3514 int have_bphy,
3515 int have_gphy)
3516 {
3517 struct ieee80211_hw *hw = dev->wl->hw;
3518 struct ieee80211_hw_mode *mode;
3519 struct bcm43xx_phy *phy = &dev->phy;
3520 int cnt = 0;
3521 int err;
3522
3523 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3524 have_aphy = 0;
3525
3526 phy->possible_phymodes = 0;
3527 for ( ; 1; cnt++) {
3528 if (have_aphy) {
3529 assert(cnt < BCM43xx_MAX_PHYHWMODES);
3530 mode = &phy->hwmodes[cnt];
3531
3532 mode->mode = MODE_IEEE80211A;
3533 mode->num_channels = bcm43xx_a_chantable_size;
3534 mode->channels = bcm43xx_a_chantable;
3535 mode->num_rates = bcm43xx_a_ratetable_size;
3536 mode->rates = bcm43xx_a_ratetable;
3537 err = ieee80211_register_hwmode(hw, mode);
3538 if (err)
3539 return err;
3540
3541 phy->possible_phymodes |= BCM43xx_PHYMODE_A;
3542 have_aphy = 0;
3543 continue;
3544 }
3545 if (have_bphy) {
3546 assert(cnt < BCM43xx_MAX_PHYHWMODES);
3547 mode = &phy->hwmodes[cnt];
3548
3549 mode->mode = MODE_IEEE80211B;
3550 mode->num_channels = bcm43xx_bg_chantable_size;
3551 mode->channels = bcm43xx_bg_chantable;
3552 mode->num_rates = bcm43xx_b_ratetable_size;
3553 mode->rates = bcm43xx_b_ratetable;
3554 err = ieee80211_register_hwmode(hw, mode);
3555 if (err)
3556 return err;
3557
3558 phy->possible_phymodes |= BCM43xx_PHYMODE_B;
3559 have_bphy = 0;
3560 continue;
3561 }
3562 if (have_gphy) {
3563 assert(cnt < BCM43xx_MAX_PHYHWMODES);
3564 mode = &phy->hwmodes[cnt];
3565
3566 mode->mode = MODE_IEEE80211G;
3567 mode->num_channels = bcm43xx_bg_chantable_size;
3568 mode->channels = bcm43xx_bg_chantable;
3569 mode->num_rates = bcm43xx_g_ratetable_size;
3570 mode->rates = bcm43xx_g_ratetable;
3571 err = ieee80211_register_hwmode(hw, mode);
3572 if (err)
3573 return err;
3574
3575 phy->possible_phymodes |= BCM43xx_PHYMODE_G;
3576 have_gphy = 0;
3577 continue;
3578 }
3579 break;
3580 }
3581
3582 return 0;
3583 }
3584
3585 static void bcm43xx_wireless_core_detach(struct bcm43xx_wldev *dev)
3586 {
3587 /* We release firmware that late to not be required to re-request
3588 * is all the time when we reinit the core. */
3589 bcm43xx_release_firmware(dev);
3590 }
3591
3592 static int bcm43xx_wireless_core_attach(struct bcm43xx_wldev *dev)
3593 {
3594 struct bcm43xx_wl *wl = dev->wl;
3595 struct ssb_bus *bus = dev->dev->bus;
3596 struct pci_dev *pdev = bus->host_pci;
3597 int err;
3598 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3599 u32 tmp;
3600
3601 /* Do NOT do any device initialization here.
3602 * Do it in wireless_core_init() instead.
3603 * This function is for gathering basic information about the HW, only.
3604 * Also some structs may be set up here. But most likely you want to have
3605 * that in core_init(), too.
3606 */
3607
3608 /* Get the PHY type. */
3609 if (dev->dev->id.revision >= 5) {
3610 u32 tmshigh;
3611
3612 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3613 have_aphy = !!(tmshigh & BCM43xx_TMSHIGH_APHY);
3614 have_gphy = !!(tmshigh & BCM43xx_TMSHIGH_GPHY);
3615 if (!have_aphy && !have_gphy)
3616 have_bphy = 1;
3617 } else if (dev->dev->id.revision == 4) {
3618 have_gphy = 1;
3619 have_aphy = 1;
3620 } else
3621 have_bphy = 1;
3622
3623 /* Initialize LEDs structs. */
3624 err = bcm43xx_leds_init(dev);
3625 if (err)
3626 goto out;
3627
3628 dev->phy.gmode = (have_gphy || have_bphy);
3629 tmp = dev->phy.gmode ? BCM43xx_TMSLOW_GMODE : 0;
3630 bcm43xx_wireless_core_reset(dev, tmp);
3631
3632 err = bcm43xx_phy_versioning(dev);
3633 if (err)
3634 goto err_leds_exit;
3635 /* Check if this device supports multiband. */
3636 if (!pdev ||
3637 (pdev->device != 0x4312 &&
3638 pdev->device != 0x4319 &&
3639 pdev->device != 0x4324)) {
3640 /* No multiband support. */
3641 have_aphy = 0;
3642 have_bphy = 0;
3643 have_gphy = 0;
3644 switch (dev->phy.type) {
3645 case BCM43xx_PHYTYPE_A:
3646 have_aphy = 1;
3647 break;
3648 case BCM43xx_PHYTYPE_B:
3649 have_bphy = 1;
3650 break;
3651 case BCM43xx_PHYTYPE_G:
3652 have_gphy = 1;
3653 break;
3654 default:
3655 assert(0);
3656 }
3657 }
3658 dev->phy.gmode = (have_gphy || have_bphy);
3659 tmp = dev->phy.gmode ? BCM43xx_TMSLOW_GMODE : 0;
3660 bcm43xx_wireless_core_reset(dev, tmp);
3661
3662 err = bcm43xx_validate_chipaccess(dev);
3663 if (err)
3664 goto err_leds_exit;
3665 err = bcm43xx_setup_modes(dev, have_aphy,
3666 have_bphy, have_gphy);
3667 if (err)
3668 goto err_leds_exit;
3669
3670 /* Now set some default "current_dev" */
3671 if (!wl->current_dev)
3672 wl->current_dev = dev;
3673 INIT_WORK(&dev->restart_work, bcm43xx_chip_reset);
3674
3675 bcm43xx_radio_turn_off(dev);
3676 bcm43xx_switch_analog(dev, 0);
3677 ssb_device_disable(dev->dev, 0);
3678 ssb_bus_may_powerdown(bus);
3679
3680 out:
3681 return err;
3682
3683 err_leds_exit:
3684 bcm43xx_leds_exit(dev);
3685 return err;
3686 }
3687
3688 static void bcm43xx_one_core_detach(struct ssb_device *dev)
3689 {
3690 struct bcm43xx_wldev *wldev;
3691 struct bcm43xx_wl *wl;
3692
3693 wldev = ssb_get_drvdata(dev);
3694 wl = wldev->wl;
3695 bcm43xx_debugfs_remove_device(wldev);
3696 bcm43xx_wireless_core_detach(wldev);
3697 list_del(&wldev->list);
3698 wl->nr_devs--;
3699 ssb_set_drvdata(dev, NULL);
3700 kfree(wldev);
3701 }
3702
3703 static int bcm43xx_one_core_attach(struct ssb_device *dev,
3704 struct bcm43xx_wl *wl)
3705 {
3706 struct bcm43xx_wldev *wldev;
3707 struct pci_dev *pdev;
3708 int err = -ENOMEM;
3709
3710 if (!list_empty(&wl->devlist)) {
3711 /* We are not the first core on this chip. */
3712 pdev = dev->bus->host_pci;
3713 /* Only special chips support more than one wireless
3714 * core, although some of the other chips have more than
3715 * one wireless core as well. Check for this and
3716 * bail out early.
3717 */
3718 if (!pdev ||
3719 ((pdev->device != 0x4321) &&
3720 (pdev->device != 0x4313) &&
3721 (pdev->device != 0x431A))) {
3722 dprintk(KERN_INFO PFX "Ignoring unconnected 802.11 core\n");
3723 return -ENODEV;
3724 }
3725 }
3726
3727 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3728 if (!wldev)
3729 goto out;
3730
3731 wldev->dev = dev;
3732 wldev->wl = wl;
3733 bcm43xx_set_status(wldev, BCM43xx_STAT_UNINIT);
3734 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3735 tasklet_init(&wldev->isr_tasklet,
3736 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3737 (unsigned long)wldev);
3738 if (modparam_pio)
3739 wldev->__using_pio = 1;
3740 INIT_LIST_HEAD(&wldev->list);
3741
3742 err = bcm43xx_wireless_core_attach(wldev);
3743 if (err)
3744 goto err_kfree_wldev;
3745
3746 list_add(&wldev->list, &wl->devlist);
3747 wl->nr_devs++;
3748 ssb_set_drvdata(dev, wldev);
3749 bcm43xx_debugfs_add_device(wldev);
3750
3751 out:
3752 return err;
3753
3754 err_kfree_wldev:
3755 kfree(wldev);
3756 return err;
3757 }
3758
3759 static void bcm43xx_sprom_fixup(struct ssb_bus *bus)
3760 {
3761 /* boardflags workarounds */
3762 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3763 bus->chip_id == 0x4301 &&
3764 bus->boardinfo.rev == 0x74)
3765 bus->sprom.r1.boardflags_lo |= BCM43xx_BFL_BTCOEXIST;
3766 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3767 bus->boardinfo.type == 0x4E &&
3768 bus->boardinfo.rev > 0x40)
3769 bus->sprom.r1.boardflags_lo |= BCM43xx_BFL_PACTRL;
3770
3771 /* Convert Antennagain values to Q5.2 */
3772 bus->sprom.r1.antenna_gain_a <<= 2;
3773 bus->sprom.r1.antenna_gain_bg <<= 2;
3774 }
3775
3776 static void bcm43xx_wireless_exit(struct ssb_device *dev,
3777 struct bcm43xx_wl *wl)
3778 {
3779 struct ieee80211_hw *hw = wl->hw;
3780
3781 ssb_set_devtypedata(dev, NULL);
3782 ieee80211_free_hw(hw);
3783 }
3784
3785 static int bcm43xx_wireless_init(struct ssb_device *dev)
3786 {
3787 struct ssb_sprom *sprom = &dev->bus->sprom;
3788 struct ieee80211_hw *hw;
3789 struct bcm43xx_wl *wl;
3790 int err = -ENOMEM;
3791
3792 bcm43xx_sprom_fixup(dev->bus);
3793
3794 hw = ieee80211_alloc_hw(sizeof(*wl), &bcm43xx_hw_ops);
3795 if (!hw) {
3796 printk(KERN_ERR PFX "Could not allocate ieee80211 device\n");
3797 goto out;
3798 }
3799
3800 /* fill hw info */
3801 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3802 IEEE80211_HW_MONITOR_DURING_OPER |
3803 IEEE80211_HW_DEVICE_HIDES_WEP |
3804 IEEE80211_HW_WEP_INCLUDE_IV;
3805 hw->max_signal = 100;
3806 hw->max_rssi = -110;
3807 hw->max_noise = -110;
3808 hw->queues = 1; /* FIXME: hardware has more queues */
3809 SET_IEEE80211_DEV(hw, dev->dev);
3810 if (is_valid_ether_addr(sprom->r1.et1mac))
3811 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3812 else
3813 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3814
3815 /* Get and initialize struct bcm43xx_wl */
3816 wl = hw_to_bcm43xx_wl(hw);
3817 memset(wl, 0, sizeof(*wl));
3818 wl->hw = hw;
3819 spin_lock_init(&wl->irq_lock);
3820 spin_lock_init(&wl->leds_lock);
3821 mutex_init(&wl->mutex);
3822 INIT_LIST_HEAD(&wl->devlist);
3823
3824 ssb_set_devtypedata(dev, wl);
3825 printk(KERN_INFO PFX "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3826 err = 0;
3827 out:
3828 return err;
3829 }
3830
3831 static int bcm43xx_probe(struct ssb_device *dev,
3832 const struct ssb_device_id *id)
3833 {
3834 struct bcm43xx_wl *wl;
3835 int err;
3836 int first = 0;
3837
3838 wl = ssb_get_devtypedata(dev);
3839 if (!wl) {
3840 /* Probing the first core. Must setup common struct bcm43xx_wl */
3841 first = 1;
3842 err = bcm43xx_wireless_init(dev);
3843 if (err)
3844 goto out;
3845 wl = ssb_get_devtypedata(dev);
3846 assert(wl);
3847 }
3848 err = bcm43xx_one_core_attach(dev, wl);
3849 if (err)
3850 goto err_wireless_exit;
3851
3852 if (first) {
3853 err = ieee80211_register_hw(wl->hw);
3854 if (err)
3855 goto err_one_core_detach;
3856 }
3857
3858 out:
3859 return err;
3860
3861 err_one_core_detach:
3862 bcm43xx_one_core_detach(dev);
3863 err_wireless_exit:
3864 if (first)
3865 bcm43xx_wireless_exit(dev, wl);
3866 return err;
3867 }
3868
3869 static void bcm43xx_remove(struct ssb_device *dev)
3870 {
3871 struct bcm43xx_wl *wl = ssb_get_devtypedata(dev);
3872 struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
3873
3874 assert(wl);
3875 if (wl->current_dev == wldev)
3876 ieee80211_unregister_hw(wl->hw);
3877
3878 bcm43xx_one_core_detach(dev);
3879
3880 if (list_empty(&wl->devlist)) {
3881 /* Last core on the chip unregistered.
3882 * We can destroy common struct bcm43xx_wl.
3883 */
3884 bcm43xx_wireless_exit(dev, wl);
3885 }
3886 }
3887
3888 /* Hard-reset the chip.
3889 * This can be called from interrupt or process context.
3890 * dev->irq_lock must be locked.
3891 */
3892 void bcm43xx_controller_restart(struct bcm43xx_wldev *dev, const char *reason)
3893 {
3894 if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
3895 return;
3896 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3897 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3898 }
3899
3900 #ifdef CONFIG_PM
3901
3902 static int bcm43xx_suspend(struct ssb_device *dev, pm_message_t state)
3903 {
3904 struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
3905 struct bcm43xx_wl *wl = wldev->wl;
3906
3907 dprintk(KERN_INFO PFX "Suspending...\n");
3908
3909 mutex_lock(&wl->mutex);
3910 wldev->was_started = !!wldev->started;
3911 wldev->was_initialized = (bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED);
3912 if (wldev->started)
3913 bcm43xx_wireless_core_stop(wldev);
3914 if (bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED)
3915 bcm43xx_wireless_core_exit(wldev);
3916
3917 mutex_unlock(&wl->mutex);
3918
3919 dprintk(KERN_INFO PFX "Device suspended.\n");
3920
3921 return 0;
3922 }
3923
3924 static int bcm43xx_resume(struct ssb_device *dev)
3925 {
3926 struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
3927 int err = 0;
3928
3929 dprintk(KERN_INFO PFX "Resuming...\n");
3930
3931 if (wldev->was_initialized) {
3932 err = bcm43xx_wireless_core_init(wldev);
3933 if (err) {
3934 printk(KERN_ERR PFX "Resume failed at core init\n");
3935 goto out;
3936 }
3937 }
3938 if (wldev->was_started) {
3939 assert(wldev->was_initialized);
3940 err = bcm43xx_wireless_core_start(wldev);
3941 if (err) {
3942 printk(KERN_ERR PFX "Resume failed at core start\n");
3943 goto out;
3944 }
3945 }
3946
3947 dprintk(KERN_INFO PFX "Device resumed.\n");
3948 out:
3949 return err;
3950 }
3951
3952 #else /* CONFIG_PM */
3953 # define bcm43xx_suspend NULL
3954 # define bcm43xx_resume NULL
3955 #endif /* CONFIG_PM */
3956
3957 static struct ssb_driver bcm43xx_ssb_driver = {
3958 .name = KBUILD_MODNAME,
3959 .id_table = bcm43xx_ssb_tbl,
3960 .probe = bcm43xx_probe,
3961 .remove = bcm43xx_remove,
3962 .suspend = bcm43xx_suspend,
3963 .resume = bcm43xx_resume,
3964 };
3965
3966 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3967 /* The PCI frontend stub */
3968 static const struct pci_device_id bcm43xx_pci_tbl[] = {
3969 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) },
3970 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
3971 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
3972 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
3973 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
3974 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
3975 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
3976 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
3977 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
3978 { 0 },
3979 };
3980 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
3981
3982 static struct pci_driver bcm43xx_pci_driver = {
3983 .name = "bcm43xx-pci",
3984 .id_table = bcm43xx_pci_tbl,
3985 };
3986 #endif /* CONFIG_BCM43XX_MAC80211_PCI */
3987
3988 static int __init bcm43xx_init(void)
3989 {
3990 int err;
3991
3992 bcm43xx_debugfs_init();
3993 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3994 err = ssb_pcihost_register(&bcm43xx_pci_driver);
3995 if (err)
3996 goto err_dfs_exit;
3997 #endif
3998 err = bcm43xx_pcmcia_init();
3999 if (err)
4000 goto err_pci_exit;
4001 err = ssb_driver_register(&bcm43xx_ssb_driver);
4002 if (err)
4003 goto err_pcmcia_exit;
4004
4005 return err;
4006
4007 err_pcmcia_exit:
4008 bcm43xx_pcmcia_exit();
4009 err_pci_exit:
4010 #ifdef CONFIG_BCM43XX_MAC80211_PCI
4011 ssb_pcihost_unregister(&bcm43xx_pci_driver);
4012 #endif
4013 err_dfs_exit:
4014 bcm43xx_debugfs_exit();
4015 return err;
4016 }
4017
4018 static void __exit bcm43xx_exit(void)
4019 {
4020 ssb_driver_unregister(&bcm43xx_ssb_driver);
4021 bcm43xx_pcmcia_exit();
4022 #ifdef CONFIG_BCM43XX_MAC80211_PCI
4023 ssb_pcihost_unregister(&bcm43xx_pci_driver);
4024 #endif
4025 bcm43xx_debugfs_exit();
4026 }
4027
4028 module_init(bcm43xx_init)
4029 module_exit(bcm43xx_exit)
OpenWrt Source Repository