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uboot-kirkwood: add uboot for nsa310b
[openwrt/openwrt.git] / package / boot / uboot-kirkwood / patches / 007-nsa310-uboot-generic.patch
1 arm: kirkwood: add ZyXEL NSA310 device
2
3 This patch add ZyXEL NSA310 1-Bay Media Server
4
5 The ZyXEL NSA310 device is a Kirkwood based NAS:
6
7 - SoC: Marvell 88F6702 1200Mhz
8 - SDRAM memory: 256MB DDR2 400Mhz
9 - Gigabit ethernet: PHY Realtek
10 - Flash memory: 128MB
11 - 1 Power button
12 - 1 Power LED (blue)
13 - 5 Status LED (green/red)
14 - 1 Copy/Sync button
15 - 1 Reset button
16 - 2 SATA II port (1 internal and 1 external eSata)
17 - 2 USB 2.0 ports (1 front and 1 back)
18 - Smart fan
19
20 Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it>
21
22 NOTE: this patch is ready for upstream, LEDE-specific parts are in
23 another patch
24
25 diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
26 index 9205b1e..819bd3b 100644
27 --- a/arch/arm/mach-kirkwood/Kconfig
28 +++ b/arch/arm/mach-kirkwood/Kconfig
29 @@ -49,6 +49,9 @@ config TARGET_GOFLEXHOME
30 config TARGET_NAS220
31 bool "BlackArmor NAS220"
32
33 +config TARGET_NSA310
34 + bool "Zyxel NSA310 Board"
35 +
36 config TARGET_NSA310S
37 bool "Zyxel NSA310S"
38
39 @@ -72,6 +75,7 @@ source "board/raidsonic/ib62x0/Kconfig"
40 source "board/Seagate/dockstar/Kconfig"
41 source "board/Seagate/goflexhome/Kconfig"
42 source "board/Seagate/nas220/Kconfig"
43 +source "board/zyxel/nsa310/Kconfig"
44 source "board/zyxel/nsa310s/Kconfig"
45
46 endif
47 diff --git a/board/zyxel/nsa310/Kconfig b/board/zyxel/nsa310/Kconfig
48 new file mode 100644
49 index 0000000..145ade6
50 --- /dev/null
51 +++ b/board/zyxel/nsa310/Kconfig
52 @@ -0,0 +1,12 @@
53 +if TARGET_NSA310
54 +
55 +config SYS_BOARD
56 + default "nsa310"
57 +
58 +config SYS_VENDOR
59 + default "zyxel"
60 +
61 +config SYS_CONFIG_NAME
62 + default "nsa310"
63 +
64 +endif
65 diff --git a/board/zyxel/nsa310/MAINTAINERS b/board/zyxel/nsa310/MAINTAINERS
66 new file mode 100644
67 index 0000000..d09f1ab
68 --- /dev/null
69 +++ b/board/zyxel/nsa310/MAINTAINERS
70 @@ -0,0 +1,6 @@
71 +NSA310 BOARD
72 +M: Alberto Bursi <alberto.bursi@outlook.it>
73 +S: Maintained
74 +F: board/zyxel/nsa310/
75 +F: include/configs/nsa310.h
76 +F: configs/nsa310_defconfig
77 diff --git a/board/zyxel/nsa310/Makefile b/board/zyxel/nsa310/Makefile
78 new file mode 100644
79 index 0000000..dfe93cc
80 --- /dev/null
81 +++ b/board/zyxel/nsa310/Makefile
82 @@ -0,0 +1,12 @@
83 +#
84 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
85 +#
86 +# Based on
87 +# (C) Copyright 2009
88 +# Marvell Semiconductor <www.marvell.com>
89 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
90 +#
91 +# SPDX-License-Identifier: GPL-2.0+
92 +#
93 +
94 +obj-y := nsa310.o
95 diff --git a/board/zyxel/nsa310/kwbimage.cfg b/board/zyxel/nsa310/kwbimage.cfg
96 new file mode 100644
97 index 0000000..f60e1d2
98 --- /dev/null
99 +++ b/board/zyxel/nsa310/kwbimage.cfg
100 @@ -0,0 +1,166 @@
101 +#
102 +# Copyright (C) 2013 Rafal Kazmierowski
103 +#
104 +# Based on guruplug.c originally written by
105 +# Siddarth Gore <gores@marvell.com>
106 +# (C) Copyright 2009
107 +# Marvell Semiconductor <www.marvell.com>
108 +#
109 +# See file CREDITS for list of people who contributed to this
110 +# project.
111 +#
112 +# This program is free software; you can redistribute it and/or
113 +# modify it under the terms of the GNU General Public License as
114 +# published by the Free Software Foundation; either version 2 of
115 +# the License, or (at your option) any later version.
116 +#
117 +# This program is distributed in the hope that it will be useful,
118 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
119 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
120 +# GNU General Public License for more details.
121 +#
122 +# You should have received a copy of the GNU General Public License
123 +# along with this program; if not, write to the Free Software
124 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
125 +# MA 02110-1301 USA
126 +#
127 +# Refer docs/README.kwimage for more details about how-to configure
128 +# and create kirkwood boot image
129 +#
130 +
131 +# Boot Media configurations
132 +BOOT_FROM nand
133 +#BOOT_FROM uart
134 +NAND_ECC_MODE default
135 +NAND_PAGE_SIZE 0x0800
136 +
137 +# SOC registers configuration using bootrom header extension
138 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
139 +
140 +# Configure RGMII-0 interface pad voltage to 1.8V
141 +DATA 0xFFD100e0 0x1b1b1b9b
142 +
143 +#Dram initalization for SINGLE x16 CL=5 @ 400MHz
144 +DATA 0xFFD01400 0x43010c30 # DDR Configuration register
145 +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
146 +# bit23-14: zero
147 +# bit24: 1= enable exit self refresh mode on DDR access
148 +# bit25: 1 required
149 +# bit29-26: zero
150 +# bit31-30: 01
151 +
152 +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
153 +# bit 4: 0=addr/cmd in smame cycle
154 +# bit 5: 0=clk is driven during self refresh, we don't care for APX
155 +# bit 6: 0=use recommended falling edge of clk for addr/cmd
156 +# bit14: 0=input buffer always powered up
157 +# bit18: 1=cpu lock transaction enabled
158 +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
159 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
160 +# bit30-28: 3 required
161 +# bit31: 0=no additional STARTBURST delay
162 +
163 +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
164 +# bit3-0: TRAS lsbs
165 +# bit7-4: TRCD
166 +# bit11- 8: TRP
167 +# bit15-12: TWR
168 +# bit19-16: TWTR
169 +# bit20: TRAS msb
170 +# bit23-21: 0x0
171 +# bit27-24: TRRD
172 +# bit31-28: TRTP
173 +
174 +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
175 +# bit6-0: TRFC
176 +# bit8-7: TR2R
177 +# bit10-9: TR2W
178 +# bit12-11: TW2W
179 +# bit31-13: zero required
180 +
181 +DATA 0xFFD01410 0x0000000c # DDR Address Control
182 +# bit1-0: 01, Cs0width=x8
183 +# bit3-2: 10, Cs0size=1Gb
184 +# bit5-4: 01, Cs1width=x8
185 +# bit7-6: 10, Cs1size=1Gb
186 +# bit9-8: 00, Cs2width=nonexistent
187 +# bit11-10: 00, Cs2size =nonexistent
188 +# bit13-12: 00, Cs3width=nonexistent
189 +# bit15-14: 00, Cs3size =nonexistent
190 +# bit16: 0, Cs0AddrSel
191 +# bit17: 0, Cs1AddrSel
192 +# bit18: 0, Cs2AddrSel
193 +# bit19: 0, Cs3AddrSel
194 +# bit31-20: 0 required
195 +
196 +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
197 +# bit0: 0, OpenPage enabled
198 +# bit31-1: 0 required
199 +
200 +DATA 0xFFD01418 0x00000000 # DDR Operation
201 +# bit3-0: 0x0, DDR cmd
202 +# bit31-4: 0 required
203 +
204 +DATA 0xFFD0141C 0x00000652 # DDR Mode
205 +# bit2-0: 2, BurstLen=2 required
206 +# bit3: 0, BurstType=0 required
207 +# bit6-4: 4, CL=5
208 +# bit7: 0, TestMode=0 normal
209 +# bit8: 0, DLL reset=0 normal
210 +# bit11-9: 6, auto-precharge write recovery ????????????
211 +# bit12: 0, PD must be zero
212 +# bit31-13: 0 required
213 +
214 +DATA 0xFFD01420 0x00000004 # DDR Extended Mode
215 +# bit0: 0, DDR DLL enabled
216 +# bit1: 0, DDR drive strenght normal
217 +# bit2: 0, DDR ODT control lsd (disabled)
218 +# bit5-3: 000, required
219 +# bit6: 1, DDR ODT control msb, (disabled)
220 +# bit9-7: 000, required
221 +# bit10: 0, differential DQS enabled
222 +# bit11: 0, required
223 +# bit12: 0, DDR output buffer enabled
224 +# bit31-13: 0 required
225 +
226 +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
227 +# bit2-0: 111, required
228 +# bit3 : 1 , MBUS Burst Chop disabled
229 +# bit6-4: 111, required
230 +# bit7 : 0
231 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
232 +# bit9 : 0 , no half clock cycle addition to dataout
233 +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
234 +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
235 +# bit15-12: 1111 required
236 +# bit31-16: 0 required
237 +
238 +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
239 +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
240 +
241 +
242 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
243 +#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
244 +# bit0: 1, Window enabled
245 +# bit1: 0, Write Protect disabled
246 +# bit3-2: 00, CS0 hit selected
247 +# bit23-4: ones, required
248 +# bit31-24: 0x0F, Size (i.e. 256MB)
249 +
250 +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
251 +DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db
252 +DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled
253 +
254 +DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low)
255 +DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW
256 +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
257 +# bit3-2: 01, ODT1 active NEVER!
258 +# bit31-4: zero, required
259 +
260 +DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI
261 +DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL
262 +DATA 0xFFD01480 0x00000001 # DDR Initialization Control
263 +#bit0=1, enable DDR init upon this register write
264 +
265 +# End of Header extension
266 +DATA 0x0 0x0
267 diff --git a/board/zyxel/nsa310/nsa310.c b/board/zyxel/nsa310/nsa310.c
268 new file mode 100644
269 index 0000000..eee3f1a
270 --- /dev/null
271 +++ b/board/zyxel/nsa310/nsa310.c
272 @@ -0,0 +1,190 @@
273 +/*
274 + * Copyright (C) 2013 Rafal Kazmierowski
275 + *
276 + * Based on NSA320.c Peter Schildmann <linux@schildmann.info>
277 + * originally written by
278 + * Marvell Semiconductor <www.marvell.com>
279 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
280 + *
281 + * See file CREDITS for list of people who contributed to this
282 + * project.
283 + *
284 + * This program is free software; you can redistribute it and/or
285 + * modify it under the terms of the GNU General Public License as
286 + * published by the Free Software Foundation; either version 2 of
287 + * the License, or (at your option) any later version.
288 + *
289 + * This program is distributed in the hope that it will be useful,
290 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
291 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
292 + * GNU General Public License for more details.
293 + *
294 + * You should have received a copy of the GNU General Public License
295 + * along with this program; if not, write to the Free Software
296 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
297 + * MA 02110-1301 USA
298 + */
299 +
300 +#include <common.h>
301 +#include <miiphy.h>
302 +#include <asm/arch/cpu.h>
303 +#include <asm/arch/soc.h>
304 +#include <asm/arch/mpp.h>
305 +#include <asm/io.h>
306 +#include "nsa310.h"
307 +
308 +DECLARE_GLOBAL_DATA_PTR;
309 +
310 +int board_early_init_f(void)
311 +{
312 + /*
313 + * default gpio configuration
314 + * There are maximum 64 gpios controlled through 2 sets of registers
315 + * the below configuration configures mainly initial LED status
316 + */
317 + mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,
318 + NSA310_OE_LOW, NSA310_OE_HIGH);
319 +
320 + /* Multi-Purpose Pins Functionality configuration */
321 + /* (all LEDs & power off active high) */
322 + static const u32 kwmpp_config[] = {
323 + MPP0_NF_IO2,
324 + MPP1_NF_IO3,
325 + MPP2_NF_IO4,
326 + MPP3_NF_IO5,
327 + MPP4_NF_IO6,
328 + MPP5_NF_IO7,
329 + MPP6_SYSRST_OUTn,
330 + MPP7_GPO,
331 + MPP8_TW_SDA, /* PCF8563 RTC chip */
332 + MPP9_TW_SCK, /* connected to TWSI */
333 + MPP10_UART0_TXD,
334 + MPP11_UART0_RXD,
335 + MPP12_GPO, /* SATA2 LED (green) */
336 + MPP13_GPIO, /* SATA2 LED (red) */
337 + MPP14_GPIO, /* MCU DATA pin (in) */
338 + MPP15_GPIO, /* USB LED (green) */
339 + MPP16_GPIO, /* MCU CLK pin (out) */
340 + MPP17_GPIO, /* MCU ACT pin (out) */
341 + MPP18_NF_IO0,
342 + MPP19_NF_IO1,
343 + MPP20_GPIO,
344 + MPP21_GPIO, /* USB LED (red)-Power*/
345 + MPP22_GPIO,
346 + MPP23_GPIO,
347 + MPP24_GPIO,
348 + MPP25_GPIO,
349 + MPP26_GPIO,
350 + MPP27_GPIO,
351 + MPP28_GPIO, /* SYS LED (green) */
352 + MPP29_GPIO, /* SYS LED (red) */
353 + MPP30_GPIO,
354 + MPP31_GPIO,
355 + MPP32_GPIO,
356 + MPP33_GPIO,
357 + MPP34_GPIO,
358 + MPP35_GPIO,
359 + MPP36_GPIO, /* Reset button */
360 + MPP37_GPIO, /* Copy button */
361 + MPP38_GPIO, /* VID B0 */
362 + MPP39_GPIO, /* COPY LED (green) */
363 + MPP40_GPIO, /* COPY LED (red) */
364 + MPP41_GPIO, /* SATA1 LED (green) */
365 + MPP42_GPIO, /* SATA1 LED (red) */
366 + MPP43_GPIO, /* HTP pin */
367 + MPP44_GPIO, /* Buzzer */
368 + MPP45_GPIO, /* VID B1 */
369 + MPP46_GPIO, /* Power button */
370 + MPP47_GPIO, /* Power resume data */
371 + MPP48_GPIO, /* Power off */
372 + MPP49_GPIO, /* Power resume clock */
373 + 0
374 + };
375 + kirkwood_mpp_conf(kwmpp_config,NULL);
376 + return 0;
377 +}
378 +
379 +int board_init(void)
380 +{
381 + /* address of boot parameters */
382 + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
383 +
384 + return 0;
385 +}
386 +
387 +#ifdef CONFIG_RESET_PHY_R
388 +/* Configure and enable MV88E1318 PHY */
389 +void reset_phy(void)
390 +{
391 + u16 reg;
392 + u16 devadr;
393 + char *name = "egiga0";
394 +
395 + if (miiphy_set_current_dev(name))
396 + return;
397 +
398 + /* command to read PHY dev address */
399 + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
400 + printf("Err..%s could not read PHY dev address\n",
401 + __FUNCTION__);
402 + return;
403 + }
404 +
405 + /* Set RGMII delay */
406 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
407 + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
408 + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
409 + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
410 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
411 +
412 + /* reset the phy */
413 + miiphy_reset(name, devadr);
414 +
415 + printf("MV88E1318 PHY initialized on %s\n", name);
416 +}
417 +#endif /* CONFIG_RESET_PHY_R */
418 +
419 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
420 +void show_boot_progress(int val)
421 +{
422 + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
423 + u32 dout0 = readl(&gpio0->dout);
424 + u32 blen0 = readl(&gpio0->blink_en);
425 +
426 + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
427 + u32 dout1 = readl(&gpio1->dout);
428 + u32 blen1 = readl(&gpio1->blink_en);
429 +
430 + switch (val) {
431 + case BOOTSTAGE_ID_DECOMP_IMAGE:
432 + writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);
433 + writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);
434 + break;
435 + case BOOTSTAGE_ID_RUN_OS:
436 + writel(dout0 & ~SYS_RED_LED, &gpio0->dout);
437 + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
438 + break;
439 + case BOOTSTAGE_ID_NET_START:
440 + writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
441 + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
442 + break;
443 + case BOOTSTAGE_ID_NET_LOADED:
444 + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
445 + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
446 + break;
447 + case -BOOTSTAGE_ID_NET_NETLOOP_OK:
448 + case -BOOTSTAGE_ID_NET_LOADED:
449 + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
450 + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
451 + break;
452 + default:
453 + if (val < 0) {
454 + /* error */
455 + printf("Error occured, error code = %d\n", -val);
456 + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
457 + writel(blen0 | SYS_RED_LED, &gpio0->blink_en);
458 + }
459 + break;
460 + }
461 +}
462 +#endif
463 diff --git a/board/zyxel/nsa310/nsa310.h b/board/zyxel/nsa310/nsa310.h
464 new file mode 100644
465 index 0000000..6634a4f
466 --- /dev/null
467 +++ b/board/zyxel/nsa310/nsa310.h
468 @@ -0,0 +1,56 @@
469 +/*
470 + * Copyright (C) 2013 Rafal Kazmierowski
471 + *
472 + * Based on Peter Schildmann <linux@schildmann.info>
473 + * and guruplug.h originally written by
474 + * Siddarth Gore <gores@marvell.com>
475 + * (C) Copyright 2009
476 + * Marvell Semiconductor <www.marvell.com>
477 + *
478 + * See file CREDITS for list of people who contributed to this
479 + * project.
480 + *
481 + * This program is free software; you can redistribute it and/or
482 + * modify it under the terms of the GNU General Public License as
483 + * published by the Free Software Foundation; either version 2 of
484 + * the License, or (at your option) any later version.
485 + *
486 + * This program is distributed in the hope that it will be useful,
487 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
488 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
489 + * GNU General Public License for more details.
490 + *
491 + * You should have received a copy of the GNU General Public License
492 + * along with this program; if not, write to the Free Software
493 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
494 + * MA 02110-1301 USA
495 + */
496 +
497 +#ifndef __NSA310_H
498 +#define __NSA310_H
499 +
500 +/* GPIO's */
501 +#define SYS_GREEN_LED (1 << 28)
502 +#define SYS_RED_LED (1 << 29)
503 +#define SATA1_GREEN_LED (1 << 41)
504 +#define SATA1_RED_LED (1 << 42)
505 +#define SATA2_GREEN_LED (1 << 12)
506 +#define SATA2_RED_LED (1 << 13)
507 +#define USB_GREEN_LED (1 << 15)
508 +#define USB_RED_LED (1 << 21)
509 +#define COPY_GREEN_LED (1 << 39)
510 +#define COPY_RED_LED (1 << 40)
511 +
512 +#define NSA310_OE_LOW (0)
513 +#define NSA310_VAL_LOW (SYS_GREEN_LED)
514 +#define NSA310_OE_HIGH ((COPY_GREEN_LED | COPY_RED_LED | \
515 + SATA1_GREEN_LED | SATA1_RED_LED))
516 +#define NSA310_VAL_HIGH (0)
517 +
518 +/* PHY related */
519 +#define MV88E1318_MAC_CTRL_REG 21
520 +#define MV88E1318_PGADR_REG 22
521 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
522 +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
523 +
524 +#endif /* __NSA310_H */
525 diff --git a/configs/nsa310_defconfig b/configs/nsa310_defconfig
526 new file mode 100644
527 index 0000000..d26ef35
528 --- /dev/null
529 +++ b/configs/nsa310_defconfig
530 @@ -0,0 +1,18 @@
531 +CONFIG_ARM=y
532 +CONFIG_KIRKWOOD=y
533 +CONFIG_TARGET_NSA310=y
534 +CONFIG_BOOTDELAY=3
535 +CONFIG_SYS_PROMPT="NSA310> "
536 +# CONFIG_CMD_IMLS is not set
537 +# CONFIG_CMD_FLASH is not set
538 +CONFIG_SYS_NS16550=y
539 +CONFIG_CMD_FDT=y
540 +CONFIG_OF_LIBFDT=y
541 +CONFIG_CMD_SETEXPR=y
542 +CONFIG_CMD_DHCP=y
543 +CONFIG_CMD_NAND=y
544 +CONFIG_CMD_PING=y
545 +CONFIG_CMD_USB=y
546 +CONFIG_CMD_EXT2=y
547 +CONFIG_CMD_FAT=y
548 +CONFIG_USB_STORAGE=y
549 diff --git a/include/configs/nsa310.h b/include/configs/nsa310.h
550 new file mode 100644
551 index 0000000..86ef825
552 --- /dev/null
553 +++ b/include/configs/nsa310.h
554 @@ -0,0 +1,168 @@
555 +/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>
556 + *
557 + * Based on
558 + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
559 + *
560 + * Based on guruplug.h originally written by
561 + * Siddarth Gore <gores@marvell.com>
562 + * (C) Copyright 2009
563 + * Marvell Semiconductor <www.marvell.com>
564 + *
565 + * See file CREDITS for list of people who contributed to this
566 + * project.
567 + *
568 + * This program is free software; you can redistribute it and/or
569 + * modify it under the terms of the GNU General Public License as
570 + * published by the Free Software Foundation; either version 2 of
571 + * the License, or (at your option) any later version.
572 + *
573 + * This program is distributed in the hope that it will be useful,
574 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
575 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
576 + * GNU General Public License for more details.
577 + *
578 + * You should have received a copy of the GNU General Public License
579 + * along with this program; if not, write to the Free Software
580 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
581 + * MA 02110-1301 USA
582 + */
583 +
584 +#ifndef _CONFIG_NSA310_H
585 +#define _CONFIG_NSA310_H
586 +
587 +/*
588 + * Version number information
589 + */
590 +
591 +#define CONFIG_IDENT_STRING "\nZyXEL NSA310 1-Bay Power Media Server \n"
592 +
593 +/*
594 + * High Level Configuration Options (easy to change)
595 + */
596 +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
597 +#define CONFIG_KW88F6281 /* SOC Name */
598 +#define CONFIG_MACH_NSA310 /* Machine type */
599 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
600 +
601 +/*
602 + * Misc Configuration Options
603 + */
604 +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
605 +
606 +/*
607 + * Commands configuration
608 + */
609 +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
610 +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */
611 +#define CONFIG_CMD_DHCP
612 +#define CONFIG_CMD_ENV
613 +#define CONFIG_CMD_IDE
614 +#define CONFIG_CMD_MII
615 +#define CONFIG_CMD_NAND
616 +#define CONFIG_CMD_PING
617 +#define CONFIG_CMD_USB
618 +#define CONFIG_CMD_DATE
619 +#define CONFIG_SYS_LONGHELP
620 +#define CONFIG_PREBOOT
621 +#define CONFIG_SYS_HUSH_PARSER
622 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
623 +
624 +/*
625 + * mv-common.h should be defined after CMD configs since it used them
626 + * to enable certain macros
627 + */
628 +#include "mv-common.h"
629 +
630 +/* Remove or override few declarations from mv-common.h */
631 +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
632 +#define CONFIG_SYS_PROMPT "NSA310> " /* Command Prompt */
633 +
634 +/*
635 + * Environment variables configurations
636 + */
637 +#ifdef CONFIG_CMD_NAND
638 +#define CONFIG_ENV_IS_IN_NAND 1
639 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
640 +#else
641 +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
642 +#endif
643 +
644 +/* max 4k env size is enough, but in case of nand
645 + * it has to be rounded to sector size
646 + */
647 +#define CONFIG_ENV_SIZE 0x20000 /* 128k */
648 +#define CONFIG_ENV_ADDR 0xc0000
649 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */
650 +
651 +/*
652 + * Default environment variables
653 + */
654 +#define CONFIG_BOOTCOMMAND \
655 + "ubi part ubi; " \
656 + "ubi read 0x800000 kernel; " \
657 + "bootm 0x800000"
658 +
659 +#define CONFIG_MTDPARTS \
660 + "mtdparts=orion_nand:" \
661 + "0x0c0000(uboot)," \
662 + "0x80000(uboot_env)," \
663 + "0x7ec0000(ubi)\0"
664 +
665 +#define CONFIG_EXTRA_ENV_SETTINGS \
666 + "console=console=ttyS0,115200\0" \
667 + "mtdids=nand0=orion_nand\0" \
668 + "mtdparts="CONFIG_MTDPARTS \
669 + "bootargs_root=\0"
670 +
671 +/*
672 + * Ethernet Driver configuration
673 + */
674 +#ifdef CONFIG_CMD_NET
675 +#define CONFIG_NETCONSOLE
676 +#define CONFIG_NET_MULTI
677 +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
678 +#define CONFIG_PHY_BASE_ADR 0x1
679 +#define CONFIG_PHY_GIGE
680 +#define CONFIG_RESET_PHY_R
681 +#endif /* CONFIG_CMD_NET */
682 +
683 +/*
684 + * SATA Driver configuration
685 + */
686 +#ifdef CONFIG_MVSATA_IDE
687 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
688 +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
689 +#endif /* CONFIG_MVSATA_IDE */
690 +
691 +/*
692 + * File system
693 + */
694 +#define CONFIG_CMD_EXT2
695 +#define CONFIG_CMD_EXT4
696 +#define CONFIG_CMD_FAT
697 +#define CONFIG_CMD_JFFS2
698 +#define CONFIG_JFFS2_NAND
699 +#define CONFIG_JFFS2_LZO
700 +#define CONFIG_CMD_UBI
701 +#define CONFIG_CMD_UBIFS
702 +#define CONFIG_RBTREE
703 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
704 +#define CONFIG_MTD_PARTITIONS
705 +#define CONFIG_CMD_MTDPARTS
706 +#define CONFIG_LZO
707 +
708 +/*
709 + * EFI partition
710 + */
711 +#define CONFIG_EFI_PARTITION
712 +
713 +/*
714 + * Date Time
715 + */
716 +#ifdef CONFIG_CMD_DATE
717 +#define CONFIG_RTC_MV
718 +#define CONFIG_CMD_SNTP
719 +#define CONFIG_CMD_DNS
720 +#endif /* CONFIG_CMD_DATE */
721 +
722 +#endif /* _CONFIG_NSA310_H */
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