package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch

   1 --- a/arch/arm/mach-kirkwood/Kconfig
   2 +++ b/arch/arm/mach-kirkwood/Kconfig
   3 @@ -62,6 +62,9 @@ config TARGET_NSA310
   4  config TARGET_NSA310S
   5         bool "Zyxel NSA310S"
   6
   7 +config TARGET_NSA325
   8 +       bool "Zyxel NSA325 board"
   9 +
  10  endchoice
  11
  12  config SYS_SOC
  13 @@ -85,5 +88,6 @@ source "board/Seagate/goflexhome/Kconfig
  14  source "board/Seagate/nas220/Kconfig"
  15  source "board/zyxel/nsa310/Kconfig"
  16  source "board/zyxel/nsa310s/Kconfig"
  17 +source "board/zyxel/nsa325/Kconfig"
  18
  19  endif
  20 --- /dev/null
  21 +++ b/board/zyxel/nsa325/Kconfig
  22 @@ -0,0 +1,12 @@
  23 +if TARGET_NSA325
  24 +
  25 +config SYS_BOARD
  26 +       default "nsa325"
  27 +
  28 +config SYS_VENDOR
  29 +       default "zyxel"
  30 +
  31 +config SYS_CONFIG_NAME
  32 +       default "nsa325"
  33 +
  34 +endif
  35 --- /dev/null
  36 +++ b/board/zyxel/nsa325/MAINTAINERS
  37 @@ -0,0 +1,6 @@
  38 +NSA325 BOARD
  39 +M:     Alberto Bursi <alberto.bursi@outlook.it>
  40 +S:     Maintained
  41 +F:     board/zyxel/nsa325/
  42 +F:     include/configs/nsa325.h
  43 +F:     configs/nsa325_defconfig
  44 --- /dev/null
  45 +++ b/board/zyxel/nsa325/Makefile
  46 @@ -0,0 +1,13 @@
  47 +#
  48 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
  49 +#
  50 +# Based on
  51 +# (C) Copyright 2009
  52 +# Marvell Semiconductor <www.marvell.com>
  53 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  54 +#
  55 +# SPDX-License-Identifier:     GPL-2.0+
  56 +#
  57 +
  58 +obj-y  := nsa325.o
  59 +
  60 --- /dev/null
  61 +++ b/board/zyxel/nsa325/kwbimage.cfg
  62 @@ -0,0 +1,78 @@
  63 +# Copyright (C) 2015 bodhi <mibodhi@gmail.com>
  64 +#
  65 +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
  66 +#
  67 +# See file CREDITS for list of people who contributed to this
  68 +# project.
  69 +#
  70 +# This program is free software; you can redistribute it and/or
  71 +# modify it under the terms of the GNU General Public License as
  72 +# published by the Free Software Foundation; either version 2 of
  73 +# the License, or (at your option) any later version.
  74 +#
  75 +# This program is distributed in the hope that it will be useful,
  76 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  77 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  78 +# GNU General Public License for more details.
  79 +#
  80 +# You should have received a copy of the GNU General Public License
  81 +# along with this program; if not, write to the Free Software
  82 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  83 +# MA 02110-1301 USA
  84 +#
  85 +# Refer docs/README.kwimage for more details about how-to configure
  86 +# and create kirkwood boot image
  87 +#
  88 +
  89 +# Boot Media configurations
  90 +#BOOT_FROM     uart
  91 +BOOT_FROM       nand
  92 +NAND_ECC_MODE   default
  93 +NAND_PAGE_SIZE  0x0800
  94 +
  95 +# SOC registers configuration using bootrom header extension
  96 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  97 +
  98 +# Configure RGMII-0 interface pad voltage to 1.8V
  99 +DATA 0xFFD100e0 0x1b1b1b9b
 100 +
 101 +#Dram initalization
 102 +DATA 0xFFD01400 0x4301503E      # DDR Configuration register
 103 +DATA 0xFFD01404 0xB9843000      # DDR Controller Control Low
 104 +DATA 0xFFD01408 0x33137777      # DDR Timing (Low)
 105 +DATA 0xFFD0140C 0x16000C55      # DDR Timing (High)
 106 +DATA 0xFFD01410 0x04000000      # DDR Address Control
 107 +DATA 0xFFD01414 0x00000000     #  DDR Open Pages Control
 108 +DATA 0xFFD01418 0x00000000     #  DDR Operation
 109 +DATA 0xFFD0141C 0x00000672     #  DDR Mode
 110 +DATA 0xFFD01420 0x00000004     #  DDR Extended Mode
 111 +DATA 0xFFD01424 0x0000F14F     #  DDR Controller Control High
 112 +DATA 0xFFD01428 0x000D6720     # DDR3 ODT Read Timing
 113 +DATA 0xFFD0147C 0x0000B571     # DDR2 ODT Write Timing
 114 +DATA 0xFFD01504 0x1FFFFFF1      # CS[0]n Size
 115 +DATA 0xFFD01508 0x20000000      # CS[1]n Base address to 512Mb
 116 +DATA 0xFFD0150C 0x1FFFFFF4      # CS[1]n Size 512Mb Window enabled for CS1
 117 +DATA 0xFFD01514 0x00000000      # CS[2]n Size, window disabled
 118 +DATA 0xFFD0151C 0x00000000      # CS[3]n Size, window disabled
 119 +DATA 0xFFD01494 0x00120000      #  DDR ODT Control (Low)
 120 +DATA 0xFFD01498 0x00000000      #  DDR ODT Control (High)
 121 +DATA 0xFFD0149C 0x0000E803      # CPU ODT Control
 122 +
 123 +DATA 0xFFD015D0 0x00000630
 124 +DATA 0xFFD015D4 0x00000046
 125 +DATA 0xFFD015D8 0x00000008
 126 +DATA 0xFFD015DC 0x00000000
 127 +DATA 0xFFD015E0 0x00000023
 128 +DATA 0xFFD015E4 0x00203C18
 129 +DATA 0xFFD01620 0x00384800
 130 +DATA 0xFFD01480 0x00000001
 131 +DATA 0xFFD20134 0x66666666
 132 +DATA 0xFFD20138 0x00066666
 133 +
 134 +#Disable nsa325 hardware watchdog to allow successful kwbooting
 135 +DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog
 136 +DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)
 137 +
 138 +# End of Header extension
 139 +DATA 0x0 0x0
 140 +
 141 --- /dev/null
 142 +++ b/board/zyxel/nsa325/nsa325.c
 143 @@ -0,0 +1,265 @@
 144 +/*
 145 + * Copyright (C) 2015 bodhi <mibodhi@gmail.com>
 146 + *
 147 + * Based on
 148 + * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
 149 + *
 150 + * Based on nsa320.c originall written by
 151 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 152 + *
 153 + * Based on guruplug.c originally written by
 154 + * Siddarth Gore <gores@marvell.com>
 155 + * (C) Copyright 2009
 156 + * Marvell Semiconductor <www.marvell.com>
 157 + *
 158 + * See file CREDITS for list of people who contributed to this
 159 + * project.
 160 + *
 161 + * This program is free software; you can redistribute it and/or
 162 + * modify it under the terms of the GNU General Public License as
 163 + * published by the Free Software Foundation; either version 2 of
 164 + * the License, or (at your option) any later version.
 165 + *
 166 + * This program is distributed in the hope that it will be useful,
 167 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 168 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 169 + * GNU General Public License for more details.
 170 + *
 171 + * You should have received a copy of the GNU General Public License
 172 + * along with this program; if not, write to the Free Software
 173 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 174 + * MA 02110-1301 USA
 175 + */
 176 +
 177 +#include <common.h>
 178 +#include <miiphy.h>
 179 +#include <asm/arch/soc.h>
 180 +#include <asm/arch/mpp.h>
 181 +#include <asm/arch/cpu.h>
 182 +#include <asm/gpio.h>
 183 +#include <asm/io.h>
 184 +#include "nsa325.h"
 185 +#include <asm/arch/gpio.h>
 186 +
 187 +DECLARE_GLOBAL_DATA_PTR;
 188 +
 189 +int board_early_init_f(void)
 190 +{
 191 +       /*
 192 +        * default gpio configuration
 193 +        * There are maximum 64 gpios controlled through 2 sets of registers
 194 +        * the below configuration configures mainly initial LED status
 195 +        */
 196 +       mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
 197 +                      NSA325_OE_LOW, NSA325_OE_HIGH);
 198 +
 199 +       /* Multi-Purpose Pins Functionality configuration */
 200 +       /* (all LEDs & power off active high) */
 201 +       u32 kwmpp_config[] = {
 202 +               MPP0_NF_IO2,
 203 +               MPP1_NF_IO3,
 204 +               MPP2_NF_IO4,
 205 +               MPP3_NF_IO5,
 206 +               MPP4_NF_IO6,
 207 +               MPP5_NF_IO7,
 208 +               MPP6_SYSRST_OUTn,
 209 +               MPP7_GPO,
 210 +               MPP8_TW_SDA,            /* PCF8563 RTC chip   */
 211 +               MPP9_TW_SCK,            /* connected to TWSI  */
 212 +               MPP10_UART0_TXD,
 213 +               MPP11_UART0_RXD,
 214 +               MPP12_GPO,              /* HDD2 LED (green)   */
 215 +               MPP13_GPIO,             /* HDD2 LED (red)     */
 216 +               MPP14_GPIO,             /* MCU DATA pin (in)  */
 217 +               MPP15_GPIO,             /* USB LED (green)    */
 218 +               MPP16_GPIO,             /* MCU CLK pin (out)  */
 219 +               MPP17_GPIO,             /* MCU ACT pin (out)  */
 220 +               MPP18_NF_IO0,
 221 +               MPP19_NF_IO1,
 222 +               MPP20_GPIO,
 223 +               MPP21_GPIO,             /* USB power          */
 224 +               MPP22_GPIO,
 225 +               MPP23_GPIO,
 226 +               MPP24_GPIO,
 227 +               MPP25_GPIO,
 228 +               MPP26_GPIO,
 229 +               MPP27_GPIO,
 230 +               MPP28_GPIO,             /* SYS LED (green)    */
 231 +               MPP29_GPIO,             /* SYS LED (orange)   */
 232 +               MPP30_GPIO,
 233 +               MPP31_GPIO,
 234 +               MPP32_GPIO,
 235 +               MPP33_GPIO,
 236 +               MPP34_GPIO,
 237 +               MPP35_GPIO,
 238 +               MPP36_GPIO,             /* reset button       */
 239 +               MPP37_GPIO,             /* copy button        */
 240 +               MPP38_GPIO,             /* VID B0             */
 241 +               MPP39_GPIO,             /* COPY LED (green)   */
 242 +               MPP40_GPIO,             /* COPY LED (red)     */
 243 +               MPP41_GPIO,             /* HDD1 LED (green)   */
 244 +               MPP42_GPIO,             /* HDD1 LED (red)     */
 245 +               MPP43_GPIO,             /* HTP pin            */
 246 +               MPP44_GPIO,             /* buzzer             */
 247 +               MPP45_GPIO,             /* VID B1             */
 248 +               MPP46_GPIO,             /* power button       */
 249 +               MPP47_GPIO,             /* HDD2 power         */
 250 +               MPP48_GPIO,             /* power off          */
 251 +               0
 252 +       };
 253 +       kirkwood_mpp_conf(kwmpp_config, NULL);
 254 +       return 0;
 255 +}
 256 +
 257 +int board_init(void)
 258 +{
 259 +
 260 +       /* address of boot parameters */
 261 +       gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 262 +
 263 +       /* This disables the hardware watchdog in the mcu on this board. */
 264 +       kw_gpio_set_valid(14, 1);
 265 +       kw_gpio_direction_output(14, 0);
 266 +       kw_gpio_set_value(14, 1);
 267 +
 268 +       return 0;
 269 +}
 270 +
 271 +#ifdef CONFIG_RESET_PHY_R
 272 +/* Configure and enable MV88E1318 PHY */
 273 +void reset_phy(void)
 274 +{
 275 +       u16 reg;
 276 +       u16 devadr;
 277 +       char *name = "egiga0";
 278 +
 279 +       if (miiphy_set_current_dev(name))
 280 +               return;
 281 +
 282 +       /* command to read PHY dev address */
 283 +       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 284 +               printf("Err..%s could not read PHY dev address\n",
 285 +                       __FUNCTION__);
 286 +               return;
 287 +       }
 288 +
 289 +       /* Set RGMII delay */
 290 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
 291 +       miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
 292 +       reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
 293 +       miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
 294 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 295 +
 296 +       /* reset the phy */
 297 +       miiphy_reset(name, devadr);
 298 +
 299 +       /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */
 300 +       /* and has an MCU attached to the LED[2] via tristate interrupt */
 301 +       reg = 0;
 302 +
 303 +       /* switch to LED register page */
 304 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
 305 +       /* read out LED polarity register */
 306 +       miiphy_read(name, devadr, MV88E1318_LED_POL_REG, &reg);
 307 +       /* clear 4, set 5 - LED2 low, tri-state */
 308 +       reg &= ~(MV88E1318_LED2_4);
 309 +       reg |= (MV88E1318_LED2_5);
 310 +       /* write back LED polarity register */
 311 +       miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);
 312 +       /* jump back to page 0, per the PHY chip documenation. */
 313 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 314 +
 315 +       /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */
 316 +       miiphy_write(name, devadr, 0x4, 0x1e1);
 317 +       miiphy_write(name, devadr, 0x9, 0x300);
 318 +       /* Downshift */
 319 +       miiphy_write(name, devadr, 0x10, 0x3860);
 320 +       miiphy_write(name, devadr, 0x0, 0x9140);
 321 +
 322 +       printf("MV88E1318 PHY initialized on %s\n", name);
 323 +
 324 +}
 325 +#endif /* CONFIG_RESET_PHY_R */
 326 +
 327 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
 328 +void show_boot_progress(int val)
 329 +{
 330 +       struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
 331 +       u32 dout0 = readl(&gpio0->dout);
 332 +       u32 blen0 = readl(&gpio0->blink_en);
 333 +
 334 +       struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 335 +       u32 dout1 = readl(&gpio1->dout);
 336 +       u32 blen1 = readl(&gpio1->blink_en);
 337 +
 338 +       switch (val) {
 339 +       case BOOTSTAGE_ID_DECOMP_IMAGE:
 340 +               writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
 341 +               writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
 342 +               break;
 343 +       case BOOTSTAGE_ID_RUN_OS:
 344 +               writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
 345 +               writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
 346 +               break;
 347 +       case BOOTSTAGE_ID_NET_START:
 348 +               writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
 349 +               writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
 350 +               break;
 351 +       case BOOTSTAGE_ID_NET_LOADED:
 352 +               writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
 353 +               writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
 354 +               break;
 355 +       case -BOOTSTAGE_ID_NET_NETLOOP_OK:
 356 +       case -BOOTSTAGE_ID_NET_LOADED:
 357 +               writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
 358 +               writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
 359 +               break;
 360 +       default:
 361 +               if (val < 0) {
 362 +                       /* error */
 363 +                       printf("Error occured, error code = %d\n", -val);
 364 +                       writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
 365 +                       writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
 366 +               }
 367 +               break;
 368 +       }
 369 +}
 370 +#endif
 371 +
 372 +#if defined(CONFIG_KIRKWOOD_GPIO)
 373 +/* Return GPIO button status */
 374 +/*
 375 +un-pressed:
 376 + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )
 377 + gpio-37 (Copy Button  ) in hi (act lo) - IRQ edge (clear )
 378 + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )
 379 +pressed
 380 + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )
 381 + gpio-37 (Copy Button  ) in lo (act hi) - IRQ edge (clear )
 382 + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )
 383 +*/
 384 +
 385 +static int
 386 +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 387 +{
 388 +       if (strcmp(argv[1], "power") == 0) {
 389 +                       kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);
 390 +                       kw_gpio_direction_input(BTN_POWER);
 391 +                       return !kw_gpio_get_value(BTN_POWER);
 392 +       }
 393 +       else if (strcmp(argv[1], "reset") == 0)
 394 +               return kw_gpio_get_value(BTN_RESET);
 395 +       else if (strcmp(argv[1], "copy") == 0)
 396 +               return kw_gpio_get_value(BTN_COPY);
 397 +       else
 398 +               return -1;
 399 +}
 400 +
 401 +
 402 +U_BOOT_CMD(button, 2, 0, do_read_button,
 403 +          "Return GPIO button status 0=off 1=on",
 404 +          "- button power|reset|copy: test buttons states\n"
 405 +);
 406 +
 407 +#endif
 408 +
 409 --- /dev/null
 410 +++ b/board/zyxel/nsa325/nsa325.h
 411 @@ -0,0 +1,77 @@
 412 +/*
 413 + * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
 414 + *
 415 + * Based on nsa320.h originall written by
 416 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 417 + *
 418 + * Based on guruplug.h originally written by
 419 + * Siddarth Gore <gores@marvell.com>
 420 + * (C) Copyright 2009
 421 + * Marvell Semiconductor <www.marvell.com>
 422 + *
 423 + * See file CREDITS for list of people who contributed to this
 424 + * project.
 425 + *
 426 + * This program is free software; you can redistribute it and/or
 427 + * modify it under the terms of the GNU General Public License as
 428 + * published by the Free Software Foundation; either version 2 of
 429 + * the License, or (at your option) any later version.
 430 + *
 431 + * This program is distributed in the hope that it will be useful,
 432 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 433 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 434 + * GNU General Public License for more details.
 435 + *
 436 + * You should have received a copy of the GNU General Public License
 437 + * along with this program; if not, write to the Free Software
 438 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 439 + * MA 02110-1301 USA
 440 + */
 441 +
 442 +#ifndef __NSA325_H
 443 +#define __NSA325_H
 444 +
 445 +/* low GPIO's */
 446 +#define HDD2_GREEN_LED         (1 << 12)
 447 +#define HDD2_RED_LED           (1 << 13)
 448 +#define USB_GREEN_LED          (1 << 15)
 449 +#define USB_POWER              (1 << 21)
 450 +#define SYS_GREEN_LED          (1 << 28)
 451 +#define SYS_ORANGE_LED         (1 << 29)
 452 +
 453 +#define PIN_USB_GREEN_LED      15
 454 +#define PIN_USB_POWER          21
 455 +
 456 +#define NSA325_OE_LOW          (~(HDD2_GREEN_LED | HDD2_RED_LED | \
 457 +                                  USB_GREEN_LED | USB_POWER | \
 458 +                                  SYS_GREEN_LED | SYS_ORANGE_LED))
 459 +#define NSA325_VAL_LOW         (SYS_GREEN_LED | USB_POWER)
 460 +
 461 +/* high GPIO's */
 462 +#define COPY_GREEN_LED         (1 << 7)
 463 +#define COPY_RED_LED           (1 << 8)
 464 +#define HDD1_GREEN_LED         (1 << 9)
 465 +#define HDD1_RED_LED           (1 << 10)
 466 +#define HDD2_POWER          (1 << 15)
 467 +#define WATCHDOG_SIGNAL     (1 << 14)
 468 +
 469 +#define NSA325_OE_HIGH         (~(COPY_GREEN_LED | COPY_RED_LED | \
 470 +                                  HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))
 471 +#define NSA325_VAL_HIGH                (WATCHDOG_SIGNAL | HDD2_POWER)
 472 +
 473 +/* PHY related */
 474 +#define MV88E1318_PGADR_REG            22
 475 +#define MV88E1318_MAC_CTRL_PG  2
 476 +#define MV88E1318_MAC_CTRL_REG 21
 477 +#define MV88E1318_RGMII_TXTM_CTRL      (1 << 4)
 478 +#define MV88E1318_RGMII_RXTM_CTRL      (1 << 5)
 479 +#define MV88E1318_LED_PG        3
 480 +#define MV88E1318_LED_POL_REG  17
 481 +#define MV88E1318_LED2_4           (1 << 4)
 482 +#define MV88E1318_LED2_5           (1 << 5)
 483 +
 484 +#define BTN_POWER                              46
 485 +#define BTN_RESET                              36
 486 +#define BTN_COPY                               37
 487 +
 488 +#endif /* __NSA325_H */
 489 --- /dev/null
 490 +++ b/configs/nsa325_defconfig
 491 @@ -0,0 +1,37 @@
 492 +CONFIG_ARM=y
 493 +CONFIG_KIRKWOOD=y
 494 +CONFIG_SYS_TEXT_BASE=0x600000
 495 +CONFIG_TARGET_NSA325=y
 496 +CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
 497 +CONFIG_BOOTDELAY=3
 498 +CONFIG_SYS_PROMPT="NSA325> "
 499 +# CONFIG_CMD_IMLS is not set
 500 +# CONFIG_CMD_FLASH is not set
 501 +CONFIG_SYS_NS16550=y
 502 +CONFIG_CMD_FDT=y
 503 +CONFIG_OF_LIBFDT=y
 504 +CONFIG_CMD_SETEXPR=y
 505 +CONFIG_CMD_DHCP=y
 506 +CONFIG_CMD_MII=y
 507 +CONFIG_CMD_PING=y
 508 +CONFIG_CMD_DNS=y
 509 +CONFIG_CMD_SNTP=y
 510 +CONFIG_CMD_USB=y
 511 +CONFIG_USB=y
 512 +CONFIG_CMD_DATE=y
 513 +CONFIG_CMD_EXT2=y
 514 +CONFIG_CMD_EXT4=y
 515 +CONFIG_CMD_FAT=y
 516 +CONFIG_CMD_JFFS2=y
 517 +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
 518 +CONFIG_CMD_MTDPARTS=y
 519 +CONFIG_CMD_ENV=y
 520 +CONFIG_CMD_NAND=y
 521 +CONFIG_EFI_PARTITION=y
 522 +CONFIG_ENV_IS_IN_NAND=y
 523 +CONFIG_CMD_UBI=y
 524 +CONFIG_USB_EHCI_HCD=y
 525 +CONFIG_USB_STORAGE=y
 526 +CONFIG_LZMA=y
 527 +CONFIG_LZO=y
 528 +CONFIG_SYS_LONGHELP=y
 529 --- /dev/null
 530 +++ b/include/configs/nsa325.h
 531 @@ -0,0 +1,122 @@
 532 +/*
 533 + * (C) Copyright 2016 bodhi <mibodhi@gmail.com>
 534 + *
 535 + * Based on
 536 + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
 537 + * Based on
 538 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 539 + *
 540 + * Based on guruplug.h originally written by
 541 + * Siddarth Gore <gores@marvell.com>
 542 + * (C) Copyright 2009
 543 + * Marvell Semiconductor <www.marvell.com>
 544 + *
 545 + * See file CREDITS for list of people who contributed to this
 546 + * project.
 547 + *
 548 + * This program is free software; you can redistribute it and/or
 549 + * modify it under the terms of the GNU General Public License as
 550 + * published by the Free Software Foundation; either version 2 of
 551 + * the License, or (at your option) any later version.
 552 + *
 553 + * This program is distributed in the hope that it will be useful,
 554 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 555 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 556 + * GNU General Public License for more details.
 557 + *
 558 + * You should have received a copy of the GNU General Public License
 559 + * along with this program; if not, write to the Free Software
 560 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 561 + * MA 02110-1301 USA
 562 + */
 563 +
 564 +#ifndef _CONFIG_NSA325_H
 565 +#define _CONFIG_NSA325_H
 566 +
 567 +/*
 568 + * High Level Configuration Options (easy to change)
 569 + */
 570 +#define CONFIG_FEROCEON_88FR131        1       /* CPU Core subversion */
 571 +#define CONFIG_KW88F6281       1       /* SOC Name */
 572 +
 573 +#define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 574 +
 575 +/*
 576 + * Misc Configuration Options
 577 + */
 578 +#define CONFIG_SHOW_BOOT_PROGRESS 1    /* boot progess display (LED's) */
 579 +
 580 +/*
 581 + * Commands configuration
 582 + */
 583 +#define CONFIG_PREBOOT
 584 +
 585 +/*
 586 + * mv-common.h should be defined after CMD configs since it used them
 587 + * to enable certain macros
 588 + */
 589 +#include "mv-common.h"
 590 +
 591 +/*
 592 + *  Environment variables configurations
 593 + */
 594 +#ifdef CONFIG_CMD_NAND
 595 +#define CONFIG_ENV_SECT_SIZE           0x20000         /* 128K */
 596 +#endif
 597 +/*
 598 + * max 4k env size is enough, but in case of nand
 599 + * it has to be rounded to sector size
 600 + */
 601 +#define CONFIG_ENV_SIZE                        0x20000         /* 128k */
 602 +#define CONFIG_ENV_ADDR                        0xc0000
 603 +#define CONFIG_ENV_OFFSET              0xc0000 /* env starts here */
 604 +
 605 +/*
 606 + * Default environment variables
 607 + */
 608 +#define CONFIG_BOOTCOMMAND \
 609 +       "ubi part ubi; " \
 610 +       "ubi read 0x800000 kernel; " \
 611 +       "bootm 0x800000"
 612 +
 613 +#define CONFIG_EXTRA_ENV_SETTINGS \
 614 +       "console=console=ttyS0,115200\0"        \
 615 +       "mtdids=nand0=orion_nand\0"             \
 616 +       "mtdparts="CONFIG_MTDPARTS_DEFAULT      \
 617 +       "bootargs_root=\0"
 618 +
 619 +/*
 620 + * Ethernet Driver configuration
 621 + */
 622 +#ifdef CONFIG_CMD_NET
 623 +#define CONFIG_MVGBE_PORTS             {1, 0}  /* enable port 0 only */
 624 +#define CONFIG_PHY_BASE_ADR            0x1
 625 +#define CONFIG_NETCONSOLE
 626 +#endif /* CONFIG_CMD_NET */
 627 +
 628 +/*
 629 + * SATA Driver configuration
 630 + */
 631 +#ifdef CONFIG_MVSATA_IDE
 632 +#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
 633 +#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
 634 +#endif /* CONFIG_MVSATA_IDE */
 635 +
 636 +/*
 637 + * File system
 638 + */
 639 +#define CONFIG_JFFS2_NAND
 640 +#define CONFIG_JFFS2_LZO
 641 +#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 642 +#define CONFIG_MTD_PARTITIONS
 643 +
 644 +/*
 645 + *  Date Time
 646 + */
 647 +#ifdef CONFIG_CMD_DATE
 648 +#define CONFIG_RTC_MV
 649 +#endif /* CONFIG_CMD_DATE */
 650 +
 651 +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
 652 +
 653 +#endif /* _CONFIG_NSA325_H */