package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch

   1 --- /dev/null
   2 +++ b/board/arcadyan/arv8539pw22/Makefile
   3 @@ -0,0 +1,28 @@
   4 +#
   5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
   6 +#
   7 +# SPDX-License-Identifier:     GPL-2.0+
   8 +#
   9 +
  10 +include $(TOPDIR)/config.mk
  11 +
  12 +LIB    = $(obj)lib$(BOARD).o
  13 +
  14 +COBJS  = $(BOARD).o
  15 +
  16 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  17 +OBJS   := $(addprefix $(obj),$(COBJS))
  18 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  19 +
  20 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  21 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  22 +
  23 +#########################################################################
  24 +
  25 +# defines $(obj).depend target
  26 +include $(SRCTREE)/rules.mk
  27 +
  28 +sinclude $(obj).depend
  29 +
  30 +#########################################################################
  31 +
  32 --- /dev/null
  33 +++ b/board/arcadyan/arv8539pw22/arv8539pw22.c
  34 @@ -0,0 +1,53 @@
  35 +/*
  36 + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
  37 + * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
  38 + *
  39 + * SPDX-License-Identifier:    GPL-2.0+
  40 + */
  41 +
  42 +#include <common.h>
  43 +#include <switch.h>
  44 +#include <asm/gpio.h>
  45 +#include <asm/lantiq/eth.h>
  46 +#include <asm/lantiq/reset.h>
  47 +#include <asm/lantiq/chipid.h>
  48 +
  49 +int board_early_init_f(void)
  50 +{
  51 +       return 0;
  52 +}
  53 +
  54 +int checkboard(void)
  55 +{
  56 +       puts("Board: " CONFIG_BOARD_NAME "\n");
  57 +       ltq_chip_print_info();
  58 +
  59 +       return 0;
  60 +}
  61 +
  62 +static const struct ltq_eth_port_config eth_port_config[] = {
  63 +       /* MAC0: Atheros ar8216 switch */
  64 +       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
  65 +};
  66 +
  67 +static const struct ltq_eth_board_config eth_board_config = {
  68 +       .ports = eth_port_config,
  69 +       .num_ports = ARRAY_SIZE(eth_port_config),
  70 +};
  71 +
  72 +int board_eth_init(bd_t *bis)
  73 +{
  74 +       return ltq_eth_initialize(&eth_board_config);
  75 +}
  76 +
  77 +static struct switch_device ar8216_dev = {
  78 +       .name = "ar8216",
  79 +       .cpu_port = 0,
  80 +       .port_mask = 0xF,
  81 +};
  82 +
  83 +int board_switch_init(void)
  84 +{
  85 +       return switch_device_register(&ar8216_dev);
  86 +}
  87 +
  88 --- /dev/null
  89 +++ b/board/arcadyan/arv8539pw22/config.mk
  90 @@ -0,0 +1,8 @@
  91 +#
  92 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
  93 +#
  94 +# SPDX-License-Identifier:     GPL-2.0+
  95 +#
  96 +
  97 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
  98 +
  99 --- /dev/null
 100 +++ b/board/arcadyan/arv8539pw22/ddr_settings.h
 101 @@ -0,0 +1,55 @@
 102 +/*
 103 + * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
 104 + *
 105 + * This file has been generated with lantiq_ram_extract_magic.awk script.
 106 + *
 107 + * SPDX-License-Identifier:    GPL-2.0+
 108 + */
 109 +
 110 +#define MC_DC00_VALUE  0x1B1B
 111 +#define MC_DC01_VALUE  0x0
 112 +#define MC_DC02_VALUE  0x0
 113 +#define MC_DC03_VALUE  0x0
 114 +#define MC_DC04_VALUE  0x0
 115 +#define MC_DC05_VALUE  0x200
 116 +#define MC_DC06_VALUE  0x605
 117 +#define MC_DC07_VALUE  0x303
 118 +#define MC_DC08_VALUE  0x102
 119 +#define MC_DC09_VALUE  0x70A
 120 +#define MC_DC10_VALUE  0x203
 121 +#define MC_DC11_VALUE  0xC02
 122 +#define MC_DC12_VALUE  0x1C8
 123 +#define MC_DC13_VALUE  0x1
 124 +#define MC_DC14_VALUE  0x0
 125 +#define MC_DC15_VALUE  0x134
 126 +#define MC_DC16_VALUE  0xC800
 127 +#define MC_DC17_VALUE  0xD
 128 +#define MC_DC18_VALUE  0x301
 129 +#define MC_DC19_VALUE  0x200
 130 +#define MC_DC20_VALUE  0xA03
 131 +#define MC_DC21_VALUE  0x1400
 132 +#define MC_DC22_VALUE  0x1414
 133 +#define MC_DC23_VALUE  0x0
 134 +#define MC_DC24_VALUE  0x5B
 135 +#define MC_DC25_VALUE  0x0
 136 +#define MC_DC26_VALUE  0x0
 137 +#define MC_DC27_VALUE  0x0
 138 +#define MC_DC28_VALUE  0x510
 139 +#define MC_DC29_VALUE  0x4E20
 140 +#define MC_DC30_VALUE  0x8235
 141 +#define MC_DC31_VALUE  0x0
 142 +#define MC_DC32_VALUE  0x0
 143 +#define MC_DC33_VALUE  0x0
 144 +#define MC_DC34_VALUE  0x0
 145 +#define MC_DC35_VALUE  0x0
 146 +#define MC_DC36_VALUE  0x0
 147 +#define MC_DC37_VALUE  0x0
 148 +#define MC_DC38_VALUE  0x0
 149 +#define MC_DC39_VALUE  0x0
 150 +#define MC_DC40_VALUE  0x0
 151 +#define MC_DC41_VALUE  0x0
 152 +#define MC_DC42_VALUE  0x0
 153 +#define MC_DC43_VALUE  0x0
 154 +#define MC_DC44_VALUE  0x0
 155 +#define MC_DC45_VALUE  0x500
 156 +#define MC_DC46_VALUE  0x0
 157 --- a/boards.cfg
 158 +++ b/boards.cfg
 159 @@ -520,6 +520,9 @@ Active  mips        mips32         danub
 160  Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_brn                      arv752dpw22:SYS_BOOT_BRN                                                                                                          -
 161  Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_nor                      arv752dpw22:SYS_BOOT_NOR                                                                                                          -
 162  Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_ram                      arv752dpw22:SYS_BOOT_RAM                                                                                                          -
 163 +Active  mips        mips32         danube      arcadyan        arv8539pw22         arv8539pw22_brn                      arv8539pw22:SYS_BOOT_BRN                                                                                                          -
 164 +Active  mips        mips32         danube      arcadyan        arv8539pw22         arv8539pw22_nor                      arv8539pw22:SYS_BOOT_NOR                                                                                                          -
 165 +Active  mips        mips32         danube      arcadyan        arv8539pw22         arv8539pw22_ram                      arv8539pw22:SYS_BOOT_RAM                                                                                                          -
 166  Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>
 167  Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>
 168  Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <luka@openwrt.org>
 169 --- /dev/null
 170 +++ b/include/configs/arv8539pw22.h
 171 @@ -0,0 +1,70 @@
 172 +/*
 173 + * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
 174 + *
 175 + * SPDX-License-Identifier:    GPL-2.0+
 176 + */
 177 +
 178 +#ifndef __CONFIG_H
 179 +#define __CONFIG_H
 180 +
 181 +#define CONFIG_MACH_TYPE       "ARV8539PW22"
 182 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 183 +#define CONFIG_BOARD_NAME      "Speedport W 504V Typ A"
 184 +
 185 +/* Configure SoC */
 186 +#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */
 187 +
 188 +#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */
 189 +
 190 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */
 191 +
 192 +#define CONFIG_SYS_BOOTM_LEN           0x1000000       /* 16 MB */
 193 +
 194 +/* Switch devices */
 195 +#define CONFIG_SWITCH_MULTI
 196 +#define CONFIG_SWITCH_AR8216
 197 +
 198 +/* Environment */
 199 +#if defined(CONFIG_SYS_BOOT_NOR)
 200 +#define CONFIG_ENV_IS_IN_FLASH
 201 +#define CONFIG_ENV_OVERWRITE
 202 +#define CONFIG_ENV_OFFSET              (192 * 1024)
 203 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 204 +#else
 205 +#define CONFIG_ENV_IS_NOWHERE
 206 +#endif
 207 +
 208 +#define CONFIG_ENV_SIZE                        (8 * 1024)
 209 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 210 +
 211 +/* Burnboot loadable image */
 212 +#if defined(CONFIG_SYS_BOOT_BRN)
 213 +#define CONFIG_SYS_TEXT_BASE           0x80002000
 214 +#define CONFIG_SKIP_LOWLEVEL_INIT
 215 +#define CONFIG_SYS_DISABLE_CACHE
 216 +#define CONFIG_ENV_OVERWRITE 1
 217 +#endif
 218 +
 219 +
 220 +/* Console */
 221 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 222 +#define CONFIG_BAUDRATE                        115200
 223 +#define CONFIG_CONSOLE_ASC             1
 224 +#define CONFIG_CONSOLE_DEV             "ttyS1"
 225 +
 226 +/* Pull in default board configs for Lantiq XWAY Danube */
 227 +#include <asm/lantiq/config.h>
 228 +#include <asm/arch/config.h>
 229 +
 230 +/* Pull in default OpenWrt configs for Lantiq SoC */
 231 +#include "openwrt-lantiq-common.h"
 232 +
 233 +#define CONFIG_ENV_UPDATE_UBOOT_NOR            \
 234 +       "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 235 +
 236 +#define CONFIG_EXTRA_ENV_SETTINGS      \
 237 +       CONFIG_ENV_LANTIQ_DEFAULTS      \
 238 +       CONFIG_ENV_UPDATE_UBOOT_NOR     \
 239 +       "kernel_addr=0xB0040000\0"
 240 +
 241 +#endif /* __CONFIG_H */