package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch

   1 From ab3f81920b4e47bd2894388540363700d5b1e59c Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 29 Jul 2022 15:26:31 +0800
   4 Subject: [PATCH 03/31] board: mediatek: add MT7986 reference boards
   5
   6 Add general board files based on MT7986 SoCs.
   7
   8 MT7986 uses one mmc controller for booting from both SD and eMMC.
   9 Both MT7986A and MT7986B use the same pins for spi controller.
  10
  11 Configs for various boot types:
  12 1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B
  13 2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only
  14 3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only
  15
  16 Reviewed-by: Simon Glass <sjg@chromium.org>
  17 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  18 ---
  19  arch/arm/dts/Makefile                |   6 +
  20  arch/arm/dts/mt7986a-emmc-rfb.dts    |  16 ++
  21  arch/arm/dts/mt7986a-rfb.dts         | 218 +++++++++++++++++++++++++++
  22  arch/arm/dts/mt7986a-sd-rfb.dts      | 177 ++++++++++++++++++++++
  23  arch/arm/dts/mt7986b-emmc-rfb.dts    |  16 ++
  24  arch/arm/dts/mt7986b-rfb.dts         | 204 +++++++++++++++++++++++++
  25  arch/arm/dts/mt7986b-sd-rfb.dts      | 173 +++++++++++++++++++++
  26  board/mediatek/mt7986/MAINTAINERS    |  10 ++
  27  board/mediatek/mt7986/Makefile       |   3 +
  28  board/mediatek/mt7986/mt7986_rfb.c   |  10 ++
  29  configs/mt7986_rfb_defconfig         |  66 ++++++++
  30  configs/mt7986a_bpir3_emmc_defconfig |  64 ++++++++
  31  configs/mt7986a_bpir3_sd_defconfig   |  64 ++++++++
  32  include/configs/mt7986.h             |  26 ++++
  33  14 files changed, 1053 insertions(+)
  34  create mode 100644 arch/arm/dts/mt7986a-emmc-rfb.dts
  35  create mode 100644 arch/arm/dts/mt7986a-rfb.dts
  36  create mode 100644 arch/arm/dts/mt7986a-sd-rfb.dts
  37  create mode 100644 arch/arm/dts/mt7986b-emmc-rfb.dts
  38  create mode 100644 arch/arm/dts/mt7986b-rfb.dts
  39  create mode 100644 arch/arm/dts/mt7986b-sd-rfb.dts
  40  create mode 100644 board/mediatek/mt7986/MAINTAINERS
  41  create mode 100644 board/mediatek/mt7986/Makefile
  42  create mode 100644 board/mediatek/mt7986/mt7986_rfb.c
  43  create mode 100644 configs/mt7986_rfb_defconfig
  44  create mode 100644 configs/mt7986a_bpir3_emmc_defconfig
  45  create mode 100644 configs/mt7986a_bpir3_sd_defconfig
  46  create mode 100644 include/configs/mt7986.h
  47
  48 --- a/arch/arm/dts/Makefile
  49 +++ b/arch/arm/dts/Makefile
  50 @@ -1205,6 +1205,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  51         mt7622-bananapi-bpi-r64.dtb \
  52         mt7623n-bananapi-bpi-r2.dtb \
  53         mt7629-rfb.dtb \
  54 +       mt7986a-rfb.dtb \
  55 +       mt7986b-rfb.dtb \
  56 +       mt7986a-sd-rfb.dtb \
  57 +       mt7986b-sd-rfb.dtb \
  58 +       mt7986a-emmc-rfb.dtb \
  59 +       mt7986b-emmc-rfb.dtb \
  60         mt8183-pumpkin.dtb \
  61         mt8512-bm1-emmc.dtb \
  62         mt8516-pumpkin.dtb \
  63 --- /dev/null
  64 +++ b/arch/arm/dts/mt7986a-emmc-rfb.dts
  65 @@ -0,0 +1,16 @@
  66 +// SPDX-License-Identifier: GPL-2.0
  67 +/*
  68 + * Copyright (c) 2022 MediaTek Inc.
  69 + * Author: Sam Shih <sam.shih@mediatek.com>
  70 + */
  71 +
  72 +/dts-v1/;
  73 +#include "mt7986a-rfb.dts"
  74 +
  75 +/ {
  76 +       compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
  77 +                    "mediatek,mt7986-emmc-rfb";
  78 +       bl2_verify {
  79 +               bl2_compatible = "emmc";
  80 +       };
  81 +};
  82 --- /dev/null
  83 +++ b/arch/arm/dts/mt7986a-rfb.dts
  84 @@ -0,0 +1,218 @@
  85 +// SPDX-License-Identifier: GPL-2.0
  86 +/*
  87 + * Copyright (c) 2022 MediaTek Inc.
  88 + * Author: Sam Shih <sam.shih@mediatek.com>
  89 + */
  90 +
  91 +/dts-v1/;
  92 +#include "mt7986.dtsi"
  93 +#include <dt-bindings/gpio/gpio.h>
  94 +
  95 +/ {
  96 +       #address-cells = <1>;
  97 +       #size-cells = <1>;
  98 +       model = "mt7986-rfb";
  99 +       compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
 100 +       chosen {
 101 +               stdout-path = &uart0;
 102 +               tick-timer = &timer0;
 103 +       };
 104 +
 105 +       reg_1p8v: regulator-1p8v {
 106 +               compatible = "regulator-fixed";
 107 +               regulator-name = "fixed-1.8V";
 108 +               regulator-min-microvolt = <1800000>;
 109 +               regulator-max-microvolt = <1800000>;
 110 +               regulator-boot-on;
 111 +               regulator-always-on;
 112 +       };
 113 +
 114 +       reg_3p3v: regulator-3p3v {
 115 +               compatible = "regulator-fixed";
 116 +               regulator-name = "fixed-3.3V";
 117 +               regulator-min-microvolt = <3300000>;
 118 +               regulator-max-microvolt = <3300000>;
 119 +               regulator-boot-on;
 120 +               regulator-always-on;
 121 +       };
 122 +};
 123 +
 124 +&uart0 {
 125 +       status = "okay";
 126 +};
 127 +
 128 +&uart1 {
 129 +       pinctrl-names = "default";
 130 +       pinctrl-0 = <&uart1_pins>;
 131 +       status = "disabled";
 132 +};
 133 +
 134 +&eth {
 135 +       status = "okay";
 136 +       mediatek,gmac-id = <0>;
 137 +       phy-mode = "sgmii";
 138 +       mediatek,switch = "mt7531";
 139 +       reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 140 +
 141 +       fixed-link {
 142 +               speed = <1000>;
 143 +               full-duplex;
 144 +       };
 145 +};
 146 +
 147 +&pinctrl {
 148 +       spi_flash_pins: spi0-pins-func-1 {
 149 +               mux {
 150 +                       function = "flash";
 151 +                       groups = "spi0", "spi0_wp_hold";
 152 +               };
 153 +
 154 +               conf-pu {
 155 +                       pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 156 +                       drive-strength = <MTK_DRIVE_8mA>;
 157 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 158 +               };
 159 +
 160 +               conf-pd {
 161 +                       pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 162 +                       drive-strength = <MTK_DRIVE_8mA>;
 163 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 164 +               };
 165 +       };
 166 +
 167 +       snfi_pins: snfi-pins-func-1 {
 168 +               mux {
 169 +                       function = "flash";
 170 +                       groups = "snfi";
 171 +               };
 172 +
 173 +               clk {
 174 +                       pins = "SPI0_CLK";
 175 +                       drive-strength = <MTK_DRIVE_8mA>;
 176 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 177 +               };
 178 +
 179 +               conf-pu {
 180 +                       pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 181 +                       drive-strength = <MTK_DRIVE_6mA>;
 182 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
 183 +               };
 184 +
 185 +               conf-pd {
 186 +                       pins = "SPI0_MOSI", "SPI0_MISO";
 187 +                       drive-strength = <MTK_DRIVE_6mA>;
 188 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 189 +               };
 190 +       };
 191 +
 192 +       spic_pins: spi1-pins-func-1 {
 193 +               mux {
 194 +                       function = "spi";
 195 +                       groups = "spi1_2";
 196 +               };
 197 +       };
 198 +
 199 +       uart1_pins: spi1-pins-func-3 {
 200 +               mux {
 201 +                       function = "uart";
 202 +                       groups = "uart1_2";
 203 +               };
 204 +       };
 205 +
 206 +       pwm_pins: pwm0-pins-func-1 {
 207 +               mux {
 208 +                       function = "pwm";
 209 +                       groups = "pwm0";
 210 +               };
 211 +       };
 212 +
 213 +       mmc0_pins_default: mmc0default {
 214 +               mux {
 215 +                       function = "flash";
 216 +                       groups =  "emmc_51";
 217 +               };
 218 +
 219 +               conf-cmd-dat {
 220 +                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 221 +                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 222 +                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 223 +                       input-enable;
 224 +                       drive-strength = <MTK_DRIVE_4mA>;
 225 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 226 +               };
 227 +
 228 +               conf-clk {
 229 +                       pins = "EMMC_CK";
 230 +                       drive-strength = <MTK_DRIVE_6mA>;
 231 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 232 +               };
 233 +
 234 +               conf-dsl {
 235 +                       pins = "EMMC_DSL";
 236 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 237 +               };
 238 +
 239 +               conf-rst {
 240 +                       pins = "EMMC_RSTB";
 241 +                       drive-strength = <MTK_DRIVE_4mA>;
 242 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 243 +               };
 244 +       };
 245 +};
 246 +
 247 +&snand {
 248 +       pinctrl-names = "default";
 249 +       pinctrl-0 = <&snfi_pins>;
 250 +       status = "okay";
 251 +       quad-spi;
 252 +};
 253 +
 254 +&spi0 {
 255 +       #address-cells = <1>;
 256 +       #size-cells = <0>;
 257 +       pinctrl-names = "default";
 258 +       pinctrl-0 = <&spi_flash_pins>;
 259 +       status = "okay";
 260 +       must_tx;
 261 +       enhance_timing;
 262 +       dma_ext;
 263 +       ipm_design;
 264 +       support_quad;
 265 +       tick_dly = <2>;
 266 +       sample_sel = <0>;
 267 +
 268 +       spi_nor@0 {
 269 +               compatible = "jedec,spi-nor";
 270 +               reg = <0>;
 271 +               spi-max-frequency = <52000000>;
 272 +       };
 273 +
 274 +       spi_nand@1 {
 275 +               compatible = "spi-nand";
 276 +               reg = <1>;
 277 +               spi-max-frequency = <52000000>;
 278 +       };
 279 +};
 280 +
 281 +&pwm {
 282 +       pinctrl-names = "default";
 283 +       pinctrl-0 = <&pwm_pins>;
 284 +       status = "okay";
 285 +};
 286 +
 287 +&watchdog {
 288 +       status = "disabled";
 289 +};
 290 +
 291 +&mmc0 {
 292 +       pinctrl-names = "default";
 293 +       pinctrl-0 = <&mmc0_pins_default>;
 294 +       bus-width = <8>;
 295 +       max-frequency = <52000000>;
 296 +       cap-mmc-highspeed;
 297 +       cap-mmc-hw-reset;
 298 +       vmmc-supply = <&reg_3p3v>;
 299 +       vqmmc-supply = <&reg_1p8v>;
 300 +       non-removable;
 301 +       status = "okay";
 302 +};
 303 --- /dev/null
 304 +++ b/arch/arm/dts/mt7986a-sd-rfb.dts
 305 @@ -0,0 +1,177 @@
 306 +// SPDX-License-Identifier: GPL-2.0
 307 +/*
 308 + * Copyright (c) 2022 MediaTek Inc.
 309 + * Author: Sam Shih <sam.shih@mediatek.com>
 310 + */
 311 +
 312 +/dts-v1/;
 313 +#include "mt7986.dtsi"
 314 +#include <dt-bindings/gpio/gpio.h>
 315 +
 316 +/ {
 317 +       #address-cells = <1>;
 318 +       #size-cells = <1>;
 319 +       model = "mt7986-rfb";
 320 +       compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
 321 +                    "mediatek,mt7986-sd-rfb";
 322 +       chosen {
 323 +               stdout-path = &uart0;
 324 +               tick-timer = &timer0;
 325 +       };
 326 +
 327 +       reg_3p3v: regulator-3p3v {
 328 +               compatible = "regulator-fixed";
 329 +               regulator-name = "fixed-3.3V";
 330 +               regulator-min-microvolt = <3300000>;
 331 +               regulator-max-microvolt = <3300000>;
 332 +               regulator-boot-on;
 333 +               regulator-always-on;
 334 +       };
 335 +};
 336 +
 337 +&uart0 {
 338 +       status = "okay";
 339 +};
 340 +
 341 +&uart1 {
 342 +       pinctrl-names = "default";
 343 +       pinctrl-0 = <&uart1_pins>;
 344 +       status = "disabled";
 345 +};
 346 +
 347 +&eth {
 348 +       status = "okay";
 349 +       mediatek,gmac-id = <0>;
 350 +       phy-mode = "sgmii";
 351 +       mediatek,switch = "mt7531";
 352 +       reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 353 +
 354 +       fixed-link {
 355 +               speed = <1000>;
 356 +               full-duplex;
 357 +       };
 358 +};
 359 +
 360 +&pinctrl {
 361 +       spi_flash_pins: spi0-pins-func-1 {
 362 +               mux {
 363 +                       function = "flash";
 364 +                       groups = "spi0", "spi0_wp_hold";
 365 +               };
 366 +
 367 +               conf-pu {
 368 +                       pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 369 +                       drive-strength = <MTK_DRIVE_8mA>;
 370 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 371 +               };
 372 +
 373 +               conf-pd {
 374 +                       pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 375 +                       drive-strength = <MTK_DRIVE_8mA>;
 376 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 377 +               };
 378 +       };
 379 +
 380 +       spic_pins: spi1-pins-func-1 {
 381 +               mux {
 382 +                       function = "spi";
 383 +                       groups = "spi1_2";
 384 +               };
 385 +       };
 386 +
 387 +       uart1_pins: spi1-pins-func-3 {
 388 +               mux {
 389 +                       function = "uart";
 390 +                       groups = "uart1_2";
 391 +               };
 392 +       };
 393 +
 394 +       pwm_pins: pwm0-pins-func-1 {
 395 +               mux {
 396 +                       function = "pwm";
 397 +                       groups = "pwm0";
 398 +               };
 399 +       };
 400 +
 401 +       mmc0_pins_default: mmc0default {
 402 +               mux {
 403 +                       function = "flash";
 404 +                       groups =  "emmc_51";
 405 +               };
 406 +
 407 +               conf-cmd-dat {
 408 +                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 409 +                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 410 +                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 411 +                       input-enable;
 412 +                       drive-strength = <MTK_DRIVE_4mA>;
 413 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 414 +               };
 415 +
 416 +               conf-clk {
 417 +                       pins = "EMMC_CK";
 418 +                       drive-strength = <MTK_DRIVE_6mA>;
 419 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 420 +               };
 421 +
 422 +               conf-dsl {
 423 +                       pins = "EMMC_DSL";
 424 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 425 +               };
 426 +
 427 +               conf-rst {
 428 +                       pins = "EMMC_RSTB";
 429 +                       drive-strength = <MTK_DRIVE_4mA>;
 430 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 431 +               };
 432 +       };
 433 +};
 434 +
 435 +&spi0 {
 436 +       #address-cells = <1>;
 437 +       #size-cells = <0>;
 438 +       pinctrl-names = "default";
 439 +       pinctrl-0 = <&spi_flash_pins>;
 440 +       status = "okay";
 441 +       must_tx;
 442 +       enhance_timing;
 443 +       dma_ext;
 444 +       ipm_design;
 445 +       support_quad;
 446 +       tick_dly = <2>;
 447 +       sample_sel = <0>;
 448 +
 449 +       spi_nor@0 {
 450 +               compatible = "jedec,spi-nor";
 451 +               reg = <0>;
 452 +               spi-max-frequency = <52000000>;
 453 +       };
 454 +
 455 +       spi_nand@1 {
 456 +               compatible = "spi-nand";
 457 +               reg = <1>;
 458 +               spi-max-frequency = <52000000>;
 459 +       };
 460 +};
 461 +
 462 +&pwm {
 463 +       pinctrl-names = "default";
 464 +       pinctrl-0 = <&pwm_pins>;
 465 +       status = "okay";
 466 +};
 467 +
 468 +&watchdog {
 469 +       status = "disabled";
 470 +};
 471 +
 472 +&mmc0 {
 473 +       pinctrl-names = "default";
 474 +       pinctrl-0 = <&mmc0_pins_default>;
 475 +       bus-width = <4>;
 476 +       max-frequency = <52000000>;
 477 +       cap-sd-highspeed;
 478 +       r_smpl = <1>;
 479 +       vmmc-supply = <&reg_3p3v>;
 480 +       vqmmc-supply = <&reg_3p3v>;
 481 +       status = "okay";
 482 +};
 483 --- /dev/null
 484 +++ b/arch/arm/dts/mt7986b-emmc-rfb.dts
 485 @@ -0,0 +1,16 @@
 486 +// SPDX-License-Identifier: GPL-2.0
 487 +/*
 488 + * Copyright (c) 2022 MediaTek Inc.
 489 + * Author: Sam Shih <sam.shih@mediatek.com>
 490 + */
 491 +
 492 +/dts-v1/;
 493 +#include "mt7986a-rfb.dts"
 494 +
 495 +/ {
 496 +       compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
 497 +                    "mediatek,mt7986-emmc-rfb";
 498 +       bl2_verify {
 499 +               bl2_compatible = "emmc";
 500 +       };
 501 +};
 502 --- /dev/null
 503 +++ b/arch/arm/dts/mt7986b-rfb.dts
 504 @@ -0,0 +1,204 @@
 505 +// SPDX-License-Identifier: GPL-2.0
 506 +/*
 507 + * Copyright (c) 2022 MediaTek Inc.
 508 + * Author: Sam Shih <sam.shih@mediatek.com>
 509 + */
 510 +
 511 +/dts-v1/;
 512 +#include "mt7986.dtsi"
 513 +#include <dt-bindings/gpio/gpio.h>
 514 +
 515 +/ {
 516 +       #address-cells = <1>;
 517 +       #size-cells = <1>;
 518 +       model = "mt7986-rfb";
 519 +       compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
 520 +       chosen {
 521 +               stdout-path = &uart0;
 522 +               tick-timer = &timer0;
 523 +       };
 524 +
 525 +       reg_3p3v: regulator-3p3v {
 526 +               compatible = "regulator-fixed";
 527 +               regulator-name = "fixed-3.3V";
 528 +               regulator-min-microvolt = <3300000>;
 529 +               regulator-max-microvolt = <3300000>;
 530 +               regulator-boot-on;
 531 +               regulator-always-on;
 532 +       };
 533 +};
 534 +
 535 +&uart0 {
 536 +       status = "okay";
 537 +};
 538 +
 539 +&uart1 {
 540 +       pinctrl-names = "default";
 541 +       pinctrl-0 = <&uart1_pins>;
 542 +       status = "disabled";
 543 +};
 544 +
 545 +&eth {
 546 +       status = "okay";
 547 +       mediatek,gmac-id = <0>;
 548 +       phy-mode = "sgmii";
 549 +       mediatek,switch = "mt7531";
 550 +       reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 551 +
 552 +       fixed-link {
 553 +               speed = <1000>;
 554 +               full-duplex;
 555 +       };
 556 +};
 557 +
 558 +&pinctrl {
 559 +       spi_flash_pins: spi0-pins-func-1 {
 560 +               mux {
 561 +                       function = "flash";
 562 +                       groups = "spi0", "spi0_wp_hold";
 563 +               };
 564 +
 565 +               conf-pu {
 566 +                       pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 567 +                       drive-strength = <MTK_DRIVE_8mA>;
 568 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 569 +               };
 570 +
 571 +               conf-pd {
 572 +                       pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 573 +                       drive-strength = <MTK_DRIVE_8mA>;
 574 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 575 +               };
 576 +       };
 577 +
 578 +       snfi_pins: snfi-pins-func-1 {
 579 +               mux {
 580 +                       function = "flash";
 581 +                       groups = "snfi";
 582 +               };
 583 +
 584 +               clk {
 585 +                       pins = "SPI0_CLK";
 586 +                       drive-strength = <MTK_DRIVE_8mA>;
 587 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 588 +               };
 589 +
 590 +               conf-pu {
 591 +                       pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 592 +                       drive-strength = <MTK_DRIVE_6mA>;
 593 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
 594 +               };
 595 +
 596 +               conf-pd {
 597 +                       pins = "SPI0_MOSI", "SPI0_MISO";
 598 +                       drive-strength = <MTK_DRIVE_6mA>;
 599 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 600 +               };
 601 +       };
 602 +
 603 +       spic_pins: spi1-pins-func-1 {
 604 +               mux {
 605 +                       function = "spi";
 606 +                       groups = "spi1_2";
 607 +               };
 608 +       };
 609 +
 610 +       uart1_pins: spi1-pins-func-3 {
 611 +               mux {
 612 +                       function = "uart";
 613 +                       groups = "uart1_2";
 614 +               };
 615 +       };
 616 +
 617 +       pwm_pins: pwm0-pins-func-1 {
 618 +               mux {
 619 +                       function = "pwm";
 620 +                       groups = "pwm0";
 621 +               };
 622 +       };
 623 +
 624 +       mmc0_pins_default: mmc0default {
 625 +               mux {
 626 +                       function = "flash";
 627 +                       groups =  "emmc_45";
 628 +                       input-schmitt-enable;
 629 +               };
 630 +
 631 +               conf-cmd-dat {
 632 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
 633 +                              "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
 634 +                              "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
 635 +                       input-enable;
 636 +                       drive-strength = <MTK_DRIVE_4mA>;
 637 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 638 +               };
 639 +
 640 +               conf-clk {
 641 +                       pins = "SPI1_CS";
 642 +                       drive-strength = <MTK_DRIVE_6mA>;
 643 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 644 +               };
 645 +
 646 +               conf-rst {
 647 +                       pins = "PWM1";
 648 +                       drive-strength = <MTK_DRIVE_4mA>;
 649 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 650 +               };
 651 +       };
 652 +};
 653 +
 654 +&snand {
 655 +       pinctrl-names = "default";
 656 +       pinctrl-0 = <&snfi_pins>;
 657 +       status = "okay";
 658 +       quad-spi;
 659 +};
 660 +
 661 +&spi0 {
 662 +       #address-cells = <1>;
 663 +       #size-cells = <0>;
 664 +       pinctrl-names = "default";
 665 +       pinctrl-0 = <&spi_flash_pins>;
 666 +       status = "okay";
 667 +       must_tx;
 668 +       enhance_timing;
 669 +       dma_ext;
 670 +       ipm_design;
 671 +       support_quad;
 672 +       tick_dly = <2>;
 673 +       sample_sel = <0>;
 674 +
 675 +       spi_nor@0 {
 676 +               compatible = "jedec,spi-nor";
 677 +               reg = <0>;
 678 +               spi-max-frequency = <52000000>;
 679 +       };
 680 +
 681 +       spi_nand@1 {
 682 +               compatible = "spi-nand";
 683 +               reg = <1>;
 684 +               spi-max-frequency = <52000000>;
 685 +       };
 686 +};
 687 +
 688 +&pwm {
 689 +       pinctrl-names = "default";
 690 +       pinctrl-0 = <&pwm_pins>;
 691 +       status = "okay";
 692 +};
 693 +
 694 +&watchdog {
 695 +       status = "disabled";
 696 +};
 697 +
 698 +&mmc0 {
 699 +       pinctrl-names = "default";
 700 +       pinctrl-0 = <&mmc0_pins_default>;
 701 +       bus-width = <8>;
 702 +       max-frequency = <52000000>;
 703 +       cap-mmc-highspeed;
 704 +       cap-mmc-hw-reset;
 705 +       vmmc-supply = <&reg_3p3v>;
 706 +       non-removable;
 707 +       status = "okay";
 708 +};
 709 --- /dev/null
 710 +++ b/arch/arm/dts/mt7986b-sd-rfb.dts
 711 @@ -0,0 +1,173 @@
 712 +// SPDX-License-Identifier: GPL-2.0
 713 +/*
 714 + * Copyright (c) 2022 MediaTek Inc.
 715 + * Author: Sam Shih <sam.shih@mediatek.com>
 716 + */
 717 +
 718 +/dts-v1/;
 719 +#include "mt7986.dtsi"
 720 +#include <dt-bindings/gpio/gpio.h>
 721 +
 722 +/ {
 723 +       #address-cells = <1>;
 724 +       #size-cells = <1>;
 725 +       model = "mt7986-rfb";
 726 +       compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
 727 +                    "mediatek,mt7986-sd-rfb";
 728 +       chosen {
 729 +               stdout-path = &uart0;
 730 +               tick-timer = &timer0;
 731 +       };
 732 +
 733 +       reg_3p3v: regulator-3p3v {
 734 +               compatible = "regulator-fixed";
 735 +               regulator-name = "fixed-3.3V";
 736 +               regulator-min-microvolt = <3300000>;
 737 +               regulator-max-microvolt = <3300000>;
 738 +               regulator-boot-on;
 739 +               regulator-always-on;
 740 +       };
 741 +};
 742 +
 743 +&uart0 {
 744 +       status = "okay";
 745 +};
 746 +
 747 +&uart1 {
 748 +       pinctrl-names = "default";
 749 +       pinctrl-0 = <&uart1_pins>;
 750 +       status = "disabled";
 751 +};
 752 +
 753 +&eth {
 754 +       status = "okay";
 755 +       mediatek,gmac-id = <0>;
 756 +       phy-mode = "sgmii";
 757 +       mediatek,switch = "mt7531";
 758 +       reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 759 +
 760 +       fixed-link {
 761 +               speed = <1000>;
 762 +               full-duplex;
 763 +       };
 764 +};
 765 +
 766 +&pinctrl {
 767 +       spi_flash_pins: spi0-pins-func-1 {
 768 +               mux {
 769 +                       function = "flash";
 770 +                       groups = "spi0", "spi0_wp_hold";
 771 +               };
 772 +
 773 +               conf-pu {
 774 +                       pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 775 +                       drive-strength = <MTK_DRIVE_8mA>;
 776 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 777 +               };
 778 +
 779 +               conf-pd {
 780 +                       pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 781 +                       drive-strength = <MTK_DRIVE_8mA>;
 782 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 783 +               };
 784 +       };
 785 +
 786 +       spic_pins: spi1-pins-func-1 {
 787 +               mux {
 788 +                       function = "spi";
 789 +                       groups = "spi1_2";
 790 +               };
 791 +       };
 792 +
 793 +       uart1_pins: spi1-pins-func-3 {
 794 +               mux {
 795 +                       function = "uart";
 796 +                       groups = "uart1_2";
 797 +               };
 798 +       };
 799 +
 800 +       pwm_pins: pwm0-pins-func-1 {
 801 +               mux {
 802 +                       function = "pwm";
 803 +                       groups = "pwm0";
 804 +               };
 805 +       };
 806 +
 807 +       mmc0_pins_default: mmc0default {
 808 +               mux {
 809 +                       function = "flash";
 810 +                       groups =  "emmc_45";
 811 +                       input-schmitt-enable;
 812 +               };
 813 +
 814 +               conf-cmd-dat {
 815 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
 816 +                              "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
 817 +                              "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
 818 +                       input-enable;
 819 +                       drive-strength = <MTK_DRIVE_4mA>;
 820 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 821 +               };
 822 +
 823 +               conf-clk {
 824 +                       pins = "SPI1_CS";
 825 +                       drive-strength = <MTK_DRIVE_6mA>;
 826 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 827 +               };
 828 +
 829 +               conf-rst {
 830 +                       pins = "PWM1";
 831 +                       drive-strength = <MTK_DRIVE_4mA>;
 832 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 833 +               };
 834 +       };
 835 +};
 836 +
 837 +&spi0 {
 838 +       #address-cells = <1>;
 839 +       #size-cells = <0>;
 840 +       pinctrl-names = "default";
 841 +       pinctrl-0 = <&spi_flash_pins>;
 842 +       status = "okay";
 843 +       must_tx;
 844 +       enhance_timing;
 845 +       dma_ext;
 846 +       ipm_design;
 847 +       support_quad;
 848 +       tick_dly = <2>;
 849 +       sample_sel = <0>;
 850 +
 851 +       spi_nor@0 {
 852 +               compatible = "jedec,spi-nor";
 853 +               reg = <0>;
 854 +               spi-max-frequency = <52000000>;
 855 +       };
 856 +
 857 +       spi_nand@1 {
 858 +               compatible = "spi-nand";
 859 +               reg = <1>;
 860 +               spi-max-frequency = <52000000>;
 861 +       };
 862 +};
 863 +
 864 +&pwm {
 865 +       pinctrl-names = "default";
 866 +       pinctrl-0 = <&pwm_pins>;
 867 +       status = "okay";
 868 +};
 869 +
 870 +&watchdog {
 871 +       status = "disabled";
 872 +};
 873 +
 874 +&mmc0 {
 875 +       pinctrl-names = "default";
 876 +       pinctrl-0 = <&mmc0_pins_default>;
 877 +       bus-width = <4>;
 878 +       max-frequency = <52000000>;
 879 +       cap-sd-highspeed;
 880 +       r_smpl = <1>;
 881 +       vmmc-supply = <&reg_3p3v>;
 882 +       vqmmc-supply = <&reg_3p3v>;
 883 +       status = "okay";
 884 +};
 885 --- /dev/null
 886 +++ b/board/mediatek/mt7986/MAINTAINERS
 887 @@ -0,0 +1,10 @@
 888 +MT7986
 889 +M:     Sam Shih <sam.shih@mediatek.com>
 890 +S:     Maintained
 891 +F:     board/mediatek/mt7986
 892 +F:     include/configs/mt7986.h
 893 +F:     configs/mt7986_rfb_defconfig
 894 +F:     configs/mt7986a_emmc_rfb_defconfig
 895 +F:     configs/mt7986a_sd_rfb_defconfig
 896 +F:     configs/mt7986b_emmc_rfb_defconfig
 897 +F:     configs/mt7986b_sd_rfb_defconfig
 898 --- /dev/null
 899 +++ b/board/mediatek/mt7986/Makefile
 900 @@ -0,0 +1,3 @@
 901 +# SPDX-License-Identifier:     GPL-2.0
 902 +
 903 +obj-y  += mt7986_rfb.o
 904 --- /dev/null
 905 +++ b/board/mediatek/mt7986/mt7986_rfb.c
 906 @@ -0,0 +1,10 @@
 907 +// SPDX-License-Identifier: GPL-2.0
 908 +/*
 909 + * Copyright (C) 2022 MediaTek Inc.
 910 + * Author: Sam Shih <sam.shih@mediatek.com>
 911 + */
 912 +
 913 +int board_init(void)
 914 +{
 915 +       return 0;
 916 +}
 917 --- /dev/null
 918 +++ b/configs/mt7986_rfb_defconfig
 919 @@ -0,0 +1,66 @@
 920 +CONFIG_ARM=y
 921 +CONFIG_POSITION_INDEPENDENT=y
 922 +CONFIG_ARCH_MEDIATEK=y
 923 +CONFIG_SYS_TEXT_BASE=0x41e00000
 924 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 925 +CONFIG_NR_DRAM_BANKS=1
 926 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-rfb"
 927 +CONFIG_TARGET_MT7986=y
 928 +CONFIG_DEBUG_UART_BASE=0x11002000
 929 +CONFIG_DEBUG_UART_CLOCK=40000000
 930 +CONFIG_SYS_LOAD_ADDR=0x46000000
 931 +CONFIG_DEBUG_UART=y
 932 +# CONFIG_AUTOBOOT is not set
 933 +CONFIG_DEFAULT_FDT_FILE="mt7986a-rfb"
 934 +CONFIG_LOGLEVEL=7
 935 +CONFIG_LOG=y
 936 +CONFIG_SYS_PROMPT="MT7986> "
 937 +CONFIG_SYS_CBSIZE=512
 938 +CONFIG_SYS_PBSIZE=1049
 939 +# CONFIG_BOOTM_NETBSD is not set
 940 +# CONFIG_BOOTM_PLAN9 is not set
 941 +# CONFIG_BOOTM_RTEMS is not set
 942 +# CONFIG_BOOTM_VXWORKS is not set
 943 +# CONFIG_CMD_ELF is not set
 944 +# CONFIG_CMD_UNLZ4 is not set
 945 +# CONFIG_CMD_UNZIP is not set
 946 +CONFIG_CMD_GPIO=y
 947 +CONFIG_CMD_MTD=y
 948 +CONFIG_CMD_SF_TEST=y
 949 +CONFIG_CMD_PING=y
 950 +CONFIG_CMD_SMC=y
 951 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 952 +CONFIG_NET_RANDOM_ETHADDR=y
 953 +CONFIG_REGMAP=y
 954 +CONFIG_SYSCON=y
 955 +CONFIG_CLK=y
 956 +# CONFIG_MMC is not set
 957 +CONFIG_MTD=y
 958 +CONFIG_DM_MTD=y
 959 +CONFIG_MTD_SPI_NAND=y
 960 +CONFIG_DM_SPI_FLASH=y
 961 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 962 +CONFIG_SPI_FLASH_EON=y
 963 +CONFIG_SPI_FLASH_GIGADEVICE=y
 964 +CONFIG_SPI_FLASH_ISSI=y
 965 +CONFIG_SPI_FLASH_MACRONIX=y
 966 +CONFIG_SPI_FLASH_SPANSION=y
 967 +CONFIG_SPI_FLASH_STMICRO=y
 968 +CONFIG_SPI_FLASH_WINBOND=y
 969 +CONFIG_SPI_FLASH_XMC=y
 970 +CONFIG_SPI_FLASH_XTX=y
 971 +CONFIG_SPI_FLASH_MTD=y
 972 +CONFIG_PHY_FIXED=y
 973 +CONFIG_DM_ETH=y
 974 +CONFIG_MEDIATEK_ETH=y
 975 +CONFIG_PINCTRL=y
 976 +CONFIG_PINCONF=y
 977 +CONFIG_PINCTRL_MT7986=y
 978 +CONFIG_POWER_DOMAIN=y
 979 +CONFIG_MTK_POWER_DOMAIN=y
 980 +CONFIG_DM_SERIAL=y
 981 +CONFIG_MTK_SERIAL=y
 982 +CONFIG_SPI=y
 983 +CONFIG_DM_SPI=y
 984 +CONFIG_MTK_SPIM=y
 985 +CONFIG_HEXDUMP=y
 986 --- /dev/null
 987 +++ b/configs/mt7986a_bpir3_emmc_defconfig
 988 @@ -0,0 +1,64 @@
 989 +CONFIG_ARM=y
 990 +CONFIG_POSITION_INDEPENDENT=y
 991 +CONFIG_ARCH_MEDIATEK=y
 992 +CONFIG_SYS_TEXT_BASE=0x41e00000
 993 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 994 +CONFIG_NR_DRAM_BANKS=1
 995 +CONFIG_ENV_SIZE=0x80000
 996 +CONFIG_ENV_OFFSET=0x300000
 997 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb"
 998 +CONFIG_TARGET_MT7986=y
 999 +CONFIG_DEBUG_UART_BASE=0x11002000
1000 +CONFIG_DEBUG_UART_CLOCK=40000000
1001 +CONFIG_SYS_LOAD_ADDR=0x46000000
1002 +CONFIG_DEBUG_UART=y
1003 +# CONFIG_AUTOBOOT is not set
1004 +CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb"
1005 +CONFIG_LOGLEVEL=7
1006 +CONFIG_LOG=y
1007 +CONFIG_SYS_PROMPT="MT7986> "
1008 +CONFIG_SYS_CBSIZE=512
1009 +CONFIG_SYS_PBSIZE=1049
1010 +# CONFIG_BOOTM_NETBSD is not set
1011 +# CONFIG_BOOTM_PLAN9 is not set
1012 +# CONFIG_BOOTM_RTEMS is not set
1013 +# CONFIG_BOOTM_VXWORKS is not set
1014 +# CONFIG_CMD_ELF is not set
1015 +# CONFIG_CMD_UNLZ4 is not set
1016 +# CONFIG_CMD_UNZIP is not set
1017 +CONFIG_CMD_GPIO=y
1018 +CONFIG_CMD_GPT=y
1019 +CONFIG_CMD_GPT_RENAME=y
1020 +CONFIG_CMD_LSBLK=y
1021 +CONFIG_CMD_MMC=y
1022 +CONFIG_CMD_PART=y
1023 +CONFIG_CMD_READ=y
1024 +CONFIG_CMD_PING=y
1025 +CONFIG_CMD_SMC=y
1026 +CONFIG_CMD_FAT=y
1027 +CONFIG_CMD_FS_GENERIC=y
1028 +CONFIG_PARTITION_TYPE_GUID=y
1029 +CONFIG_ENV_OVERWRITE=y
1030 +CONFIG_ENV_IS_IN_MMC=y
1031 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
1032 +CONFIG_NET_RANDOM_ETHADDR=y
1033 +CONFIG_REGMAP=y
1034 +CONFIG_SYSCON=y
1035 +CONFIG_CLK=y
1036 +CONFIG_MMC_HS200_SUPPORT=y
1037 +CONFIG_MMC_MTK=y
1038 +CONFIG_PHY_FIXED=y
1039 +CONFIG_DM_ETH=y
1040 +CONFIG_MEDIATEK_ETH=y
1041 +CONFIG_PINCTRL=y
1042 +CONFIG_PINCONF=y
1043 +CONFIG_PINCTRL_MT7986=y
1044 +CONFIG_POWER_DOMAIN=y
1045 +CONFIG_MTK_POWER_DOMAIN=y
1046 +CONFIG_DM_REGULATOR=y
1047 +CONFIG_DM_REGULATOR_FIXED=y
1048 +CONFIG_DM_SERIAL=y
1049 +CONFIG_MTK_SERIAL=y
1050 +CONFIG_FAT_WRITE=y
1051 +CONFIG_HEXDUMP=y
1052 +# CONFIG_EFI_LOADER is not set
1053 --- /dev/null
1054 +++ b/configs/mt7986a_bpir3_sd_defconfig
1055 @@ -0,0 +1,64 @@
1056 +CONFIG_ARM=y
1057 +CONFIG_POSITION_INDEPENDENT=y
1058 +CONFIG_ARCH_MEDIATEK=y
1059 +CONFIG_SYS_TEXT_BASE=0x41e00000
1060 +CONFIG_SYS_MALLOC_F_LEN=0x4000
1061 +CONFIG_NR_DRAM_BANKS=1
1062 +CONFIG_ENV_SIZE=0x80000
1063 +CONFIG_ENV_OFFSET=0x300000
1064 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb"
1065 +CONFIG_TARGET_MT7986=y
1066 +CONFIG_DEBUG_UART_BASE=0x11002000
1067 +CONFIG_DEBUG_UART_CLOCK=40000000
1068 +CONFIG_SYS_LOAD_ADDR=0x46000000
1069 +CONFIG_DEBUG_UART=y
1070 +# CONFIG_AUTOBOOT is not set
1071 +CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb"
1072 +CONFIG_LOGLEVEL=7
1073 +CONFIG_LOG=y
1074 +CONFIG_SYS_PROMPT="MT7986> "
1075 +CONFIG_SYS_CBSIZE=512
1076 +CONFIG_SYS_PBSIZE=1049
1077 +# CONFIG_BOOTM_NETBSD is not set
1078 +# CONFIG_BOOTM_PLAN9 is not set
1079 +# CONFIG_BOOTM_RTEMS is not set
1080 +# CONFIG_BOOTM_VXWORKS is not set
1081 +# CONFIG_CMD_ELF is not set
1082 +# CONFIG_CMD_UNLZ4 is not set
1083 +# CONFIG_CMD_UNZIP is not set
1084 +CONFIG_CMD_GPIO=y
1085 +CONFIG_CMD_GPT=y
1086 +CONFIG_CMD_GPT_RENAME=y
1087 +CONFIG_CMD_LSBLK=y
1088 +CONFIG_CMD_MMC=y
1089 +CONFIG_CMD_PART=y
1090 +CONFIG_CMD_READ=y
1091 +CONFIG_CMD_PING=y
1092 +CONFIG_CMD_SMC=y
1093 +CONFIG_CMD_FAT=y
1094 +CONFIG_CMD_FS_GENERIC=y
1095 +CONFIG_PARTITION_TYPE_GUID=y
1096 +CONFIG_ENV_OVERWRITE=y
1097 +CONFIG_ENV_IS_IN_MMC=y
1098 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
1099 +CONFIG_NET_RANDOM_ETHADDR=y
1100 +CONFIG_REGMAP=y
1101 +CONFIG_SYSCON=y
1102 +CONFIG_CLK=y
1103 +CONFIG_MMC_HS200_SUPPORT=y
1104 +CONFIG_MMC_MTK=y
1105 +CONFIG_PHY_FIXED=y
1106 +CONFIG_DM_ETH=y
1107 +CONFIG_MEDIATEK_ETH=y
1108 +CONFIG_PINCTRL=y
1109 +CONFIG_PINCONF=y
1110 +CONFIG_PINCTRL_MT7986=y
1111 +CONFIG_POWER_DOMAIN=y
1112 +CONFIG_MTK_POWER_DOMAIN=y
1113 +CONFIG_DM_REGULATOR=y
1114 +CONFIG_DM_REGULATOR_FIXED=y
1115 +CONFIG_DM_SERIAL=y
1116 +CONFIG_MTK_SERIAL=y
1117 +CONFIG_FAT_WRITE=y
1118 +CONFIG_HEXDUMP=y
1119 +# CONFIG_EFI_LOADER is not set
1120 --- /dev/null
1121 +++ b/include/configs/mt7986.h
1122 @@ -0,0 +1,26 @@
1123 +/* SPDX-License-Identifier: GPL-2.0 */
1124 +/*
1125 + * Configuration for MediaTek MT7986 SoC
1126 + *
1127 + * Copyright (C) 2022 MediaTek Inc.
1128 + * Author: Sam Shih <sam.shih@mediatek.com>
1129 + */
1130 +
1131 +#ifndef __MT7986_H
1132 +#define __MT7986_H
1133 +
1134 +#include <linux/sizes.h>
1135 +
1136 +#define CONFIG_SYS_NONCACHED_MEMORY    SZ_1M
1137 +#define CONFIG_SYS_MMC_ENV_DEV         0
1138 +
1139 +/* Uboot definition */
1140 +#define CONFIG_SYS_UBOOT_BASE          CONFIG_SYS_TEXT_BASE
1141 +
1142 +/* SPL -> Uboot */
1143 +#define CONFIG_SYS_UBOOT_START         CONFIG_SYS_TEXT_BASE
1144 +
1145 +/* DRAM */
1146 +#define CONFIG_SYS_SDRAM_BASE          0x40000000
1147 +
1148 +#endif