package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch

   1 From de6f2293ab087f405dbcf7b8df45d1f9b03fc091 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 27 Jul 2022 17:16:38 +0800
   4 Subject: [PATCH 17/31] i2c: add support for MediaTek I2C interface
   5
   6 This patch adds support for MediaTek I2C interface
   7
   8 Reviewed-by: Heiko Schocher <hs@denx.de>
   9 Reviewed-by: Simon Glass <sjg@chromium.org>
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  drivers/i2c/Kconfig   |   9 +
  13  drivers/i2c/Makefile  |   1 +
  14  drivers/i2c/mtk_i2c.c | 822 ++++++++++++++++++++++++++++++++++++++++++
  15  3 files changed, 832 insertions(+)
  16  create mode 100644 drivers/i2c/mtk_i2c.c
  17
  18 --- a/drivers/i2c/Kconfig
  19 +++ b/drivers/i2c/Kconfig
  20 @@ -261,6 +261,15 @@ config SYS_I2C_MESON
  21           internal buffer holding up to 8 bytes for transfers and supports
  22           both 7-bit and 10-bit addresses.
  23
  24 +config SYS_I2C_MTK
  25 +       bool "MediaTek I2C driver"
  26 +       help
  27 +         This selects the MediaTek Integrated Inter Circuit bus driver.
  28 +         The I2C bus adapter is the base for some other I2C client,
  29 +         eg: touch, sensors.
  30 +         If you want to use MediaTek I2C interface, say Y here.
  31 +         If unsure, say N.
  32 +
  33  config SYS_I2C_MICROCHIP
  34         bool "Microchip I2C driver"
  35         help
  36 --- a/drivers/i2c/Makefile
  37 +++ b/drivers/i2c/Makefile
  38 @@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-m
  39  obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
  40  obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
  41  obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
  42 +obj-$(CONFIG_SYS_I2C_MTK) += mtk_i2c.o
  43  obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
  44  obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
  45  obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
  46 --- /dev/null
  47 +++ b/drivers/i2c/mtk_i2c.c
  48 @@ -0,0 +1,822 @@
  49 +// SPDX-License-Identifier: GPL-2.0+
  50 +/*
  51 + * Copyright (C) 2022 MediaTek Inc. All Rights Reserved.
  52 + *
  53 + * Author: Mingming Lee <Mingming.Lee@mediatek.com>
  54 + *
  55 + * MediaTek I2C Interface driver
  56 + */
  57 +
  58 +#include <clk.h>
  59 +#include <cpu_func.h>
  60 +#include <dm.h>
  61 +#include <i2c.h>
  62 +#include <log.h>
  63 +#include <asm/cache.h>
  64 +#include <asm/io.h>
  65 +#include <linux/delay.h>
  66 +#include <linux/errno.h>
  67 +
  68 +#define I2C_RS_TRANSFER                        BIT(4)
  69 +#define I2C_HS_NACKERR                 BIT(2)
  70 +#define I2C_ACKERR                     BIT(1)
  71 +#define I2C_TRANSAC_COMP               BIT(0)
  72 +#define I2C_TRANSAC_START              BIT(0)
  73 +#define I2C_RS_MUL_CNFG                        BIT(15)
  74 +#define I2C_RS_MUL_TRIG                        BIT(14)
  75 +#define I2C_DCM_DISABLE                        0x0000
  76 +#define I2C_IO_CONFIG_OPEN_DRAIN       0x0003
  77 +#define I2C_IO_CONFIG_PUSH_PULL                0x0000
  78 +#define I2C_SOFT_RST                   0x0001
  79 +#define I2C_FIFO_ADDR_CLR              0x0001
  80 +#define I2C_DELAY_LEN                  0x0002
  81 +#define I2C_ST_START_CON               0x8001
  82 +#define I2C_FS_START_CON               0x1800
  83 +#define I2C_TIME_CLR_VALUE             0x0000
  84 +#define I2C_TIME_DEFAULT_VALUE         0x0003
  85 +#define I2C_WRRD_TRANAC_VALUE          0x0002
  86 +#define I2C_RD_TRANAC_VALUE            0x0001
  87 +
  88 +#define I2C_DMA_CON_TX                 0x0000
  89 +#define I2C_DMA_CON_RX                 0x0001
  90 +#define I2C_DMA_START_EN               0x0001
  91 +#define I2C_DMA_INT_FLAG_NONE          0x0000
  92 +#define I2C_DMA_CLR_FLAG               0x0000
  93 +#define I2C_DMA_TX_RX                  0x0000
  94 +#define I2C_DMA_HARD_RST               0x0002
  95 +
  96 +#define MAX_ST_MODE_SPEED              100000
  97 +#define MAX_FS_MODE_SPEED              400000
  98 +#define MAX_HS_MODE_SPEED              3400000
  99 +#define MAX_SAMPLE_CNT_DIV             8
 100 +#define MAX_STEP_CNT_DIV               64
 101 +#define MAX_HS_STEP_CNT_DIV            8
 102 +#define I2C_DEFAULT_CLK_DIV            4
 103 +
 104 +#define MAX_I2C_ADDR                   0x7f
 105 +#define MAX_I2C_LEN                    0xff
 106 +#define TRANS_ADDR_ONLY                        BIT(8)
 107 +#define TRANSFER_TIMEOUT               50000  /* us */
 108 +#define I2C_FIFO_STAT1_MASK            0x001f
 109 +#define TIMING_SAMPLE_OFFSET           8
 110 +#define HS_SAMPLE_OFFSET               12
 111 +#define HS_STEP_OFFSET                 8
 112 +
 113 +#define I2C_CONTROL_WRAPPER            BIT(0)
 114 +#define I2C_CONTROL_RS                 BIT(1)
 115 +#define I2C_CONTROL_DMA_EN             BIT(2)
 116 +#define I2C_CONTROL_CLK_EXT_EN         BIT(3)
 117 +#define I2C_CONTROL_DIR_CHANGE         BIT(4)
 118 +#define I2C_CONTROL_ACKERR_DET_EN      BIT(5)
 119 +#define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6)
 120 +#define I2C_CONTROL_DMAACK             BIT(8)
 121 +#define I2C_CONTROL_ASYNC              BIT(9)
 122 +
 123 +#define I2C_MASTER_WR                  BIT(0)
 124 +#define I2C_MASTER_RD                  BIT(1)
 125 +#define I2C_MASTER_WRRD                        (I2C_MASTER_WR | I2C_MASTER_RD)
 126 +
 127 +enum I2C_REGS_OFFSET {
 128 +       REG_PORT,
 129 +       REG_SLAVE_ADDR,
 130 +       REG_INTR_MASK,
 131 +       REG_INTR_STAT,
 132 +       REG_CONTROL,
 133 +       REG_TRANSFER_LEN,
 134 +       REG_TRANSAC_LEN,
 135 +       REG_DELAY_LEN,
 136 +       REG_TIMING,
 137 +       REG_START,
 138 +       REG_EXT_CONF,
 139 +       REG_FIFO_STAT1,
 140 +       REG_LTIMING,
 141 +       REG_FIFO_STAT,
 142 +       REG_FIFO_THRESH,
 143 +       REG_FIFO_ADDR_CLR,
 144 +       REG_IO_CONFIG,
 145 +       REG_RSV_DEBUG,
 146 +       REG_HS,
 147 +       REG_SOFTRESET,
 148 +       REG_DCM_EN,
 149 +       REG_PATH_DIR,
 150 +       REG_DEBUGSTAT,
 151 +       REG_DEBUGCTRL,
 152 +       REG_TRANSFER_LEN_AUX,
 153 +       REG_CLOCK_DIV,
 154 +       REG_SCL_HL_RATIO,
 155 +       REG_SCL_HS_HL_RATIO,
 156 +       REG_SCL_MIS_COMP_POINT,
 157 +       REG_STA_STOP_AC_TIME,
 158 +       REG_HS_STA_STOP_AC_TIME,
 159 +       REG_DATA_TIME,
 160 +};
 161 +
 162 +enum DMA_REGS_OFFSET {
 163 +       REG_INT_FLAG = 0x0,
 164 +       REG_INT_EN = 0x04,
 165 +       REG_EN = 0x08,
 166 +       REG_RST = 0x0c,
 167 +       REG_CON = 0x18,
 168 +       REG_TX_MEM_ADDR = 0x1c,
 169 +       REG_RX_MEM_ADDR = 0x20,
 170 +       REG_TX_LEN = 0x24,
 171 +       REG_RX_LEN = 0x28,
 172 +};
 173 +
 174 +static const uint mt_i2c_regs_v1[] = {
 175 +       [REG_PORT] = 0x0,
 176 +       [REG_SLAVE_ADDR] = 0x4,
 177 +       [REG_INTR_MASK] = 0x8,
 178 +       [REG_INTR_STAT] = 0xc,
 179 +       [REG_CONTROL] = 0x10,
 180 +       [REG_TRANSFER_LEN] = 0x14,
 181 +       [REG_TRANSAC_LEN] = 0x18,
 182 +       [REG_DELAY_LEN] = 0x1c,
 183 +       [REG_TIMING] = 0x20,
 184 +       [REG_START] = 0x24,
 185 +       [REG_EXT_CONF] = 0x28,
 186 +       [REG_FIFO_STAT1] = 0x2c,
 187 +       [REG_FIFO_STAT] = 0x30,
 188 +       [REG_FIFO_THRESH] = 0x34,
 189 +       [REG_FIFO_ADDR_CLR] = 0x38,
 190 +       [REG_IO_CONFIG] = 0x40,
 191 +       [REG_RSV_DEBUG] = 0x44,
 192 +       [REG_HS] = 0x48,
 193 +       [REG_SOFTRESET] = 0x50,
 194 +       [REG_SOFTRESET] = 0x50,
 195 +       [REG_DCM_EN] = 0x54,
 196 +       [REG_DEBUGSTAT] = 0x64,
 197 +       [REG_DEBUGCTRL] = 0x68,
 198 +       [REG_TRANSFER_LEN_AUX] = 0x6c,
 199 +       [REG_CLOCK_DIV] = 0x70,
 200 +       [REG_SCL_HL_RATIO] = 0x74,
 201 +       [REG_SCL_HS_HL_RATIO] = 0x78,
 202 +       [REG_SCL_MIS_COMP_POINT] = 0x7c,
 203 +       [REG_STA_STOP_AC_TIME] = 0x80,
 204 +       [REG_HS_STA_STOP_AC_TIME] = 0x84,
 205 +       [REG_DATA_TIME] = 0x88,
 206 +};
 207 +
 208 +static const uint mt_i2c_regs_v2[] = {
 209 +       [REG_PORT] = 0x0,
 210 +       [REG_SLAVE_ADDR] = 0x4,
 211 +       [REG_INTR_MASK] = 0x8,
 212 +       [REG_INTR_STAT] = 0xc,
 213 +       [REG_CONTROL] = 0x10,
 214 +       [REG_TRANSFER_LEN] = 0x14,
 215 +       [REG_TRANSAC_LEN] = 0x18,
 216 +       [REG_DELAY_LEN] = 0x1c,
 217 +       [REG_TIMING] = 0x20,
 218 +       [REG_START] = 0x24,
 219 +       [REG_EXT_CONF] = 0x28,
 220 +       [REG_LTIMING] = 0x2c,
 221 +       [REG_HS] = 0x30,
 222 +       [REG_IO_CONFIG] = 0x34,
 223 +       [REG_FIFO_ADDR_CLR] = 0x38,
 224 +       [REG_TRANSFER_LEN_AUX] = 0x44,
 225 +       [REG_CLOCK_DIV] = 0x48,
 226 +       [REG_SOFTRESET] = 0x50,
 227 +       [REG_DEBUGSTAT] = 0xe0,
 228 +       [REG_DEBUGCTRL] = 0xe8,
 229 +       [REG_FIFO_STAT] = 0xf4,
 230 +       [REG_FIFO_THRESH] = 0xf8,
 231 +       [REG_DCM_EN] = 0xf88,
 232 +};
 233 +
 234 +struct mtk_i2c_soc_data {
 235 +       const uint *regs;
 236 +       uint dma_sync: 1;
 237 +};
 238 +
 239 +struct mtk_i2c_priv {
 240 +       /* set in i2c probe */
 241 +       void __iomem *base;             /* i2c base addr */
 242 +       void __iomem *pdmabase;         /* dma base address*/
 243 +       struct clk clk_main;            /* main clock for i2c bus */
 244 +       struct clk clk_dma;             /* DMA clock for i2c via DMA */
 245 +       const struct mtk_i2c_soc_data *soc_data; /* Compatible data for different IC */
 246 +       int op;                         /* operation mode */
 247 +       bool zero_len;                  /* Only transfer slave address, no data */
 248 +       bool pushpull;                  /* push pull mode or open drain mode */
 249 +       bool filter_msg;                /* filter msg error log */
 250 +       bool auto_restart;              /* restart mode */
 251 +       bool ignore_restart_irq;        /* ignore restart IRQ */
 252 +       uint speed;                     /* i2c speed, unit: hz */
 253 +};
 254 +
 255 +static inline void i2c_writel(struct mtk_i2c_priv *priv, uint reg, uint value)
 256 +{
 257 +       u32 offset = priv->soc_data->regs[reg];
 258 +
 259 +       writel(value, priv->base + offset);
 260 +}
 261 +
 262 +static inline uint i2c_readl(struct mtk_i2c_priv *priv, uint offset)
 263 +{
 264 +       return readl(priv->base + priv->soc_data->regs[offset]);
 265 +}
 266 +
 267 +static int mtk_i2c_clk_enable(struct mtk_i2c_priv *priv)
 268 +{
 269 +       int ret;
 270 +
 271 +       ret = clk_enable(&priv->clk_main);
 272 +       if (ret)
 273 +               return log_msg_ret("enable clk_main", ret);
 274 +
 275 +       ret = clk_enable(&priv->clk_dma);
 276 +       if (ret)
 277 +               return log_msg_ret("enable clk_dma", ret);
 278 +
 279 +       return 0;
 280 +}
 281 +
 282 +static int mtk_i2c_clk_disable(struct mtk_i2c_priv *priv)
 283 +{
 284 +       int ret;
 285 +
 286 +       ret = clk_disable(&priv->clk_dma);
 287 +       if (ret)
 288 +               return log_msg_ret("disable clk_dma", ret);
 289 +
 290 +       ret = clk_disable(&priv->clk_main);
 291 +       if (ret)
 292 +               return log_msg_ret("disable clk_main", ret);
 293 +
 294 +       return 0;
 295 +}
 296 +
 297 +static void mtk_i2c_init_hw(struct mtk_i2c_priv *priv)
 298 +{
 299 +       uint control_reg;
 300 +
 301 +       writel(I2C_DMA_HARD_RST, priv->pdmabase + REG_RST);
 302 +       writel(I2C_DMA_CLR_FLAG, priv->pdmabase + REG_RST);
 303 +       i2c_writel(priv, REG_SOFTRESET, I2C_SOFT_RST);
 304 +       /* set ioconfig */
 305 +       if (priv->pushpull)
 306 +               i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_PUSH_PULL);
 307 +       else
 308 +               i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_OPEN_DRAIN);
 309 +
 310 +       i2c_writel(priv, REG_DCM_EN, I2C_DCM_DISABLE);
 311 +       control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_CLK_EXT_EN;
 312 +       if (priv->soc_data->dma_sync)
 313 +               control_reg |= I2C_CONTROL_DMAACK | I2C_CONTROL_ASYNC;
 314 +       i2c_writel(priv, REG_CONTROL, control_reg);
 315 +       i2c_writel(priv, REG_DELAY_LEN, I2C_DELAY_LEN);
 316 +}
 317 +
 318 +/*
 319 + * Calculate i2c port speed
 320 + *
 321 + * Hardware design:
 322 + * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
 323 + * clock_div: fixed in hardware, but may be various in different SoCs
 324 + *
 325 + * The calculation want to pick the highest bus frequency that is still
 326 + * less than or equal to target_speed. The calculation try to get
 327 + * sample_cnt and step_cn
 328 + * @param[in]
 329 + *     clk_src: i2c clock source
 330 + * @param[out]
 331 + *     timing_step_cnt: step cnt calculate result
 332 + * @param[out]
 333 + *     timing_sample_cnt: sample cnt calculate result
 334 + * @return
 335 + *     0, set speed successfully.
 336 + *     -EINVAL, Unsupported speed.
 337 + */
 338 +static int mtk_i2c_calculate_speed(uint clk_src,
 339 +                                  uint target_speed,
 340 +                                  uint *timing_step_cnt,
 341 +                                  uint *timing_sample_cnt)
 342 +{
 343 +       uint base_sample_cnt = MAX_SAMPLE_CNT_DIV;
 344 +       uint base_step_cnt;
 345 +       uint max_step_cnt;
 346 +       uint sample_cnt;
 347 +       uint step_cnt;
 348 +       uint opt_div;
 349 +       uint best_mul;
 350 +       uint cnt_mul;
 351 +
 352 +       if (target_speed > MAX_HS_MODE_SPEED)
 353 +               target_speed = MAX_HS_MODE_SPEED;
 354 +
 355 +       if (target_speed > MAX_FS_MODE_SPEED)
 356 +               max_step_cnt = MAX_HS_STEP_CNT_DIV;
 357 +       else
 358 +               max_step_cnt = MAX_STEP_CNT_DIV;
 359 +
 360 +       base_step_cnt = max_step_cnt;
 361 +       /* Find the best combination */
 362 +       opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
 363 +       best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 364 +
 365 +       /*
 366 +        * Search for the best pair (sample_cnt, step_cnt) with
 367 +        * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
 368 +        * 0 < step_cnt < max_step_cnt
 369 +        * sample_cnt * step_cnt >= opt_div
 370 +        * optimizing for sample_cnt * step_cnt being minimal
 371 +        */
 372 +       for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 373 +               step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
 374 +               cnt_mul = step_cnt * sample_cnt;
 375 +               if (step_cnt > max_step_cnt)
 376 +                       continue;
 377 +
 378 +               if (cnt_mul < best_mul) {
 379 +                       best_mul = cnt_mul;
 380 +                       base_sample_cnt = sample_cnt;
 381 +                       base_step_cnt = step_cnt;
 382 +                       if (best_mul == opt_div)
 383 +                               break;
 384 +               }
 385 +       }
 386 +
 387 +       sample_cnt = base_sample_cnt;
 388 +       step_cnt = base_step_cnt;
 389 +
 390 +       if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
 391 +               /*
 392 +                * In this case, hardware can't support such
 393 +                * low i2c_bus_freq
 394 +                */
 395 +               debug("Unsupported speed(%uhz)\n", target_speed);
 396 +               return log_msg_ret("calculate speed", -EINVAL);
 397 +       }
 398 +
 399 +       *timing_step_cnt = step_cnt - 1;
 400 +       *timing_sample_cnt = sample_cnt - 1;
 401 +
 402 +       return 0;
 403 +}
 404 +
 405 +/*
 406 + * mtk_i2c_set_speed
 407 + *
 408 + * @par Description
 409 + *     Calculate i2c speed and write sample_cnt, step_cnt to TIMING register.
 410 + * @param[in]
 411 + *     dev: udevice pointer, struct udevice contains i2c source clock,
 412 + *     clock divide and speed.
 413 + * @return
 414 + *     0, set speed successfully.\n
 415 + *     error code from mtk_i2c_calculate_speed().
 416 + */
 417 +static int mtk_i2c_set_speed(struct udevice *dev, uint speed)
 418 +{
 419 +       struct mtk_i2c_priv *priv = dev_get_priv(dev);
 420 +       uint high_speed_reg;
 421 +       uint sample_cnt;
 422 +       uint timing_reg;
 423 +       uint step_cnt;
 424 +       uint clk_src;
 425 +       int ret = 0;
 426 +
 427 +       priv->speed = speed;
 428 +       if (mtk_i2c_clk_enable(priv))
 429 +               return log_msg_ret("set_speed enable clk", -1);
 430 +
 431 +       clk_src = clk_get_rate(&priv->clk_main) / I2C_DEFAULT_CLK_DIV;
 432 +       i2c_writel(priv, REG_CLOCK_DIV, (I2C_DEFAULT_CLK_DIV - 1));
 433 +       if (priv->speed > MAX_FS_MODE_SPEED) {
 434 +               /* Set master code speed register */
 435 +               ret = mtk_i2c_calculate_speed(clk_src, MAX_FS_MODE_SPEED,
 436 +                                             &step_cnt, &sample_cnt);
 437 +               if (ret < 0)
 438 +                       goto exit;
 439 +
 440 +               timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt;
 441 +               i2c_writel(priv, REG_TIMING, timing_reg);
 442 +               /* Set the high speed mode register */
 443 +               ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
 444 +                                             &step_cnt, &sample_cnt);
 445 +               if (ret < 0)
 446 +                       goto exit;
 447 +
 448 +               high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 449 +                               (sample_cnt << HS_SAMPLE_OFFSET) |
 450 +                               (step_cnt << HS_STEP_OFFSET);
 451 +               i2c_writel(priv, REG_HS, high_speed_reg);
 452 +       } else {
 453 +               ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
 454 +                                             &step_cnt, &sample_cnt);
 455 +               if (ret < 0)
 456 +                       goto exit;
 457 +
 458 +               timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt;
 459 +               /* Disable the high speed transaction */
 460 +               high_speed_reg = I2C_TIME_CLR_VALUE;
 461 +               i2c_writel(priv, REG_TIMING, timing_reg);
 462 +               i2c_writel(priv, REG_HS, high_speed_reg);
 463 +       }
 464 +exit:
 465 +       if (mtk_i2c_clk_disable(priv))
 466 +               return log_msg_ret("set_speed disable clk", -1);
 467 +
 468 +       return ret;
 469 +}
 470 +
 471 +/*
 472 + * mtk_i2c_do_transfer
 473 + *
 474 + * @par Description
 475 + *     Configure i2c register and trigger transfer.
 476 + * @param[in]
 477 + *     priv: mtk_i2cmtk_i2c_priv pointer, struct mtk_i2c_priv contains register base\n
 478 + *     address, operation mode, interrupt status and i2c driver data.
 479 + * @param[in]
 480 + *     msgs: i2c_msg pointer, struct i2c_msg contains slave\n
 481 + *     address, operation mode, msg length and data buffer.
 482 + * @param[in]
 483 + *     num: i2c_msg number.
 484 + * @param[in]
 485 + *     left_num: left i2c_msg number.
 486 + * @return
 487 + *     0, i2c transfer successfully.\n
 488 + *     -ETIMEDOUT, i2c transfer timeout.\n
 489 + *     -EREMOTEIO, i2c transfer ack error.
 490 + */
 491 +static int mtk_i2c_do_transfer(struct mtk_i2c_priv *priv,
 492 +                              struct i2c_msg *msgs,
 493 +                              int num, int left_num)
 494 +{
 495 +       struct i2c_msg *msg_rx = NULL;
 496 +       uint restart_flag = 0;
 497 +       uint trans_error = 0;
 498 +       uint irq_stat = 0;
 499 +       uint tmo_poll = 0;
 500 +       uint control_reg;
 501 +       bool tmo = false;
 502 +       uint start_reg;
 503 +       uint addr_reg;
 504 +       int ret = 0;
 505 +
 506 +       if (priv->auto_restart)
 507 +               restart_flag = I2C_RS_TRANSFER;
 508 +
 509 +       control_reg = i2c_readl(priv, REG_CONTROL) &
 510 +               ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
 511 +
 512 +       if (priv->speed > MAX_FS_MODE_SPEED || num > 1)
 513 +               control_reg |= I2C_CONTROL_RS;
 514 +
 515 +       if (priv->op == I2C_MASTER_WRRD)
 516 +               control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 517 +
 518 +       control_reg |= I2C_CONTROL_DMA_EN;
 519 +       i2c_writel(priv, REG_CONTROL, control_reg);
 520 +
 521 +       /* set start condition */
 522 +       if (priv->speed <= MAX_ST_MODE_SPEED)
 523 +               i2c_writel(priv, REG_EXT_CONF, I2C_ST_START_CON);
 524 +       else
 525 +               i2c_writel(priv, REG_EXT_CONF, I2C_FS_START_CON);
 526 +
 527 +       addr_reg = msgs->addr << 1;
 528 +       if (priv->op == I2C_MASTER_RD)
 529 +               addr_reg |= I2C_M_RD;
 530 +       if (priv->zero_len)
 531 +               i2c_writel(priv, REG_SLAVE_ADDR, addr_reg | TRANS_ADDR_ONLY);
 532 +       else
 533 +               i2c_writel(priv, REG_SLAVE_ADDR, addr_reg);
 534 +
 535 +       /* clear interrupt status */
 536 +       i2c_writel(priv, REG_INTR_STAT, restart_flag | I2C_HS_NACKERR |
 537 +                  I2C_ACKERR | I2C_TRANSAC_COMP);
 538 +       i2c_writel(priv, REG_FIFO_ADDR_CLR, I2C_FIFO_ADDR_CLR);
 539 +
 540 +       /* enable interrupt */
 541 +       i2c_writel(priv, REG_INTR_MASK, restart_flag | I2C_HS_NACKERR |
 542 +                  I2C_ACKERR | I2C_TRANSAC_COMP);
 543 +
 544 +       /* set transfer and transaction len */
 545 +       if (priv->op == I2C_MASTER_WRRD) {
 546 +               i2c_writel(priv, REG_TRANSFER_LEN, msgs->len);
 547 +               i2c_writel(priv, REG_TRANSFER_LEN_AUX, (msgs + 1)->len);
 548 +               i2c_writel(priv, REG_TRANSAC_LEN, I2C_WRRD_TRANAC_VALUE);
 549 +       } else {
 550 +               i2c_writel(priv, REG_TRANSFER_LEN, msgs->len);
 551 +               i2c_writel(priv, REG_TRANSAC_LEN, num);
 552 +       }
 553 +
 554 +       /* Clear DMA interrupt flag */
 555 +       writel(I2C_DMA_INT_FLAG_NONE, priv->pdmabase + REG_INT_FLAG);
 556 +
 557 +       /* Flush cache for first msg */
 558 +       flush_cache((ulong)msgs->buf, msgs->len);
 559 +
 560 +       /*
 561 +        * prepare buffer data to start transfer
 562 +        * three cases here: read, write, write then read
 563 +        */
 564 +       if (priv->op & I2C_MASTER_WR) {
 565 +               /* Set DMA direction TX (w/ or w/o RX) */
 566 +               writel(I2C_DMA_CON_TX, priv->pdmabase + REG_CON);
 567 +
 568 +               /* Write the tx buffer address to dma register */
 569 +               writel((ulong)msgs->buf, priv->pdmabase + REG_TX_MEM_ADDR);
 570 +               /* Write the tx length to dma register */
 571 +               writel(msgs->len, priv->pdmabase + REG_TX_LEN);
 572 +
 573 +               if (priv->op & I2C_MASTER_RD) {
 574 +                       /* write then read */
 575 +                       msg_rx = msgs + 1;
 576 +
 577 +                       /* Flush cache for second msg */
 578 +                       flush_cache((ulong)msg_rx->buf, msg_rx->len);
 579 +               }
 580 +       }
 581 +
 582 +       if (priv->op & I2C_MASTER_RD) {
 583 +               if (!msg_rx) {
 584 +                       /* Set DMA direction RX */
 585 +                       writel(I2C_DMA_CON_RX, priv->pdmabase + REG_CON);
 586 +
 587 +                       msg_rx = msgs;
 588 +               }
 589 +
 590 +               /* Write the rx buffer address to dma register */
 591 +               writel((ulong)msg_rx->buf, priv->pdmabase + REG_RX_MEM_ADDR);
 592 +               /* Write the rx length to dma register */
 593 +               writel(msg_rx->len, priv->pdmabase + REG_RX_LEN);
 594 +       }
 595 +
 596 +       writel(I2C_DMA_START_EN, priv->pdmabase + REG_EN);
 597 +
 598 +       if (!priv->auto_restart) {
 599 +               start_reg = I2C_TRANSAC_START;
 600 +       } else {
 601 +               start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
 602 +               if (left_num >= 1)
 603 +                       start_reg |= I2C_RS_MUL_CNFG;
 604 +       }
 605 +       i2c_writel(priv, REG_START, start_reg);
 606 +
 607 +       for (;;) {
 608 +               irq_stat = i2c_readl(priv, REG_INTR_STAT);
 609 +
 610 +               /* ignore the first restart irq after the master code */
 611 +               if (priv->ignore_restart_irq && (irq_stat & restart_flag)) {
 612 +                       priv->ignore_restart_irq = false;
 613 +                       irq_stat = 0;
 614 +                       i2c_writel(priv, REG_START, I2C_RS_MUL_CNFG |
 615 +                                  I2C_RS_MUL_TRIG | I2C_TRANSAC_START);
 616 +               }
 617 +
 618 +               if (irq_stat & (I2C_TRANSAC_COMP | restart_flag)) {
 619 +                       tmo = false;
 620 +                       if (irq_stat & (I2C_HS_NACKERR | I2C_ACKERR))
 621 +                               trans_error = 1;
 622 +
 623 +                       break;
 624 +               }
 625 +               udelay(1);
 626 +               if (tmo_poll++ >= TRANSFER_TIMEOUT) {
 627 +                       tmo = true;
 628 +                       break;
 629 +               }
 630 +       }
 631 +
 632 +       /* clear interrupt mask */
 633 +       i2c_writel(priv, REG_INTR_MASK, ~(restart_flag | I2C_HS_NACKERR |
 634 +                 I2C_ACKERR | I2C_TRANSAC_COMP));
 635 +
 636 +       if (!tmo && trans_error != 0) {
 637 +               if (tmo) {
 638 +                       ret = -ETIMEDOUT;
 639 +                       if (!priv->filter_msg)
 640 +                               debug("I2C timeout! addr: 0x%x,\n", msgs->addr);
 641 +               } else {
 642 +                       ret = -EREMOTEIO;
 643 +                       if (!priv->filter_msg)
 644 +                               debug("I2C ACKERR! addr: 0x%x,IRQ:0x%x\n",
 645 +                                     msgs->addr, irq_stat);
 646 +               }
 647 +               mtk_i2c_init_hw(priv);
 648 +       }
 649 +
 650 +       return ret;
 651 +}
 652 +
 653 +/*
 654 + * mtk_i2c_transfer
 655 + *
 656 + * @par Description
 657 + *     Common i2c transfer API. Set i2c transfer mode according to i2c_msg\n
 658 + *     information, then call mtk_i2c_do_transfer() to configure i2c register\n
 659 + *     and trigger transfer.
 660 + * @param[in]
 661 + *     dev: udevice pointer, struct udevice contains struct mtk_i2c_priv, \n
 662 + *        struct mtk_i2c_priv contains register base\n
 663 + *     address, operation mode, interrupt status and i2c driver data.
 664 + * @param[in]
 665 + *     msgs: i2c_msg pointer, struct i2c_msg contains slave\n
 666 + *     address, operation mode, msg length and data buffer.
 667 + * @param[in]
 668 + *     num: i2c_msg number.
 669 + * @return
 670 + *     i2c_msg number, i2c transfer successfully.\n
 671 + *     -EINVAL, msg length is more than 16\n
 672 + *     use DMA MODE or slave address more than 0x7f.\n
 673 + *     error code from mtk_i2c_init_base().\n
 674 + *     error code from mtk_i2c_set_speed().\n
 675 + *     error code from mtk_i2c_do_transfer().
 676 + */
 677 +static int mtk_i2c_transfer(struct udevice *dev, struct i2c_msg *msg,
 678 +                           int nmsgs)
 679 +{
 680 +       struct mtk_i2c_priv *priv = dev_get_priv(dev);
 681 +       int left_num;
 682 +       uint num_cnt;
 683 +       int ret;
 684 +
 685 +       priv->auto_restart = true;
 686 +       left_num = nmsgs;
 687 +       if (mtk_i2c_clk_enable(priv))
 688 +               return log_msg_ret("transfer enable clk", -1);
 689 +
 690 +       for (num_cnt = 0; num_cnt < nmsgs; num_cnt++) {
 691 +               if (((msg + num_cnt)->addr) > MAX_I2C_ADDR) {
 692 +                       ret = -EINVAL;
 693 +                       goto err_exit;
 694 +               }
 695 +               if ((msg + num_cnt)->len > MAX_I2C_LEN) {
 696 +                       ret = -EINVAL;
 697 +                       goto err_exit;
 698 +               }
 699 +       }
 700 +
 701 +       /* check if we can skip restart and optimize using WRRD mode */
 702 +       if (priv->auto_restart && nmsgs == 2) {
 703 +               if (!(msg[0].flags & I2C_M_RD) && (msg[1].flags & I2C_M_RD) &&
 704 +                   msg[0].addr == msg[1].addr) {
 705 +                       priv->auto_restart = false;
 706 +               }
 707 +       }
 708 +
 709 +       if (priv->auto_restart && nmsgs >= 2 && priv->speed > MAX_FS_MODE_SPEED)
 710 +               /* ignore the first restart irq after the master code,
 711 +                * otherwise the first transfer will be discarded.
 712 +                */
 713 +               priv->ignore_restart_irq = true;
 714 +       else
 715 +               priv->ignore_restart_irq = false;
 716 +
 717 +       while (left_num--) {
 718 +               /* transfer slave address only to support devices detect */
 719 +               if (!msg->buf)
 720 +                       priv->zero_len = true;
 721 +               else
 722 +                       priv->zero_len = false;
 723 +
 724 +               if (msg->flags & I2C_M_RD)
 725 +                       priv->op = I2C_MASTER_RD;
 726 +               else
 727 +                       priv->op = I2C_MASTER_WR;
 728 +
 729 +               if (!priv->auto_restart) {
 730 +                       if (nmsgs > 1) {
 731 +                               /* combined two messages into one transaction */
 732 +                               priv->op = I2C_MASTER_WRRD;
 733 +                               left_num--;
 734 +                       }
 735 +               }
 736 +               ret = mtk_i2c_do_transfer(priv, msg, nmsgs, left_num);
 737 +               if (ret < 0)
 738 +                       goto err_exit;
 739 +               msg++;
 740 +       }
 741 +       ret = 0;
 742 +
 743 +err_exit:
 744 +       if (mtk_i2c_clk_disable(priv))
 745 +               return log_msg_ret("transfer disable clk", -1);
 746 +
 747 +       return ret;
 748 +}
 749 +
 750 +static int mtk_i2c_of_to_plat(struct udevice *dev)
 751 +{
 752 +       struct mtk_i2c_priv *priv = dev_get_priv(dev);
 753 +       int ret;
 754 +
 755 +       priv->base = dev_remap_addr_index(dev, 0);
 756 +       priv->pdmabase = dev_remap_addr_index(dev, 1);
 757 +       ret = clk_get_by_index(dev, 0, &priv->clk_main);
 758 +       if (ret)
 759 +               return log_msg_ret("clk_get_by_index 0", ret);
 760 +
 761 +       ret = clk_get_by_index(dev, 1, &priv->clk_dma);
 762 +
 763 +       return ret;
 764 +}
 765 +
 766 +static int mtk_i2c_probe(struct udevice *dev)
 767 +{
 768 +       struct mtk_i2c_priv *priv = dev_get_priv(dev);
 769 +
 770 +       priv->soc_data = (struct mtk_i2c_soc_data *)dev_get_driver_data(dev);
 771 +
 772 +       if (mtk_i2c_clk_enable(priv))
 773 +               return log_msg_ret("probe enable clk", -1);
 774 +
 775 +       mtk_i2c_init_hw(priv);
 776 +
 777 +       if (mtk_i2c_clk_disable(priv))
 778 +               return log_msg_ret("probe disable clk", -1);
 779 +
 780 +       return 0;
 781 +}
 782 +
 783 +static int mtk_i2c_deblock(struct udevice *dev)
 784 +{
 785 +       struct mtk_i2c_priv *priv = dev_get_priv(dev);
 786 +
 787 +       if (mtk_i2c_clk_enable(priv))
 788 +               return log_msg_ret("deblock enable clk", -1);
 789 +
 790 +       mtk_i2c_init_hw(priv);
 791 +
 792 +       if (mtk_i2c_clk_disable(priv))
 793 +               return log_msg_ret("deblock disable clk", -1);
 794 +
 795 +       return 0;
 796 +}
 797 +
 798 +static const struct mtk_i2c_soc_data mt76xx_soc_data = {
 799 +       .regs = mt_i2c_regs_v1,
 800 +       .dma_sync = 0,
 801 +};
 802 +
 803 +static const struct mtk_i2c_soc_data mt7981_soc_data = {
 804 +       .regs = mt_i2c_regs_v1,
 805 +       .dma_sync = 1,
 806 +};
 807 +
 808 +static const struct mtk_i2c_soc_data mt7986_soc_data = {
 809 +       .regs = mt_i2c_regs_v1,
 810 +       .dma_sync = 1,
 811 +};
 812 +
 813 +static const struct mtk_i2c_soc_data mt8183_soc_data = {
 814 +       .regs = mt_i2c_regs_v2,
 815 +       .dma_sync = 1,
 816 +};
 817 +
 818 +static const struct mtk_i2c_soc_data mt8518_soc_data = {
 819 +       .regs = mt_i2c_regs_v1,
 820 +       .dma_sync = 0,
 821 +};
 822 +
 823 +static const struct mtk_i2c_soc_data mt8512_soc_data = {
 824 +       .regs = mt_i2c_regs_v1,
 825 +       .dma_sync = 1,
 826 +};
 827 +
 828 +static const struct dm_i2c_ops mtk_i2c_ops = {
 829 +       .xfer           = mtk_i2c_transfer,
 830 +       .set_bus_speed  = mtk_i2c_set_speed,
 831 +       .deblock        = mtk_i2c_deblock,
 832 +};
 833 +
 834 +static const struct udevice_id mtk_i2c_ids[] = {
 835 +       {
 836 +               .compatible = "mediatek,mt7622-i2c",
 837 +               .data = (ulong)&mt76xx_soc_data,
 838 +       }, {
 839 +               .compatible = "mediatek,mt7623-i2c",
 840 +               .data = (ulong)&mt76xx_soc_data,
 841 +       }, {
 842 +               .compatible = "mediatek,mt7629-i2c",
 843 +               .data = (ulong)&mt76xx_soc_data,
 844 +       }, {
 845 +               .compatible = "mediatek,mt7981-i2c",
 846 +               .data = (ulong)&mt7981_soc_data,
 847 +       }, {
 848 +               .compatible = "mediatek,mt7986-i2c",
 849 +               .data = (ulong)&mt7986_soc_data,
 850 +       }, {
 851 +               .compatible = "mediatek,mt8183-i2c",
 852 +               .data = (ulong)&mt8183_soc_data,
 853 +       }, {
 854 +               .compatible = "mediatek,mt8512-i2c",
 855 +               .data = (ulong)&mt8512_soc_data,
 856 +       }, {
 857 +               .compatible = "mediatek,mt8518-i2c",
 858 +               .data = (ulong)&mt8518_soc_data,
 859 +       }
 860 +};
 861 +
 862 +U_BOOT_DRIVER(mtk_i2c) = {
 863 +       .name           = "mtk_i2c",
 864 +       .id             = UCLASS_I2C,
 865 +       .of_match       = mtk_i2c_ids,
 866 +       .of_to_plat     = mtk_i2c_of_to_plat,
 867 +       .probe          = mtk_i2c_probe,
 868 +       .priv_auto      = sizeof(struct mtk_i2c_priv),
 869 +       .ops            = &mtk_i2c_ops,
 870 +};