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uboot-mediatek: add support for MT798x platforms
[openwrt/openwrt.git] / package / boot / uboot-mediatek / patches / 002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
1 From 79bca945dbfafcd08d71437b11e8ee57d64b4305 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 29 Jul 2022 11:22:51 +0800
4 Subject: [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek
5 MT7981 SoC
6
7 This patch adds clock driver support for MediaTek MT7981 SoC
8
9 Reviewed-by: Simon Glass <sjg@chromium.org>
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 ---
12 drivers/clk/mediatek/Makefile | 1 +
13 drivers/clk/mediatek/clk-mt7981.c | 683 +++++++++++++++++++++++++
14 include/dt-bindings/clock/mt7981-clk.h | 267 ++++++++++
15 3 files changed, 951 insertions(+)
16 create mode 100644 drivers/clk/mediatek/clk-mt7981.c
17 create mode 100644 include/dt-bindings/clock/mt7981-clk.h
18
19 --- a/drivers/clk/mediatek/Makefile
20 +++ b/drivers/clk/mediatek/Makefile
21 @@ -8,6 +8,7 @@ obj-$(CONFIG_TARGET_MT7623) += clk-mt762
22 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
23 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
24 obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
25 +obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
26 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
27 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
28 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
29 --- /dev/null
30 +++ b/drivers/clk/mediatek/clk-mt7981.c
31 @@ -0,0 +1,683 @@
32 +// SPDX-License-Identifier: GPL-2.0
33 +/*
34 + * MediaTek clock driver for MT7981 SoC
35 + *
36 + * Copyright (C) 2022 MediaTek Inc.
37 + * Author: Sam Shih <sam.shih@mediatek.com>
38 + */
39 +
40 +#include <dm.h>
41 +#include <log.h>
42 +#include <asm/arch-mediatek/reset.h>
43 +#include <asm/io.h>
44 +#include <dt-bindings/clock/mt7981-clk.h>
45 +#include <linux/bitops.h>
46 +
47 +#include "clk-mtk.h"
48 +
49 +#define MT7981_CLK_PDN 0x250
50 +#define MT7981_CLK_PDN_EN_WRITE BIT(31)
51 +
52 +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
53 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
54 +
55 +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
56 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
57 +
58 +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
59 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
60 +
61 +/* FIXED PLLS */
62 +static const struct mtk_fixed_clk fixed_pll_clks[] = {
63 + FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
64 + FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
65 + FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
66 + FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
67 + FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
68 + FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
69 + FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
70 + FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
71 +};
72 +
73 +/* TOPCKGEN FIXED CLK */
74 +static const struct mtk_fixed_clk top_fixed_clks[] = {
75 + FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
76 +};
77 +
78 +/* TOPCKGEN FIXED DIV */
79 +static const struct mtk_fixed_factor top_fixed_divs[] = {
80 + PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
81 + PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
82 + PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3),
83 + PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
84 + PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
85 + PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
86 + PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
87 + PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
88 + PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
89 + PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3),
90 + PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
91 + PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
92 + PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6),
93 + PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
94 + PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
95 + PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
96 + 1),
97 + PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2),
98 + PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
99 + PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1),
100 + PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
101 + PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
102 + PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
103 + PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
104 + PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
105 + PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
106 + PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
107 + PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
108 + 1),
109 + PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
110 + PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
111 + PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
112 + PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
113 + PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
114 + PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
115 + CK_APMIXED_WEDMCUPLL, 1, 1),
116 + PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
117 + TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
118 + TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
119 + 1250),
120 + TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
121 + 1220),
122 + TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
123 + TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1),
124 + TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
125 + TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
126 + 1),
127 + TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
128 + TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
129 + TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
130 + TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
131 + TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
132 + TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1),
133 + TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
134 + TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
135 + TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
136 + TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1),
137 + TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
138 + TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1),
139 + TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1,
140 + 1),
141 + TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
142 + TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1),
143 + TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1,
144 + 1),
145 + TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
146 + 1),
147 + TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1),
148 + TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1,
149 + 1),
150 + TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
151 + CK_TOP_NETSYS_MCU_SEL, 1, 1),
152 + TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
153 + TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
154 + TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1),
155 + TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
156 + TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1),
157 + TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1),
158 + TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1),
159 + TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
160 + TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
161 + TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
162 + TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
163 + TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
164 + TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
165 + TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
166 + 1),
167 +};
168 +
169 +/* TOPCKGEN MUX PARENTS */
170 +static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
171 + CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
172 + CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
173 + CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
174 +
175 +static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
176 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
177 + CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
178 + CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
179 +
180 +static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
181 + CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
182 + CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
183 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
184 +
185 +static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
186 + CK_TOP_M_D8_D2 };
187 +
188 +static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
189 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
190 + CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
191 +
192 +static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
193 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
194 +
195 +static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
196 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
197 + CK_TOP_CB_RTC_32K };
198 +
199 +static const int emmc_208m_parents[] = {
200 + CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
201 + CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
202 + CK_TOP_CB_MM_D6
203 +};
204 +
205 +static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
206 + CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
207 +
208 +static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
209 +
210 +static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
211 + CK_TOP_CB_WEDMCU_208M };
212 +
213 +static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
214 +
215 +static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
216 +
217 +static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
218 + CK_TOP_CB_NET2_D6 };
219 +
220 +static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M,
221 + CK_TOP_NET1_D8_D4 };
222 +
223 +static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
224 +
225 +static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
226 + CK_TOP_CB_NET1_D5 };
227 +
228 +static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M,
229 + CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
230 + CK_TOP_CB_M_416M };
231 +
232 +static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
233 + CK_TOP_CB_NET2_800M,
234 + CK_TOP_CB_MM_720M };
235 +
236 +static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
237 + CK_TOP_CB_SGM_325M };
238 +
239 +static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
240 +
241 +static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
242 + CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
243 + CK_TOP_NET1_D5_D2 };
244 +
245 +static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
246 +
247 +static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
248 +
249 +static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
250 + CK_TOP_M_D8_D2 };
251 +
252 +static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
253 + CK_TOP_M_D8_D2 };
254 +
255 +static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
256 +
257 +static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
258 +
259 +static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
260 + CK_TOP_CB_MM_D3_D5 };
261 +
262 +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
263 + _shift, _width, _gate, _upd_ofs, _upd) \
264 + { \
265 + .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
266 + .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
267 + .upd_shift = _upd, .mux_shift = _shift, \
268 + .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
269 + .gate_shift = _gate, .parent = _parents, \
270 + .num_parents = ARRAY_SIZE(_parents), \
271 + .flags = CLK_MUX_SETCLR_UPD, \
272 + }
273 +
274 +/* TOPCKGEN MUX_GATE */
275 +static const struct mtk_composite top_muxes[] = {
276 + TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
277 + 3, 7, 0x1c0, 0),
278 + TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
279 + 8, 3, 15, 0x1c0, 1),
280 + TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
281 + 23, 0x1c0, 2),
282 + TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
283 + 24, 3, 31, 0x1c0, 3),
284 + TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
285 + 2, 7, 0x1c0, 4),
286 + TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
287 + 15, 0x1c0, 5),
288 + TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
289 + 23, 0x1c0, 6),
290 + TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
291 + 0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7),
292 + TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
293 + 0x24, 0x28, 0, 3, 7, 0x1c0, 8),
294 + TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
295 + 0x24, 0x28, 8, 2, 15, 0x1c0, 9),
296 + TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
297 + 0x28, 16, 1, 23, 0x1c0, 10),
298 + TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
299 + 0x28, 24, 1, 31, 0x1c0, 11),
300 + TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
301 + 0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12),
302 + TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
303 + 0x38, 8, 1, 15, 0x1c0, 13),
304 + TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
305 + 0x38, 16, 1, 23, 0x1c0, 14),
306 + TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
307 + 0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15),
308 + TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
309 + 0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16),
310 + TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
311 + 0x48, 8, 1, 15, 0x1c0, 17),
312 + TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
313 + 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18),
314 + TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
315 + 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
316 + TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
317 + 0x54, 0x58, 0, 2, 7, 0x1c0, 20),
318 + TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
319 + 0x54, 0x58, 8, 1, 15, 0x1c0, 21),
320 + TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
321 + 0x58, 16, 1, 23, 0x1c0, 22),
322 + TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
323 + 0x58, 24, 3, 31, 0x1c0, 23),
324 + TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
325 + 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
326 + TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
327 + 15, 0x1c0, 25),
328 + TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
329 + 16, 1, 23, 0x1c0, 26),
330 + TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
331 + 24, 2, 31, 0x1c0, 27),
332 + TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
333 + 0x78, 0, 2, 7, 0x1c0, 28),
334 + TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
335 + 1, 15, 0x1c0, 29),
336 + TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
337 + 0x74, 0x78, 16, 1, 23, 0x1c0, 30),
338 + TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
339 + 0x74, 0x78, 24, 1, 31, 0x1c4, 0),
340 + TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
341 + 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1),
342 +};
343 +
344 +/* INFRA FIXED DIV */
345 +static const struct mtk_fixed_factor infra_fixed_divs[] = {
346 + TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
347 + TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
348 + TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
349 + TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
350 + TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1),
351 + TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
352 + TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
353 + TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
354 + 1),
355 + TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
356 + INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
357 + 1),
358 + INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
359 + 1),
360 + INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
361 + 1),
362 + TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
363 + INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
364 + 1),
365 + TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
366 + TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
367 + TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
368 + 1),
369 + TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
370 + INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
371 + 1, 1),
372 + INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
373 + 1, 1),
374 + INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
375 + 1, 1),
376 + TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
377 + TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
378 + INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
379 + 1),
380 + INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
381 + 1),
382 + INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1,
383 + 1),
384 + TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
385 + TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1),
386 + TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M,
387 + 1, 1),
388 + TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
389 + TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
390 + TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
391 + TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
392 + TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
393 + 1),
394 + TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
395 + CK_TOP_PEXTP_TL, 1, 1),
396 + TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
397 + TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
398 +};
399 +
400 +/* INFRASYS MUX PARENTS */
401 +static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
402 +
403 +static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
404 +
405 +static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
406 +
407 +static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM };
408 +
409 +static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM };
410 +
411 +static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
412 + CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK};
413 +
414 +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
415 + { \
416 + .id = _id, .mux_reg = (_reg) + 0x8, \
417 + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
418 + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
419 + .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
420 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
421 + }
422 +
423 +/* INFRA MUX */
424 +static const struct mtk_composite infra_muxes[] = {
425 + INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
426 + 0x10, 0, 1),
427 + INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
428 + 0x10, 1, 1),
429 + INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
430 + 0x10, 2, 1),
431 + INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
432 + 4, 1),
433 + INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
434 + 5, 1),
435 + INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
436 + 6, 1),
437 + INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
438 + 9, 2),
439 + INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
440 + 11, 2),
441 + INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
442 + 0x10, 13, 2),
443 + INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
444 + 0, 2),
445 +};
446 +
447 +static const struct mtk_gate_regs infra_0_cg_regs = {
448 + .set_ofs = 0x40,
449 + .clr_ofs = 0x44,
450 + .sta_ofs = 0x48,
451 +};
452 +
453 +static const struct mtk_gate_regs infra_1_cg_regs = {
454 + .set_ofs = 0x50,
455 + .clr_ofs = 0x54,
456 + .sta_ofs = 0x58,
457 +};
458 +
459 +static const struct mtk_gate_regs infra_2_cg_regs = {
460 + .set_ofs = 0x60,
461 + .clr_ofs = 0x64,
462 + .sta_ofs = 0x68,
463 +};
464 +
465 +#define GATE_INFRA0(_id, _name, _parent, _shift) \
466 + { \
467 + .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
468 + .shift = _shift, \
469 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
470 + }
471 +
472 +#define GATE_INFRA1(_id, _name, _parent, _shift) \
473 + { \
474 + .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
475 + .shift = _shift, \
476 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
477 + }
478 +
479 +#define GATE_INFRA2(_id, _name, _parent, _shift) \
480 + { \
481 + .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
482 + .shift = _shift, \
483 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
484 + }
485 +
486 +/* INFRA GATE */
487 +static const struct mtk_gate infracfg_ao_gates[] = {
488 + GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
489 + GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
490 + GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
491 + GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
492 + GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
493 + GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
494 + GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
495 + GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
496 + GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
497 + GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
498 + 11),
499 + GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
500 + 13),
501 + GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
502 + 14),
503 + GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
504 + GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
505 + GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
506 + GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
507 + GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
508 + GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
509 + GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
510 + GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
511 + GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
512 + GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6),
513 + GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK,
514 + 7),
515 + GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
516 + GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
517 + 9),
518 + GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
519 + GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
520 + GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
521 + GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
522 + 13),
523 + GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
524 + 14),
525 + GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
526 + GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
527 + GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
528 + CK_INFRA_FMSDC_HCK_CK, 17),
529 + GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
530 + CK_INFRA_PERI_133M, 18),
531 + GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
532 + 19),
533 + GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20),
534 + GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21),
535 + GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
536 + 23),
537 + GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK,
538 + 25),
539 + GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26),
540 + GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
541 + 0),
542 + GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
543 + 1),
544 + GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
545 + 2),
546 + GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
547 + GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie",
548 + CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12),
549 + GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
550 + GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
551 +};
552 +
553 +static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
554 + .fdivs_offs = CLK_APMIXED_NR_CLK,
555 + .xtal_rate = 40 * MHZ,
556 + .fclks = fixed_pll_clks,
557 +};
558 +
559 +static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
560 + .fdivs_offs = CK_TOP_CB_M_416M,
561 + .muxes_offs = CK_TOP_NFI1X_SEL,
562 + .fclks = top_fixed_clks,
563 + .fdivs = top_fixed_divs,
564 + .muxes = top_muxes,
565 + .flags = CLK_BYPASS_XTAL,
566 +};
567 +
568 +static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
569 + .fdivs_offs = CK_INFRA_CK_F26M,
570 + .muxes_offs = CK_INFRA_UART0_SEL,
571 + .fdivs = infra_fixed_divs,
572 + .muxes = infra_muxes,
573 +};
574 +
575 +static const struct udevice_id mt7981_fixed_pll_compat[] = {
576 + { .compatible = "mediatek,mt7981-fixed-plls" },
577 + {}
578 +};
579 +
580 +static const struct udevice_id mt7981_topckgen_compat[] = {
581 + { .compatible = "mediatek,mt7981-topckgen" },
582 + {}
583 +};
584 +
585 +static int mt7981_fixed_pll_probe(struct udevice *dev)
586 +{
587 + return mtk_common_clk_init(dev, &mt7981_fixed_pll_clk_tree);
588 +}
589 +
590 +static int mt7981_topckgen_probe(struct udevice *dev)
591 +{
592 + struct mtk_clk_priv *priv = dev_get_priv(dev);
593 +
594 + priv->base = dev_read_addr_ptr(dev);
595 + writel(MT7981_CLK_PDN_EN_WRITE, priv->base + MT7981_CLK_PDN);
596 +
597 + return mtk_common_clk_init(dev, &mt7981_topckgen_clk_tree);
598 +}
599 +
600 +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
601 + .name = "mt7981-clock-fixed-pll",
602 + .id = UCLASS_CLK,
603 + .of_match = mt7981_fixed_pll_compat,
604 + .probe = mt7981_fixed_pll_probe,
605 + .priv_auto = sizeof(struct mtk_clk_priv),
606 + .ops = &mtk_clk_topckgen_ops,
607 + .flags = DM_FLAG_PRE_RELOC,
608 +};
609 +
610 +U_BOOT_DRIVER(mtk_clk_topckgen) = {
611 + .name = "mt7981-clock-topckgen",
612 + .id = UCLASS_CLK,
613 + .of_match = mt7981_topckgen_compat,
614 + .probe = mt7981_topckgen_probe,
615 + .priv_auto = sizeof(struct mtk_clk_priv),
616 + .ops = &mtk_clk_topckgen_ops,
617 + .flags = DM_FLAG_PRE_RELOC,
618 +};
619 +
620 +static const struct udevice_id mt7981_infracfg_compat[] = {
621 + { .compatible = "mediatek,mt7981-infracfg" },
622 + {}
623 +};
624 +
625 +static const struct udevice_id mt7981_infracfg_ao_compat[] = {
626 + { .compatible = "mediatek,mt7981-infracfg_ao" },
627 + {}
628 +};
629 +
630 +static int mt7981_infracfg_probe(struct udevice *dev)
631 +{
632 + return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
633 +}
634 +
635 +static int mt7981_infracfg_ao_probe(struct udevice *dev)
636 +{
637 + return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree,
638 + infracfg_ao_gates);
639 +}
640 +
641 +U_BOOT_DRIVER(mtk_clk_infracfg) = {
642 + .name = "mt7981-clock-infracfg",
643 + .id = UCLASS_CLK,
644 + .of_match = mt7981_infracfg_compat,
645 + .probe = mt7981_infracfg_probe,
646 + .priv_auto = sizeof(struct mtk_clk_priv),
647 + .ops = &mtk_clk_infrasys_ops,
648 + .flags = DM_FLAG_PRE_RELOC,
649 +};
650 +
651 +U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
652 + .name = "mt7981-clock-infracfg-ao",
653 + .id = UCLASS_CLK,
654 + .of_match = mt7981_infracfg_ao_compat,
655 + .probe = mt7981_infracfg_ao_probe,
656 + .priv_auto = sizeof(struct mtk_cg_priv),
657 + .ops = &mtk_clk_gate_ops,
658 + .flags = DM_FLAG_PRE_RELOC,
659 +};
660 +
661 +/* ethsys */
662 +static const struct mtk_gate_regs eth_cg_regs = {
663 + .set_ofs = 0x30,
664 + .clr_ofs = 0x30,
665 + .sta_ofs = 0x30,
666 +};
667 +
668 +#define GATE_ETH(_id, _name, _parent, _shift) \
669 + { \
670 + .id = _id, .parent = _parent, .regs = &eth_cg_regs, \
671 + .shift = _shift, \
672 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
673 + }
674 +
675 +static const struct mtk_gate eth_cgs[] = {
676 + GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6),
677 + GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7),
678 + GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
679 + GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
680 +};
681 +
682 +static int mt7981_ethsys_probe(struct udevice *dev)
683 +{
684 + return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
685 + eth_cgs);
686 +}
687 +
688 +static int mt7981_ethsys_bind(struct udevice *dev)
689 +{
690 + int ret = 0;
691 +
692 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
693 + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
694 + if (ret)
695 + debug("Warning: failed to bind reset controller\n");
696 + }
697 +
698 + return ret;
699 +}
700 +
701 +static const struct udevice_id mt7981_ethsys_compat[] = {
702 + { .compatible = "mediatek,mt7981-ethsys", },
703 + {}
704 +};
705 +
706 +U_BOOT_DRIVER(mtk_clk_ethsys) = {
707 + .name = "mt7981-clock-ethsys",
708 + .id = UCLASS_CLK,
709 + .of_match = mt7981_ethsys_compat,
710 + .probe = mt7981_ethsys_probe,
711 + .bind = mt7981_ethsys_bind,
712 + .priv_auto = sizeof(struct mtk_cg_priv),
713 + .ops = &mtk_clk_gate_ops,
714 +};
715 --- /dev/null
716 +++ b/include/dt-bindings/clock/mt7981-clk.h
717 @@ -0,0 +1,267 @@
718 +/* SPDX-License-Identifier: GPL-2.0 */
719 +/*
720 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
721 + *
722 + * Author: Sam Shih <sam.shih@mediatek.com>
723 + */
724 +
725 +#ifndef _DT_BINDINGS_CLK_MT7981_H
726 +#define _DT_BINDINGS_CLK_MT7981_H
727 +
728 +/* INFRACFG */
729 +
730 +#define CK_INFRA_CK_F26M 0
731 +#define CK_INFRA_UART 1
732 +#define CK_INFRA_ISPI0 2
733 +#define CK_INFRA_I2C 3
734 +#define CK_INFRA_ISPI1 4
735 +#define CK_INFRA_PWM 5
736 +#define CK_INFRA_66M_MCK 6
737 +#define CK_INFRA_CK_F32K 7
738 +#define CK_INFRA_PCIE_CK 8
739 +#define CK_INFRA_PWM_BCK 9
740 +#define CK_INFRA_PWM_CK1 10
741 +#define CK_INFRA_PWM_CK2 11
742 +#define CK_INFRA_133M_HCK 12
743 +#define CK_INFRA_66M_PHCK 13
744 +#define CK_INFRA_FAUD_L_CK 14
745 +#define CK_INFRA_FAUD_AUD_CK 15
746 +#define CK_INFRA_FAUD_EG2_CK 16
747 +#define CK_INFRA_I2CS_CK 17
748 +#define CK_INFRA_MUX_UART0 18
749 +#define CK_INFRA_MUX_UART1 19
750 +#define CK_INFRA_MUX_UART2 20
751 +#define CK_INFRA_NFI_CK 21
752 +#define CK_INFRA_SPINFI_CK 22
753 +#define CK_INFRA_MUX_SPI0 23
754 +#define CK_INFRA_MUX_SPI1 24
755 +#define CK_INFRA_MUX_SPI2 25
756 +#define CK_INFRA_RTC_32K 26
757 +#define CK_INFRA_FMSDC_CK 27
758 +#define CK_INFRA_FMSDC_HCK_CK 28
759 +#define CK_INFRA_PERI_133M 29
760 +#define CK_INFRA_133M_PHCK 30
761 +#define CK_INFRA_USB_SYS_CK 31
762 +#define CK_INFRA_USB_CK 32
763 +#define CK_INFRA_USB_XHCI_CK 33
764 +#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
765 +#define CK_INFRA_F26M_CK0 35
766 +#define CK_INFRA_133M_MCK 36
767 +#define CLK_INFRA_NR_CLK 37
768 +
769 +/* TOPCKGEN */
770 +
771 +#define CK_TOP_CB_CKSQ_40M 0
772 +#define CK_TOP_CB_M_416M 1
773 +#define CK_TOP_CB_M_D2 2
774 +#define CK_TOP_CB_M_D3 3
775 +#define CK_TOP_M_D3_D2 4
776 +#define CK_TOP_CB_M_D4 5
777 +#define CK_TOP_CB_M_D8 6
778 +#define CK_TOP_M_D8_D2 7
779 +#define CK_TOP_CB_MM_720M 8
780 +#define CK_TOP_CB_MM_D2 9
781 +#define CK_TOP_CB_MM_D3 10
782 +#define CK_TOP_CB_MM_D3_D5 11
783 +#define CK_TOP_CB_MM_D4 12
784 +#define CK_TOP_CB_MM_D6 13
785 +#define CK_TOP_MM_D6_D2 14
786 +#define CK_TOP_CB_MM_D8 15
787 +#define CK_TOP_CB_APLL2_196M 16
788 +#define CK_TOP_APLL2_D2 17
789 +#define CK_TOP_APLL2_D4 18
790 +#define CK_TOP_NET1_2500M 19
791 +#define CK_TOP_CB_NET1_D4 20
792 +#define CK_TOP_CB_NET1_D5 21
793 +#define CK_TOP_NET1_D5_D2 22
794 +#define CK_TOP_NET1_D5_D4 23
795 +#define CK_TOP_CB_NET1_D8 24
796 +#define CK_TOP_NET1_D8_D2 25
797 +#define CK_TOP_NET1_D8_D4 26
798 +#define CK_TOP_CB_NET2_800M 27
799 +#define CK_TOP_CB_NET2_D2 28
800 +#define CK_TOP_CB_NET2_D4 29
801 +#define CK_TOP_NET2_D4_D2 30
802 +#define CK_TOP_NET2_D4_D4 31
803 +#define CK_TOP_CB_NET2_D6 32
804 +#define CK_TOP_CB_WEDMCU_208M 33
805 +#define CK_TOP_CB_SGM_325M 34
806 +#define CK_TOP_CKSQ_40M_D2 35
807 +#define CK_TOP_CB_RTC_32K 36
808 +#define CK_TOP_CB_RTC_32P7K 37
809 +#define CK_TOP_USB_TX250M 38
810 +#define CK_TOP_FAUD 39
811 +#define CK_TOP_NFI1X 40
812 +#define CK_TOP_USB_EQ_RX250M 41
813 +#define CK_TOP_USB_CDR_CK 42
814 +#define CK_TOP_USB_LN0_CK 43
815 +#define CK_TOP_SPINFI_BCK 44
816 +#define CK_TOP_SPI 45
817 +#define CK_TOP_SPIM_MST 46
818 +#define CK_TOP_UART_BCK 47
819 +#define CK_TOP_PWM_BCK 48
820 +#define CK_TOP_I2C_BCK 49
821 +#define CK_TOP_PEXTP_TL 50
822 +#define CK_TOP_EMMC_208M 51
823 +#define CK_TOP_EMMC_400M 52
824 +#define CK_TOP_DRAMC_REF 53
825 +#define CK_TOP_DRAMC_MD32 54
826 +#define CK_TOP_SYSAXI 55
827 +#define CK_TOP_SYSAPB 56
828 +#define CK_TOP_ARM_DB_MAIN 57
829 +#define CK_TOP_AP2CNN_HOST 58
830 +#define CK_TOP_NETSYS 59
831 +#define CK_TOP_NETSYS_500M 60
832 +#define CK_TOP_NETSYS_WED_MCU 61
833 +#define CK_TOP_NETSYS_2X 62
834 +#define CK_TOP_SGM_325M 63
835 +#define CK_TOP_SGM_REG 64
836 +#define CK_TOP_F26M 65
837 +#define CK_TOP_EIP97B 66
838 +#define CK_TOP_USB3_PHY 67
839 +#define CK_TOP_AUD 68
840 +#define CK_TOP_A1SYS 69
841 +#define CK_TOP_AUD_L 70
842 +#define CK_TOP_A_TUNER 71
843 +#define CK_TOP_U2U3_REF 72
844 +#define CK_TOP_U2U3_SYS 73
845 +#define CK_TOP_U2U3_XHCI 74
846 +#define CK_TOP_USB_FRMCNT 75
847 +#define CK_TOP_NFI1X_SEL 76
848 +#define CK_TOP_SPINFI_SEL 77
849 +#define CK_TOP_SPI_SEL 78
850 +#define CK_TOP_SPIM_MST_SEL 79
851 +#define CK_TOP_UART_SEL 80
852 +#define CK_TOP_PWM_SEL 81
853 +#define CK_TOP_I2C_SEL 82
854 +#define CK_TOP_PEXTP_TL_SEL 83
855 +#define CK_TOP_EMMC_208M_SEL 84
856 +#define CK_TOP_EMMC_400M_SEL 85
857 +#define CK_TOP_F26M_SEL 86
858 +#define CK_TOP_DRAMC_SEL 87
859 +#define CK_TOP_DRAMC_MD32_SEL 88
860 +#define CK_TOP_SYSAXI_SEL 89
861 +#define CK_TOP_SYSAPB_SEL 90
862 +#define CK_TOP_ARM_DB_MAIN_SEL 91
863 +#define CK_TOP_AP2CNN_HOST_SEL 92
864 +#define CK_TOP_NETSYS_SEL 93
865 +#define CK_TOP_NETSYS_500M_SEL 94
866 +#define CK_TOP_NETSYS_MCU_SEL 95
867 +#define CK_TOP_NETSYS_2X_SEL 96
868 +#define CK_TOP_SGM_325M_SEL 97
869 +#define CK_TOP_SGM_REG_SEL 98
870 +#define CK_TOP_EIP97B_SEL 99
871 +#define CK_TOP_USB3_PHY_SEL 100
872 +#define CK_TOP_AUD_SEL 101
873 +#define CK_TOP_A1SYS_SEL 102
874 +#define CK_TOP_AUD_L_SEL 103
875 +#define CK_TOP_A_TUNER_SEL 104
876 +#define CK_TOP_U2U3_SEL 105
877 +#define CK_TOP_U2U3_SYS_SEL 106
878 +#define CK_TOP_U2U3_XHCI_SEL 107
879 +#define CK_TOP_USB_FRMCNT_SEL 108
880 +#define CLK_TOP_NR_CLK 109
881 +
882 +/*
883 + * INFRACFG_AO
884 + * clock muxes need to be append to infracfg domain, and clock gates
885 + * need to be keep in infracgh_ao domain
886 + */
887 +#define INFRACFG_AO_OFFSET 10
888 +
889 +#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
890 +#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
891 +#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
892 +#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
893 +#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
894 +#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
895 +#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
896 +#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
897 +#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
898 +#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK)
899 +#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET)
900 +#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET)
901 +#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET)
902 +#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET)
903 +#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET)
904 +#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET)
905 +#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET)
906 +#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET)
907 +#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET)
908 +#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET)
909 +#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET)
910 +#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET)
911 +#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET)
912 +#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET)
913 +#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET)
914 +#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET)
915 +#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET)
916 +#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET)
917 +#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET)
918 +#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET)
919 +#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET)
920 +#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET)
921 +#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET)
922 +#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET)
923 +#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET)
924 +#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET)
925 +#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET)
926 +#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET)
927 +#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET)
928 +#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET)
929 +#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET)
930 +#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET)
931 +#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET)
932 +#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET)
933 +#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET)
934 +#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET)
935 +#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET)
936 +#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET)
937 +#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET)
938 +#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET)
939 +#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET)
940 +#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET)
941 +#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET)
942 +#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET)
943 +#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET)
944 +#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET)
945 +#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET)
946 +#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET)
947 +
948 +/* APMIXEDSYS */
949 +
950 +#define CK_APMIXED_ARMPLL 0
951 +#define CK_APMIXED_NET2PLL 1
952 +#define CK_APMIXED_MMPLL 2
953 +#define CK_APMIXED_SGMPLL 3
954 +#define CK_APMIXED_WEDMCUPLL 4
955 +#define CK_APMIXED_NET1PLL 5
956 +#define CK_APMIXED_MPLL 6
957 +#define CK_APMIXED_APLL2 7
958 +#define CLK_APMIXED_NR_CLK 8
959 +
960 +/* SGMIISYS_0 */
961 +
962 +#define CK_SGM0_TX_EN 0
963 +#define CK_SGM0_RX_EN 1
964 +#define CK_SGM0_CK0_EN 2
965 +#define CK_SGM0_CDR_CK0_EN 3
966 +#define CLK_SGMII0_NR_CLK 4
967 +
968 +/* SGMIISYS_1 */
969 +
970 +#define CK_SGM1_TX_EN 0
971 +#define CK_SGM1_RX_EN 1
972 +#define CK_SGM1_CK1_EN 2
973 +#define CK_SGM1_CDR_CK1_EN 3
974 +#define CLK_SGMII1_NR_CLK 4
975 +
976 +/* ETHSYS */
977 +
978 +#define CK_ETH_FE_EN 0
979 +#define CK_ETH_GP2_EN 1
980 +#define CK_ETH_GP1_EN 2
981 +#define CK_ETH_WOCPU0_EN 3
982 +#define CLK_ETH_NR_CLK 4
983 +
984 +#endif /* _DT_BINDINGS_CLK_MT7981_H */
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