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omap: switch to kernel 4.19
[openwrt/openwrt.git] / package / boot / uboot-omap / patches / 105-serial-ns16550-bugfix-ns16550-fifo-not-enabled.patch
1 From 17fa032671f7981628fe16b30399638842a4b1bb Mon Sep 17 00:00:00 2001
2 From: Heiko Schocher <hs@denx.de>
3 Date: Wed, 18 Jan 2017 08:05:49 +0100
4 Subject: [PATCH] serial, ns16550: bugfix: ns16550 fifo not enabled
5
6 commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
7 breaks u-boot commandline working with long commands
8 sending to the board.
9
10 Since the above patch, you have to setup the fcr register.
11
12 For board/archs which enable OF_PLATDATA, the new field
13 fcr in struct ns16550_platdata is not filled with a
14 default value ...
15
16 This leads in not setting up the uarts fifo, which ends
17 in problems, when you send long commands to u-boots
18 commandline.
19
20 Detected this issue with automated tbot tests on am335x
21 based shc board.
22
23 The error does not popup, if you type commands. You need
24 to copy&paste a long command to u-boots commandshell
25 (or send a long command with tbot)
26
27 Possible boards/plattforms with problems:
28 ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
29 ./arch/arm/mach-tegra/board.c
30 ./board/overo/overo.c
31 ./board/quipos/cairo/cairo.c
32 ./board/logicpd/omap3som/omap3logic.c
33 ./board/logicpd/zoom1/zoom1.c
34 ./board/timll/devkit8000/devkit8000.c
35 ./board/lg/sniper/sniper.c
36 ./board/ti/beagle/beagle.c
37 ./drivers/serial/serial_rockchip.c
38
39 Signed-off-by: Heiko Schocher <hs@denx.de>
40 Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
41 Tested-by: Adam Ford <aford173@gmail.com>
42 Reviewed-by: Tom Rini <trini@konsulko.com>
43 ---
44 arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 12 ++++++++----
45 arch/arm/mach-omap2/am33xx/board.c | 18 ++++++++++++------
46 arch/arm/mach-tegra/board.c | 1 +
47 board/isee/igep00x0/igep00x0.c | 3 ++-
48 board/lg/sniper/sniper.c | 3 ++-
49 board/logicpd/omap3som/omap3logic.c | 3 ++-
50 board/logicpd/zoom1/zoom1.c | 3 ++-
51 board/overo/overo.c | 3 ++-
52 board/quipos/cairo/cairo.c | 3 ++-
53 board/ti/beagle/beagle.c | 3 ++-
54 board/timll/devkit8000/devkit8000.c | 3 ++-
55 drivers/serial/ns16550.c | 9 +++------
56 drivers/serial/serial_rockchip.c | 1 +
57 include/ns16550.h | 5 +++++
58 14 files changed, 46 insertions(+), 24 deletions(-)
59
60 diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
61 index 399b07c5420a..f744398ca7ad 100644
62 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
63 +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
64 @@ -45,10 +45,14 @@ void lpc32xx_uart_init(unsigned int uart_id)
65
66 #if !CONFIG_IS_ENABLED(OF_CONTROL)
67 static const struct ns16550_platdata lpc32xx_uart[] = {
68 - { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
69 - { .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
70 - { .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
71 - { .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
72 + { .base = UART3_BASE, .reg_shift = 2,
73 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
74 + { .base = UART4_BASE, .reg_shift = 2,
75 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
76 + { .base = UART5_BASE, .reg_shift = 2,
77 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
78 + { .base = UART6_BASE, .reg_shift = 2,
79 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
80 };
81
82 #if defined(CONFIG_LPC32XX_HSUART)
83 diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
84 index 73824df18fa7..190310fd0079 100644
85 --- a/arch/arm/mach-omap2/am33xx/board.c
86 +++ b/arch/arm/mach-omap2/am33xx/board.c
87 @@ -40,14 +40,20 @@ DECLARE_GLOBAL_DATA_PTR;
88
89 #if !CONFIG_IS_ENABLED(OF_CONTROL)
90 static const struct ns16550_platdata am33xx_serial[] = {
91 - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
92 + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
93 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
94 # ifdef CONFIG_SYS_NS16550_COM2
95 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
96 + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
97 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
98 # ifdef CONFIG_SYS_NS16550_COM3
99 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
100 - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
101 - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
102 - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
103 + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
104 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
105 + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
106 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
107 + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
108 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
109 + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
110 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
111 # endif
112 # endif
113 };
114 diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
115 index 3d1d26d13d13..b3a041b539af 100644
116 --- a/arch/arm/mach-tegra/board.c
117 +++ b/arch/arm/mach-tegra/board.c
118 @@ -219,6 +219,7 @@ static struct ns16550_platdata ns16550_com1_pdata = {
119 .base = CONFIG_SYS_NS16550_COM1,
120 .reg_shift = 2,
121 .clock = CONFIG_SYS_NS16550_CLK,
122 + .fcr = UART_FCR_DEFVAL,
123 };
124
125 U_BOOT_DEVICE(ns16550_com1) = {
126 diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
127 index ae7959b1eb6e..5a3498f570a6 100644
128 --- a/board/isee/igep00x0/igep00x0.c
129 +++ b/board/isee/igep00x0/igep00x0.c
130 @@ -32,7 +32,8 @@ DECLARE_GLOBAL_DATA_PTR;
131 static const struct ns16550_platdata igep_serial = {
132 .base = OMAP34XX_UART3,
133 .reg_shift = 2,
134 - .clock = V_NS16550_CLK
135 + .clock = V_NS16550_CLK,
136 + .fcr = UART_FCR_DEFVAL,
137 };
138
139 U_BOOT_DEVICE(igep_uart) = {
140 diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
141 index 0662449c3875..b2b8f8861f11 100644
142 --- a/board/lg/sniper/sniper.c
143 +++ b/board/lg/sniper/sniper.c
144 @@ -31,7 +31,8 @@ const omap3_sysinfo sysinfo = {
145 static const struct ns16550_platdata serial_omap_platdata = {
146 .base = OMAP34XX_UART3,
147 .reg_shift = 2,
148 - .clock = V_NS16550_CLK
149 + .clock = V_NS16550_CLK,
150 + .fcr = UART_FCR_DEFVAL,
151 };
152
153 U_BOOT_DEVICE(sniper_serial) = {
154 diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
155 index 21b3fdcf49cf..b2fcc28f8b4b 100644
156 --- a/board/logicpd/omap3som/omap3logic.c
157 +++ b/board/logicpd/omap3som/omap3logic.c
158 @@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR;
159 static const struct ns16550_platdata omap3logic_serial = {
160 .base = OMAP34XX_UART1,
161 .reg_shift = 2,
162 - .clock = V_NS16550_CLK
163 + .clock = V_NS16550_CLK,
164 + .fcr = UART_FCR_DEFVAL,
165 };
166
167 U_BOOT_DEVICE(omap3logic_uart) = {
168 diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
169 index 2821ee22674f..0fad23af62f6 100644
170 --- a/board/logicpd/zoom1/zoom1.c
171 +++ b/board/logicpd/zoom1/zoom1.c
172 @@ -47,7 +47,8 @@ static const u32 gpmc_lab_enet[] = {
173 static const struct ns16550_platdata zoom1_serial = {
174 .base = OMAP34XX_UART3,
175 .reg_shift = 2,
176 - .clock = V_NS16550_CLK
177 + .clock = V_NS16550_CLK,
178 + .fcr = UART_FCR_DEFVAL,
179 };
180
181 U_BOOT_DEVICE(zoom1_uart) = {
182 diff --git a/board/overo/overo.c b/board/overo/overo.c
183 index 40f13e5876cc..5e447262bcfd 100644
184 --- a/board/overo/overo.c
185 +++ b/board/overo/overo.c
186 @@ -70,7 +70,8 @@ static struct {
187 static const struct ns16550_platdata overo_serial = {
188 .base = OMAP34XX_UART3,
189 .reg_shift = 2,
190 - .clock = V_NS16550_CLK
191 + .clock = V_NS16550_CLK,
192 + .fcr = UART_FCR_DEFVAL,
193 };
194
195 U_BOOT_DEVICE(overo_uart) = {
196 diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
197 index 77e4482906f0..793aa9023150 100644
198 --- a/board/quipos/cairo/cairo.c
199 +++ b/board/quipos/cairo/cairo.c
200 @@ -93,7 +93,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
201 static const struct ns16550_platdata cairo_serial = {
202 .base = OMAP34XX_UART2,
203 .reg_shift = 2,
204 - .clock = V_NS16550_CLK
205 + .clock = V_NS16550_CLK,
206 + .fcr = UART_FCR_DEFVAL,
207 };
208
209 U_BOOT_DEVICE(cairo_uart) = {
210 diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
211 index cfdab3e34253..23c79333a223 100644
212 --- a/board/ti/beagle/beagle.c
213 +++ b/board/ti/beagle/beagle.c
214 @@ -75,7 +75,8 @@ static struct {
215 static const struct ns16550_platdata beagle_serial = {
216 .base = OMAP34XX_UART3,
217 .reg_shift = 2,
218 - .clock = V_NS16550_CLK
219 + .clock = V_NS16550_CLK,
220 + .fcr = UART_FCR_DEFVAL,
221 };
222
223 U_BOOT_DEVICE(beagle_uart) = {
224 diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
225 index f785dbe6d732..b2f060b2ddbf 100644
226 --- a/board/timll/devkit8000/devkit8000.c
227 +++ b/board/timll/devkit8000/devkit8000.c
228 @@ -48,7 +48,8 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
229 static const struct ns16550_platdata devkit8000_serial = {
230 .base = OMAP34XX_UART3,
231 .reg_shift = 2,
232 - .clock = V_NS16550_CLK
233 + .clock = V_NS16550_CLK,
234 + .fcr = UART_FCR_DEFVAL,
235 };
236
237 U_BOOT_DEVICE(devkit8000_uart) = {
238 diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
239 index 9b423a591d8a..2df4a1f04fe5 100644
240 --- a/drivers/serial/ns16550.c
241 +++ b/drivers/serial/ns16550.c
242 @@ -20,9 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
243 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
244 #define UART_MCRVAL (UART_MCR_DTR | \
245 UART_MCR_RTS) /* RTS/DTR */
246 -#define UART_FCRVAL (UART_FCR_FIFO_EN | \
247 - UART_FCR_RXSR | \
248 - UART_FCR_TXSR) /* Clear & enable FIFOs */
249
250 #ifndef CONFIG_DM_SERIAL
251 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
252 @@ -138,7 +135,7 @@ static u32 ns16550_getfcr(NS16550_t port)
253 #else
254 static u32 ns16550_getfcr(NS16550_t port)
255 {
256 - return UART_FCRVAL;
257 + return UART_FCR_DEFVAL;
258 }
259 #endif
260
261 @@ -275,7 +272,7 @@ static inline void _debug_uart_init(void)
262 CONFIG_BAUDRATE);
263 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
264 serial_dout(&com_port->mcr, UART_MCRVAL);
265 - serial_dout(&com_port->fcr, UART_FCRVAL);
266 + serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
267
268 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
269 serial_dout(&com_port->dll, baud_divisor & 0xff);
270 @@ -440,7 +437,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
271 return -EINVAL;
272 }
273
274 - plat->fcr = UART_FCRVAL;
275 + plat->fcr = UART_FCR_DEFVAL;
276 if (port_type == PORT_JZ4780)
277 plat->fcr |= UART_FCR_UME;
278
279 diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
280 index 6bac95a414ce..c06afc58f7ea 100644
281 --- a/drivers/serial/serial_rockchip.c
282 +++ b/drivers/serial/serial_rockchip.c
283 @@ -27,6 +27,7 @@ static int rockchip_serial_probe(struct udevice *dev)
284 plat->plat.base = plat->dtplat.reg[0];
285 plat->plat.reg_shift = plat->dtplat.reg_shift;
286 plat->plat.clock = plat->dtplat.clock_frequency;
287 + plat->plat.fcr = UART_FCR_DEFVAL;
288 dev->platdata = &plat->plat;
289
290 return ns16550_serial_probe(dev);
291 diff --git a/include/ns16550.h b/include/ns16550.h
292 index 7c9703683109..5fcbcd2e74e3 100644
293 --- a/include/ns16550.h
294 +++ b/include/ns16550.h
295 @@ -121,6 +121,11 @@ typedef struct NS16550 *NS16550_t;
296 /* Ingenic JZ47xx specific UART-enable bit. */
297 #define UART_FCR_UME 0x10
298
299 +/* Clear & enable FIFOs */
300 +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
301 + UART_FCR_RXSR | \
302 + UART_FCR_TXSR)
303 +
304 /*
305 * These are the definitions for the Modem Control Register
306 */
307 --
308 2.17.0
309
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