package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c

   1 /*
   2  * DO NOT MODIFY
   3  *
   4  * Declares the U_BOOT_DRIVER() records and platform data.
   5  * This was generated by dtoc from a .dtb (device tree binary) file.
   6  */
   7
   8 /* Allow use of U_BOOT_DRVINFO() in this file */
   9 #define DT_PLAT_C
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <dt-structs.h>
  14
  15 /* Node /clock-controller@ff440000 index 0 */
  16 static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
  17         .reg                    = {0xff440000, 0x1000},
  18         .rockchip_grf           = 0x3a,
  19 };
  20 U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
  21         .name           = "rockchip_rk3328_cru",
  22         .plat   = &dtv_clock_controller_at_ff440000,
  23         .plat_size      = sizeof(dtv_clock_controller_at_ff440000),
  24         .parent_idx     = -1,
  25 };
  26
  27 /* Node /dmc index 1 */
  28 static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
  29         .reg                    = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
  30                 0xff720000, 0x1000, 0xff798000, 0x1000},
  31         .rockchip_sdram_params  = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
  32                 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
  33                 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
  34                 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
  35                 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
  36                 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
  37                 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
  38                 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
  39                 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
  40                 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
  41                 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
  42                 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
  43                 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
  44                 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
  45                 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
  46                 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
  47                 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  48                 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
  49                 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
  50                 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  51                 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
  52                 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
  53                 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
  54                 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
  55                 0x77, 0x77, 0x79, 0x9},
  56 };
  57 U_BOOT_DRVINFO(dmc) = {
  58         .name           = "rockchip_rk3328_dmc",
  59         .plat   = &dtv_dmc,
  60         .plat_size      = sizeof(dtv_dmc),
  61         .parent_idx     = -1,
  62 };
  63
  64 /* Node /mmc@ff500000 index 2 */
  65 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
  66         .bus_width              = 0x4,
  67         .cap_sd_highspeed       = true,
  68         .clocks                 = {
  69                         {0, {317}},
  70                         {0, {33}},
  71                         {0, {74}},
  72                         {0, {78}},},
  73         .disable_wp             = true,
  74         .fifo_depth             = 0x100,
  75         .interrupts             = {0x0, 0xc, 0x4},
  76         .max_frequency          = 0x8f0d180,
  77         .pinctrl_0              = {0x47, 0x48, 0x49, 0x4a},
  78         .pinctrl_names          = "default",
  79         .reg                    = {0xff500000, 0x4000},
  80         .sd_uhs_sdr104          = true,
  81         .sd_uhs_sdr12           = true,
  82         .sd_uhs_sdr25           = true,
  83         .sd_uhs_sdr50           = true,
  84         .u_boot_spl_fifo_mode   = true,
  85         .vmmc_supply            = 0x4b,
  86         .vqmmc_supply           = 0x1e,
  87 };
  88 U_BOOT_DRVINFO(mmc_at_ff500000) = {
  89         .name           = "rockchip_rk3288_dw_mshc",
  90         .plat   = &dtv_mmc_at_ff500000,
  91         .plat_size      = sizeof(dtv_mmc_at_ff500000),
  92         .parent_idx     = -1,
  93 };
  94
  95 /* Node /serial@ff130000 index 3 */
  96 static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
  97         .clock_frequency        = 0x16e3600,
  98         .clocks                 = {
  99                         {0, {40}},
 100                         {0, {212}},},
 101         .dma_names              = {"tx", "rx"},
 102         .dmas                   = {0x10, 0x6, 0x10, 0x7},
 103         .interrupts             = {0x0, 0x39, 0x4},
 104         .pinctrl_0              = 0x26,
 105         .pinctrl_names          = "default",
 106         .reg                    = {0xff130000, 0x100},
 107         .reg_io_width           = 0x4,
 108         .reg_shift              = 0x2,
 109 };
 110 U_BOOT_DRVINFO(serial_at_ff130000) = {
 111         .name           = "ns16550_serial",
 112         .plat   = &dtv_serial_at_ff130000,
 113         .plat_size      = sizeof(dtv_serial_at_ff130000),
 114         .parent_idx     = -1,
 115 };
 116
 117 /* Node /syscon@ff100000 index 4 */
 118 static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
 119         .reg                    = {0xff100000, 0x1000},
 120 };
 121 U_BOOT_DRVINFO(syscon_at_ff100000) = {
 122         .name           = "rockchip_rk3328_grf",
 123         .plat   = &dtv_syscon_at_ff100000,
 124         .plat_size      = sizeof(dtv_syscon_at_ff100000),
 125         .parent_idx     = -1,
 126 };
 127