uboot-rockchip: update to v2021.07
[openwrt/openwrt.git] / package / boot / uboot-rockchip / src / of-platdata / nanopi-r2s-rk3328 / dt-plat.c
1 /*
2 * DO NOT MODIFY
3 *
4 * Declares the U_BOOT_DRIVER() records and platform data.
5 * This was generated by dtoc from a .dtb (device tree binary) file.
6 */
7
8 /* Allow use of U_BOOT_DRVINFO() in this file */
9 #define DT_PLAT_C
10
11 #include <common.h>
12 #include <dm.h>
13 #include <dt-structs.h>
14
15 /*
16 * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
17 *
18 * idx driver_info driver
19 * --- -------------------- --------------------
20 * 0: clock_controller_at_ff440000 rockchip_rk3328_cru
21 * 1: dmc rockchip_rk3328_dmc
22 * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
23 * 3: serial_at_ff130000 ns16550_serial
24 * 4: syscon_at_ff100000 rockchip_rk3328_grf
25 * --- -------------------- --------------------
26 */
27
28 /*
29 * Node /clock-controller@ff440000 index 0
30 * driver rockchip_rk3328_cru parent None
31 */
32 static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
33 .reg = {0xff440000, 0x1000},
34 .rockchip_grf = 0x3a,
35 };
36 U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
37 .name = "rockchip_rk3328_cru",
38 .plat = &dtv_clock_controller_at_ff440000,
39 .plat_size = sizeof(dtv_clock_controller_at_ff440000),
40 .parent_idx = -1,
41 };
42
43 /*
44 * Node /dmc index 1
45 * driver rockchip_rk3328_dmc parent None
46 */
47 static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
48 .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
49 0xff720000, 0x1000, 0xff798000, 0x1000},
50 .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
51 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
52 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
53 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
54 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
55 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
56 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
57 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
58 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
59 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
60 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
61 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
62 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
63 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
64 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
65 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
66 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
67 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
68 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
69 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
70 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
71 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
72 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
73 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
74 0x77, 0x77, 0x79, 0x9},
75 };
76 U_BOOT_DRVINFO(dmc) = {
77 .name = "rockchip_rk3328_dmc",
78 .plat = &dtv_dmc,
79 .plat_size = sizeof(dtv_dmc),
80 .parent_idx = -1,
81 };
82
83 /*
84 * Node /mmc@ff500000 index 2
85 * driver rockchip_rk3288_dw_mshc parent None
86 */
87 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
88 .bus_width = 0x4,
89 .cap_sd_highspeed = true,
90 .clocks = {
91 {0, {317}},
92 {0, {33}},
93 {0, {74}},
94 {0, {78}},},
95 .disable_wp = true,
96 .fifo_depth = 0x100,
97 .interrupts = {0x0, 0xc, 0x4},
98 .max_frequency = 0x8f0d180,
99 .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
100 .pinctrl_names = "default",
101 .reg = {0xff500000, 0x4000},
102 .sd_uhs_sdr104 = true,
103 .sd_uhs_sdr12 = true,
104 .sd_uhs_sdr25 = true,
105 .sd_uhs_sdr50 = true,
106 .u_boot_spl_fifo_mode = true,
107 .vmmc_supply = 0x4b,
108 .vqmmc_supply = 0x1e,
109 };
110 U_BOOT_DRVINFO(mmc_at_ff500000) = {
111 .name = "rockchip_rk3288_dw_mshc",
112 .plat = &dtv_mmc_at_ff500000,
113 .plat_size = sizeof(dtv_mmc_at_ff500000),
114 .parent_idx = -1,
115 };
116
117 /*
118 * Node /serial@ff130000 index 3
119 * driver ns16550_serial parent None
120 */
121 static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
122 .clock_frequency = 0x16e3600,
123 .clocks = {
124 {0, {40}},
125 {0, {212}},},
126 .dma_names = {"tx", "rx"},
127 .dmas = {0x10, 0x6, 0x10, 0x7},
128 .interrupts = {0x0, 0x39, 0x4},
129 .pinctrl_0 = 0x26,
130 .pinctrl_names = "default",
131 .reg = {0xff130000, 0x100},
132 .reg_io_width = 0x4,
133 .reg_shift = 0x2,
134 };
135 U_BOOT_DRVINFO(serial_at_ff130000) = {
136 .name = "ns16550_serial",
137 .plat = &dtv_serial_at_ff130000,
138 .plat_size = sizeof(dtv_serial_at_ff130000),
139 .parent_idx = -1,
140 };
141
142 /*
143 * Node /syscon@ff100000 index 4
144 * driver rockchip_rk3328_grf parent None
145 */
146 static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
147 .reg = {0xff100000, 0x1000},
148 };
149 U_BOOT_DRVINFO(syscon_at_ff100000) = {
150 .name = "rockchip_rk3328_grf",
151 .plat = &dtv_syscon_at_ff100000,
152 .plat_size = sizeof(dtv_syscon_at_ff100000),
153 .parent_idx = -1,
154 };
155