package/boot/uboot-sunxi/patches/010-sunxi-support-smta.patch

   1 diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
   2 index dfb0a3e..7a6a3cc 100644
   3 --- a/arch/arm/cpu/armv7/sunxi/Makefile
   4 +++ b/arch/arm/cpu/armv7/sunxi/Makefile
   5 @@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I)      += clock_sun6i.o
   6  endif
   7  obj-$(CONFIG_MACH_SUN9I)       += clock_sun9i.o
   8  obj-$(CONFIG_MACH_SUN6I)       += tzpc.o
   9 +obj-$(CONFIG_MACH_SUN8I)       += tzpc.o
  10
  11  obj-$(CONFIG_AXP152_POWER)     += pmic_bus.o
  12  obj-$(CONFIG_AXP209_POWER)     += pmic_bus.o
  13 diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
  14 index 5c9c69b..6c8a0fd 100644
  15 --- a/arch/arm/cpu/armv7/sunxi/tzpc.c
  16 +++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
  17 @@ -13,6 +13,15 @@ void tzpc_init(void)
  18  {
  19         struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
  20
  21 +#ifdef CONFIG_MACH_SUN6I
  22         /* Enable non-secure access to the RTC */
  23 -       writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
  24 +       writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
  25 +#endif
  26 +
  27 +#ifdef CONFIG_MACH_SUN8I_H3
  28 +       /* Enable non-secure access to all peripherals */
  29 +       writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
  30 +       writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
  31 +       writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
  32 +#endif
  33  }
  34 diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
  35 index ba4d43b..95c55cd 100644
  36 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h
  37 +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
  38 @@ -13,10 +13,21 @@ struct sunxi_tzpc {
  39         u32 decport0_status;    /* 0x04 Status of decode protection port 0 */
  40         u32 decport0_set;       /* 0x08 Set decode protection port 0 */
  41         u32 decport0_clear;     /* 0x0c Clear decode protection port 0 */
  42 +       /* For A80 and later SoCs */
  43 +       u32 decport1_status;    /* 0x10 Status of decode protection port 1 */
  44 +       u32 decport1_set;       /* 0x14 Set decode protection port 1 */
  45 +       u32 decport1_clear;     /* 0x18 Clear decode protection port 1 */
  46 +       u32 decport2_status;    /* 0x1c Status of decode protection port 2 */
  47 +       u32 decport2_set;       /* 0x20 Set decode protection port 2 */
  48 +       u32 decport2_clear;     /* 0x24 Clear decode protection port 2 */
  49  };
  50  #endif
  51
  52 -#define SUNXI_TZPC_DECPORT0_RTC        (1 << 1)
  53 +#define SUN6I_TZPC_DECPORT0_RTC        (1 << 1)
  54 +
  55 +#define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
  56 +#define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
  57 +#define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
  58
  59  void tzpc_init(void);
  60