package/boot/uboot-sunxi/patches/015-fix-2nd-usb-ctrler-on-sun47i.patch

   1 From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Mon, 21 Mar 2016 14:44:35 +0100
   4 Subject: [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
   5  working
   6
   7 The 2nd usb controller on sun4i/sun7i has its base address 0x8000
   8 bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
   9 are interleaved with the ohci clk-gates introducing a hole between
  10 the clks for usb1 and usb2.
  11
  12 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  13 Acked-by: Ian Campbell <ijc@hellion.org.uk>
  14 ---
  15  drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
  16  drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
  17  2 files changed, 23 insertions(+), 5 deletions(-)
  18
  19 diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
  20 index cf3dcc4..677a5d3 100644
  21 --- a/drivers/usb/host/ehci-sunxi.c
  22 +++ b/drivers/usb/host/ehci-sunxi.c
  23 @@ -17,6 +17,14 @@
  24  #include <dm.h>
  25  #include "ehci.h"
  26
  27 +#ifdef CONFIG_SUNXI_GEN_SUN4I
  28 +#define BASE_DIST              0x8000
  29 +#define AHB_CLK_DIST           2
  30 +#else
  31 +#define BASE_DIST              0x1000
  32 +#define AHB_CLK_DIST           1
  33 +#endif
  34 +
  35  struct ehci_sunxi_priv {
  36         struct ehci_ctrl ehci;
  37         int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
  38 @@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev)
  39  #ifdef CONFIG_MACH_SUN8I_H3
  40         priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
  41  #endif
  42 -       priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
  43 -       priv->ahb_gate_mask <<= priv->phy_index - 1;
  44 +       priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
  45 +       priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
  46 +       priv->phy_index++; /* Non otg phys start at 1 */
  47
  48         setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
  49  #ifdef CONFIG_SUNXI_GEN_SUN6I
  50 diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
  51 index 1b1f651..d4fb95a 100644
  52 --- a/drivers/usb/host/ohci-sunxi.c
  53 +++ b/drivers/usb/host/ohci-sunxi.c
  54 @@ -17,6 +17,14 @@
  55  #include <usb.h>
  56  #include "ohci.h"
  57
  58 +#ifdef CONFIG_SUNXI_GEN_SUN4I
  59 +#define BASE_DIST              0x8000
  60 +#define AHB_CLK_DIST           2
  61 +#else
  62 +#define BASE_DIST              0x1000
  63 +#define AHB_CLK_DIST           1
  64 +#endif
  65 +
  66  struct ohci_sunxi_priv {
  67         ohci_t ohci;
  68         int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
  69 @@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev)
  70         priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
  71  #endif
  72         priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
  73 -       priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
  74 -       priv->ahb_gate_mask <<= priv->phy_index - 1;
  75 -       priv->usb_gate_mask <<= priv->phy_index - 1;
  76 +       priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
  77 +       priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
  78 +       priv->usb_gate_mask <<= priv->phy_index;
  79 +       priv->phy_index++; /* Non otg phys start at 1 */
  80
  81         setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
  82         setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);