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mac80211: add support for mt7620
[openwrt/openwrt.git] / package / kernel / mac80211 / patches / 910-01-add-support-for-mt7620.patch
1 --- a/drivers/net/wireless/rt2x00/rt2800.h 2014-06-30 01:05:26.000000000 +0300
2 +++ b/drivers/net/wireless/rt2x00/rt2800.h 2014-06-30 01:23:42.000000000 +0300
3 @@ -79,6 +79,7 @@
4 #define RF5372 0x5372
5 #define RF5390 0x5390
6 #define RF5392 0x5392
7 +#define RF7620 0x7620
8
9 /*
10 * Chipset revisions.
11 @@ -654,6 +655,14 @@
12 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
13
14 /*
15 + * mt7620 RF registers (reversed order)
16 + */
17 +#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
18 +#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
19 +#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
20 +#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
21 +
22 +/*
23 * EFUSE_CSR: RT30x0 EEPROM
24 */
25 #define EFUSE_CTRL 0x0580
26 @@ -1037,6 +1046,11 @@
27 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
28
29 /*
30 + * mt7620
31 + */
32 +#define MIMO_PS_CFG 0x1210
33 +
34 +/*
35 * EDCA_AC0_CFG:
36 */
37 #define EDCA_AC0_CFG 0x1300
38 @@ -1216,6 +1230,8 @@
39 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
40 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
41 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
42 +#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000) /* mt7620 */
43 +#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000) /* mt7620 */
44 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
45 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
46 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
47 @@ -1562,6 +1578,17 @@
48 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
49 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
50
51 +/* mt7620 */
52 +#define TX0_RF_GAIN_CORRECT 0x13a0
53 +#define TX1_RF_GAIN_CORRECT 0x13a4
54 +#define TX0_RF_GAIN_ATTEN 0x13a8
55 +#define TX1_RF_GAIN_ATTEN 0x13ac
56 +#define TX_ALG_CFG_0 0x13b0
57 +#define TX_ALG_CFG_1 0x13b4
58 +#define TX0_BB_GAIN_ATTEN 0x13c0
59 +#define TX1_BB_GAIN_ATTEN 0x13c4
60 +#define TX_ALC_VGA3 0x13c8
61 +
62 /* TX_PWR_CFG_7 */
63 #define TX_PWR_CFG_7 0x13d4
64 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
65 --- a/drivers/net/wireless/rt2x00/rt2800lib.c 2014-06-30 01:05:26.000000000 +0300
66 +++ b/drivers/net/wireless/rt2x00/rt2800lib.c 2014-06-30 17:31:35.000000000 +0300
67 @@ -61,6 +61,8 @@
68 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
69 #define WAIT_FOR_RFCSR(__dev, __reg) \
70 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
71 +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
72 + rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, (__reg))
73 #define WAIT_FOR_RF(__dev, __reg) \
74 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
75 #define WAIT_FOR_MCU(__dev, __reg) \
76 @@ -186,19 +188,55 @@ static void rt2800_rfcsr_write(struct rt
77 * Wait until the RFCSR becomes available, afterwards we
78 * can safely write the new data into the register.
79 */
80 - if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
81 - reg = 0;
82 - rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
83 - rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
84 - rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
85 - rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
86 + switch (rt2x00dev->chip.rf) {
87 + case RF7620:
88 + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
89 + reg = 0;
90 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
91 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620, word);
92 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
93 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
94 +
95 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
96 + }
97 + break;
98 +
99 + default:
100 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
101 + reg = 0;
102 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
103 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
104 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
105 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
106
107 - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
108 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
109 + }
110 + break;
111 }
112
113 mutex_unlock(&rt2x00dev->csr_mutex);
114 }
115
116 +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
117 + const unsigned int reg, const u8 value)
118 +{
119 + rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
120 +}
121 +
122 +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
123 + const unsigned int reg, const u8 value)
124 +{
125 + rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
126 + rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
127 +}
128 +
129 +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
130 + const unsigned int reg, const u8 value)
131 +{
132 + rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
133 + rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
134 +}
135 +
136 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
137 const unsigned int word, u8 *value)
138 {
139 @@ -214,22 +252,47 @@ static void rt2800_rfcsr_read(struct rt2
140 * doesn't become available in time, reg will be 0xffffffff
141 * which means we return 0xff to the caller.
142 */
143 - if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
144 - reg = 0;
145 - rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
146 - rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
147 - rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
148 + switch (rt2x00dev->chip.rf) {
149 + case RF7620:
150 + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
151 + reg = 0;
152 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620, word);
153 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
154 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
155
156 - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
157 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
158
159 - WAIT_FOR_RFCSR(rt2x00dev, &reg);
160 - }
161 + WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
162 + }
163
164 - *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
165 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
166 + break;
167 +
168 + default:
169 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
170 + reg = 0;
171 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
172 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
174 +
175 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
176 +
177 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
178 + }
179 +
180 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
181 + break;
182 + }
183
184 mutex_unlock(&rt2x00dev->csr_mutex);
185 }
186
187 +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
188 + const unsigned int reg, u8 *value)
189 +{
190 + rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
191 +}
192 +
193 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, const u32 value)
195 {
196 @@ -566,6 +629,13 @@ void rt2800_get_txwi_rxwi_size(struct rt
197 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
198 break;
199
200 + case RT5390:
201 + if ( rt2x00dev->chip.rf == RF7620 ) {
202 + *txwi_size = TXWI_DESC_SIZE_5WORDS;
203 + *rxwi_size = RXWI_DESC_SIZE_6WORDS;
204 + }
205 + break;
206 +
207 case RT5592:
208 *txwi_size = TXWI_DESC_SIZE_5WORDS;
209 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
210 @@ -3326,6 +3396,312 @@ static void rt2800_config_channel_rf55xx
211 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
212 }
213
214 +typedef struct mt7620_freqconfig {
215 + u8 Channel;
216 + u8 Rdiv;
217 + u16 N;
218 + u8 K;
219 + u8 D;
220 + u32 Ksd;
221 +} mt7620_freqconfig;
222 +
223 +mt7620_freqconfig mt7620_chanconfig[] =
224 +{
225 + /* 2.4 to 2.483 GHz
226 + * CH Rdiv N K D Ksd */
227 + { 0, 0, 0, 0, 0, 0 },
228 + { 1, 3, 0x50, 0, 0, 0x19999 },
229 + { 2, 3, 0x50, 0, 0, 0x24444 },
230 + { 3, 3, 0x50, 0, 0, 0x2EEEE },
231 + { 4, 3, 0x50, 0, 0, 0x39999 },
232 + { 5, 3, 0x51, 0, 0, 0x04444 },
233 + { 6, 3, 0x51, 0, 0, 0x0EEEE },
234 + { 7, 3, 0x51, 0, 0, 0x19999 },
235 + { 8, 3, 0x51, 0, 0, 0x24444 },
236 + { 9, 3, 0x51, 0, 0, 0x2EEEE },
237 + { 10, 3, 0x51, 0, 0, 0x39999 },
238 + { 11, 3, 0x52, 0, 0, 0x04444 },
239 + { 12, 3, 0x52, 0, 0, 0x0EEEE },
240 + { 13, 3, 0x52, 0, 0, 0x19999 },
241 + { 14, 3, 0x52, 0, 0, 0x33333 },
242 +};
243 +
244 +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
245 + struct ieee80211_conf *conf,
246 + struct rf_channel *rf,
247 + struct channel_info *info)
248 +{
249 + int i;
250 + u8 bbp;
251 + u8 rfcsr;
252 + u8 txrx_agc_fc;
253 + u32 reg;
254 + u16 eeprom, target_power;
255 + u32 mac_sys_ctrl, mac_status;
256 + u32 tx_pin = 0x00150F0F;
257 + struct hw_mode_spec *spec = &rt2x00dev->spec;
258 +
259 + /* Frequeny plan setting */
260 + /*
261 + * Rdiv setting
262 + * R13[1:0]
263 + */
264 + rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
265 + rfcsr = rfcsr & (~0x03);
266 + if (spec->clk_is_20mhz)
267 + rfcsr |= (mt7620_chanconfig[rf->channel].Rdiv & 0x3);
268 + rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
269 +
270 + /*
271 + * N setting
272 + * R21[0], R20[7:0]
273 + */
274 + rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
275 + rfcsr = (mt7620_chanconfig[rf->channel].N & 0x00ff);
276 + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
277 +
278 + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
279 + rfcsr = rfcsr & (~0x01);
280 + rfcsr |= ((mt7620_chanconfig[rf->channel].N & 0x0100) >> 8);
281 + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
282 +
283 + /*
284 + * K setting
285 + * R16[3:0] (RF PLL freq selection)
286 + */
287 + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
288 + rfcsr = rfcsr & (~0x0f);
289 + rfcsr |= (mt7620_chanconfig[rf->channel].K & 0x0f);
290 + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
291 +
292 + /*
293 + * D setting
294 + * R22[2:0] (D=15, R22[2:0]=<111>)
295 + */
296 + rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
297 + rfcsr = rfcsr & (~0x07);
298 + rfcsr |= (mt7620_chanconfig[rf->channel].D & 0x07);
299 + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
300 +
301 + /*
302 + * Ksd setting
303 + * Ksd: R19<1:0>,R18<7:0>,R17<7:0>
304 + */
305 + rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
306 + rfcsr = (mt7620_chanconfig[rf->channel].Ksd & 0x000000ff);
307 + rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
308 +
309 + rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
310 + rfcsr = ((mt7620_chanconfig[rf->channel].Ksd & 0x0000ff00) >> 8);
311 + rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
312 +
313 + rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
314 + rfcsr = rfcsr & (~0x03);
315 + rfcsr |= ((mt7620_chanconfig[rf->channel].Ksd & 0x00030000) >> 16);
316 + rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
317 +
318 + /* Default: XO=20MHz , SDM mode */
319 + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
320 + rfcsr = rfcsr & (~0xE0);
321 + rfcsr |= 0x80;
322 + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
323 +
324 + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
325 + rfcsr |= 0x80;
326 + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
327 +
328 + rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
329 + if (rt2x00dev->default_ant.tx_chain_num == 1)
330 + rfcsr &= (~0x2);
331 + else
332 + rfcsr |= 0x2;
333 + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
334 +
335 + rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
336 + if (rt2x00dev->default_ant.tx_chain_num == 1)
337 + rfcsr &= (~0x20);
338 + else
339 + rfcsr |= 0x20;
340 + if (rt2x00dev->default_ant.rx_chain_num == 1)
341 + rfcsr &= (~0x02);
342 + else
343 + rfcsr |= 0x02;
344 + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
345 +
346 + rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
347 + if (rt2x00dev->default_ant.tx_chain_num == 1)
348 + rfcsr &= (~0x40);
349 + else
350 + rfcsr |= 0x40;
351 + rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
352 +
353 + /* RF for DC Cal BW */
354 + if (conf_is_ht40(conf)) {
355 + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
356 + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
357 + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
358 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
359 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
360 + } else {
361 + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
362 + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
363 + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
364 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
365 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
366 + }
367 +
368 + if (conf_is_ht40(conf)) {
369 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
370 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
371 + } else {
372 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
373 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
374 + }
375 +
376 + rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
377 + if (conf_is_ht40(conf) && (rf->channel == 11))
378 + rfcsr |= 0x4;
379 + else
380 + rfcsr &= (~0x4);
381 + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
382 +
383 + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
384 + /*if (bScan == FALSE)*/
385 + if (conf_is_ht40(conf)) {
386 + txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
387 + RFCSR24_TX_AGC_FC);
388 + } else {
389 + txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
390 + RFCSR24_TX_AGC_FC);
391 + }
392 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
393 + rfcsr &= (~0x3F);
394 + rfcsr |= txrx_agc_fc;
395 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
396 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
397 + rfcsr &= (~0x3F);
398 + rfcsr |= txrx_agc_fc;
399 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
400 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
401 + rfcsr &= (~0x3F);
402 + rfcsr |= txrx_agc_fc;
403 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
404 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
405 + rfcsr &= (~0x3F);
406 + rfcsr |= txrx_agc_fc;
407 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
408 +
409 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
410 + rfcsr &= (~0x3F);
411 + rfcsr |= txrx_agc_fc;
412 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
413 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
414 + rfcsr &= (~0x3F);
415 + rfcsr |= txrx_agc_fc;
416 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
417 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
418 + rfcsr &= (~0x3F);
419 + rfcsr |= txrx_agc_fc;
420 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
421 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
422 + rfcsr &= (~0x3F);
423 + rfcsr |= txrx_agc_fc;
424 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
425 +
426 + rt2800_register_read(rt2x00dev, TX_ALG_CFG_0, &reg);
427 + reg = reg & (~0x3F3F);
428 + reg |= info->default_power1;
429 + reg |= (info->default_power2 << 8);
430 + reg |= (0x2F << 16);
431 + reg |= (0x2F << 24);
432 +
433 + rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
434 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
435 + /* init base power by e2p target power */
436 + rt2800_eeprom_read(rt2x00dev, 0xD0, &target_power);
437 + target_power &= 0x3F;
438 + reg = reg & (~0x3F3F);
439 + reg |= target_power;
440 + reg |= (target_power << 8);
441 + }
442 + rt2800_register_write(rt2x00dev, TX_ALG_CFG_0, reg);
443 +
444 + rt2800_register_read(rt2x00dev, TX_ALG_CFG_1, &reg);
445 + reg = reg & (~0x3F);
446 + rt2800_register_write(rt2x00dev, TX_ALG_CFG_1, reg);
447 +
448 + /*if (bScan == FALSE)*/
449 + /* Save MAC SYS CTRL registers */
450 + rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
451 + /* Disable Tx/Rx */
452 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
453 + /* Check MAC Tx/Rx idle */
454 + for (i = 0; i < 10000; i++) {
455 + rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &mac_status);
456 + if (mac_status & 0x3)
457 + udelay(50);
458 + else
459 + break;
460 + }
461 +
462 + if (i == 10000)
463 + rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
464 +
465 + if (rf->channel > 10) {
466 + rt2800_bbp_read(rt2x00dev, 30, &bbp);
467 + bbp = 0x40;
468 + rt2800_bbp_write(rt2x00dev, 30, bbp);
469 + rt2800_rfcsr_write(rt2x00dev, 39, 0);
470 + rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
471 + } else {
472 + rt2800_bbp_read(rt2x00dev, 30, &bbp);
473 + bbp = 0x1f;
474 + rt2800_bbp_write(rt2x00dev, 30, bbp);
475 + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
476 + rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
477 + }
478 +
479 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
480 +
481 + rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
482 + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
483 +
484 + /* vcocal_en (initiate VCO calibration (reset after completion)) */
485 + rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
486 + rfcsr = ((rfcsr & ~0x80) | 0x80);
487 + rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
488 + mdelay(2);
489 +
490 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
491 +
492 + if (rt2x00dev->default_ant.tx_chain_num == 1) {
493 + rt2800_bbp_write(rt2x00dev, 91, 0x07);
494 + rt2800_bbp_write(rt2x00dev, 95, 0x1A);
495 + rt2800_bbp_write(rt2x00dev, 195, 128);
496 + rt2800_bbp_write(rt2x00dev, 196, 0xA0);
497 + rt2800_bbp_write(rt2x00dev, 195, 170);
498 + rt2800_bbp_write(rt2x00dev, 196, 0x12);
499 + rt2800_bbp_write(rt2x00dev, 195, 171);
500 + rt2800_bbp_write(rt2x00dev, 196, 0x10);
501 + } else {
502 + rt2800_bbp_write(rt2x00dev, 91, 0x06);
503 + rt2800_bbp_write(rt2x00dev, 95, 0x9A);
504 + rt2800_bbp_write(rt2x00dev, 195, 128);
505 + rt2800_bbp_write(rt2x00dev, 196, 0xE0);
506 + rt2800_bbp_write(rt2x00dev, 195, 170);
507 + rt2800_bbp_write(rt2x00dev, 196, 0x30);
508 + rt2800_bbp_write(rt2x00dev, 195, 171);
509 + rt2800_bbp_write(rt2x00dev, 196, 0x30);
510 + }
511 +
512 + /* On 11A, We should delay and wait RF/BBP to be stable*/
513 + /* and the appropriate time should be 1000 micro seconds */
514 + /* 2005/06/05 - On 11G, We also need this delay time.
515 + * Otherwise it's difficult to pass the WHQL.*/
516 + udelay(1000);
517 +}
518 +
519 +
520 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
521 const unsigned int word,
522 const u8 value)
523 @@ -3482,7 +3858,7 @@ static void rt2800_config_channel(struct
524 struct channel_info *info)
525 {
526 u32 reg;
527 - unsigned int tx_pin;
528 + u32 tx_pin;
529 u8 bbp, rfcsr;
530
531 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
532 @@ -3535,6 +3911,9 @@ static void rt2800_config_channel(struct
533 case RF5592:
534 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
535 break;
536 + case RF7620:
537 + rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
538 + break;
539 default:
540 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
541 }
542 @@ -3631,7 +4010,7 @@ static void rt2800_config_channel(struct
543 else if (rt2x00_rt(rt2x00dev, RT3593) ||
544 rt2x00_rt(rt2x00dev, RT3883))
545 rt2800_bbp_write(rt2x00dev, 82, 0x82);
546 - else
547 + else if (rt2x00dev->chip.rf != RF7620)
548 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
549
550 if (rt2x00_rt(rt2x00dev, RT3593) ||
551 @@ -3653,7 +4032,7 @@ static void rt2800_config_channel(struct
552 if (rt2x00_rt(rt2x00dev, RT3572))
553 rt2800_rfcsr_write(rt2x00dev, 8, 0);
554
555 - tx_pin = 0;
556 + rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
557
558 switch (rt2x00dev->default_ant.tx_chain_num) {
559 case 3:
560 @@ -3702,6 +4081,7 @@ static void rt2800_config_channel(struct
561
562 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
563 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
564 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
565
566 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
567
568 @@ -4710,6 +5090,14 @@ void rt2800_vco_calibration(struct rt2x0
569 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
570 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
571 break;
572 + case RF7620:
573 + rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
574 + /* vcocal_en (initiate VCO calibration (reset after completion))
575 + * It should be at the end of RF configuration. */
576 + rfcsr = ((rfcsr & ~0x80) | 0x80);
577 + rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
578 + mdelay(1);
579 + break;
580 default:
581 return;
582 }
583 @@ -5110,9 +5498,42 @@ static int rt2800_init_registers(struct
584 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
585 rt2x00_rt(rt2x00dev, RT5392) ||
586 rt2x00_rt(rt2x00dev, RT5592)) {
587 - rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
588 - rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
589 - rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
590 + if (rt2x00dev->chip.rf == RF7620) {
591 + rt2800_register_write(rt2x00dev, TX_SW_CFG0,
592 + 0x00000401);
593 + rt2800_register_write(rt2x00dev, TX_SW_CFG1,
594 + 0x000C0000);
595 + rt2800_register_write(rt2x00dev, TX_SW_CFG2,
596 + 0x00000000);
597 + rt2800_register_write(rt2x00dev, MIMO_PS_CFG,
598 + 0x00000002);
599 + rt2800_register_write(rt2x00dev, TX_PIN_CFG,
600 + 0x00150F0F);
601 + rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
602 + 0x06060606);
603 + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN,
604 + 0x0);
605 + rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN,
606 + 0x0);
607 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
608 + 0x6C6C666C);
609 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
610 + 0x6C6C666C);
611 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
612 + 0x3630363A);
613 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
614 + 0x3630363A);
615 + rt2800_register_read(rt2x00dev, TX_ALG_CFG_1, &reg);
616 + reg = reg & (~0x80000000);
617 + rt2800_register_write(rt2x00dev, TX_ALG_CFG_1, reg);
618 + } else {
619 + rt2800_register_write(rt2x00dev, TX_SW_CFG0,
620 + 0x00000404);
621 + rt2800_register_write(rt2x00dev, TX_SW_CFG1,
622 + 0x00080606);
623 + rt2800_register_write(rt2x00dev, TX_SW_CFG2,
624 + 0x00000000);
625 + }
626 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
627 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
628 } else {
629 @@ -6144,6 +6565,225 @@ static void rt2800_init_bbp_5592(struct
630 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
631 }
632
633 +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
634 + const u8 reg, const u8 value)
635 +{
636 + rt2800_bbp_write(rt2x00dev, 195, reg);
637 + rt2800_bbp_write(rt2x00dev, 196, value);
638 +}
639 +
640 +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
641 + const u8 reg, const u8 value)
642 +{
643 + rt2800_bbp_write(rt2x00dev, 158, reg);
644 + rt2800_bbp_write(rt2x00dev, 159, value);
645 +}
646 +
647 +static void rt2800_init_bbp_7620(struct rt2x00_dev *rt2x00dev)
648 +{
649 + u8 bbp;
650 +
651 + /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
652 + rt2800_bbp_read(rt2x00dev, 105, &bbp);
653 + rt2x00_set_field8(&bbp, BBP105_MLD,
654 + rt2x00dev->default_ant.rx_chain_num == 2);
655 + rt2800_bbp_write(rt2x00dev, 105, bbp);
656 +
657 + /* Avoid data loss and CRC errors */
658 + /* MAC interface control (MAC_IF_80M, 1: 80 MHz) */
659 + rt2800_bbp4_mac_if_ctrl(rt2x00dev);
660 +
661 + /* Fix I/Q swap issue */
662 + rt2800_bbp_read(rt2x00dev, 1, &bbp);
663 + bbp |= 0x04;
664 + rt2800_bbp_write(rt2x00dev, 1, bbp);
665 +
666 + /* BBP for G band */
667 + rt2800_bbp_write(rt2x00dev, 3, 0x08);
668 + rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
669 + rt2800_bbp_write(rt2x00dev, 6, 0x08);
670 + rt2800_bbp_write(rt2x00dev, 14, 0x09);
671 + rt2800_bbp_write(rt2x00dev, 15, 0xFF);
672 + rt2800_bbp_write(rt2x00dev, 16, 0x01);
673 + rt2800_bbp_write(rt2x00dev, 20, 0x06);
674 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
675 + rt2800_bbp_write(rt2x00dev, 22, 0x00);
676 + rt2800_bbp_write(rt2x00dev, 27, 0x00);
677 + rt2800_bbp_write(rt2x00dev, 28, 0x00);
678 + rt2800_bbp_write(rt2x00dev, 30, 0x00);
679 + rt2800_bbp_write(rt2x00dev, 31, 0x48);
680 + rt2800_bbp_write(rt2x00dev, 47, 0x40);
681 + rt2800_bbp_write(rt2x00dev, 62, 0x00);
682 + rt2800_bbp_write(rt2x00dev, 63, 0x00);
683 + rt2800_bbp_write(rt2x00dev, 64, 0x00);
684 + rt2800_bbp_write(rt2x00dev, 65, 0x2C);
685 + rt2800_bbp_write(rt2x00dev, 66, 0x1C);
686 + rt2800_bbp_write(rt2x00dev, 67, 0x20);
687 + rt2800_bbp_write(rt2x00dev, 68, 0xDD);
688 + rt2800_bbp_write(rt2x00dev, 69, 0x10);
689 + rt2800_bbp_write(rt2x00dev, 70, 0x05);
690 + rt2800_bbp_write(rt2x00dev, 73, 0x18);
691 + rt2800_bbp_write(rt2x00dev, 74, 0x0F);
692 + rt2800_bbp_write(rt2x00dev, 75, 0x60);
693 + rt2800_bbp_write(rt2x00dev, 76, 0x44);
694 + rt2800_bbp_write(rt2x00dev, 77, 0x59);
695 + rt2800_bbp_write(rt2x00dev, 78, 0x1E);
696 + rt2800_bbp_write(rt2x00dev, 79, 0x1C);
697 + rt2800_bbp_write(rt2x00dev, 80, 0x0C);
698 + rt2800_bbp_write(rt2x00dev, 81, 0x3A);
699 + rt2800_bbp_write(rt2x00dev, 82, 0xB6);
700 + rt2800_bbp_write(rt2x00dev, 83, 0x9A);
701 + rt2800_bbp_write(rt2x00dev, 84, 0x9A);
702 + rt2800_bbp_write(rt2x00dev, 86, 0x38);
703 + rt2800_bbp_write(rt2x00dev, 88, 0x90);
704 + rt2800_bbp_write(rt2x00dev, 91, 0x04);
705 + rt2800_bbp_write(rt2x00dev, 92, 0x02);
706 + rt2800_bbp_write(rt2x00dev, 95, 0x9A);
707 + rt2800_bbp_write(rt2x00dev, 96, 0x00);
708 + rt2800_bbp_write(rt2x00dev, 103, 0xC0);
709 + rt2800_bbp_write(rt2x00dev, 104, 0x92);
710 + /* FIXME BBP105 owerwrite */
711 + rt2800_bbp_write(rt2x00dev, 105, 0x3C);
712 + rt2800_bbp_write(rt2x00dev, 106, 0x12);
713 + rt2800_bbp_write(rt2x00dev, 109, 0x00);
714 + rt2800_bbp_write(rt2x00dev, 134, 0x10);
715 + rt2800_bbp_write(rt2x00dev, 135, 0xA6);
716 + rt2800_bbp_write(rt2x00dev, 137, 0x04);
717 + rt2800_bbp_write(rt2x00dev, 142, 0x30);
718 + rt2800_bbp_write(rt2x00dev, 143, 0xF7);
719 + rt2800_bbp_write(rt2x00dev, 160, 0xEC);
720 + rt2800_bbp_write(rt2x00dev, 161, 0xC4);
721 + rt2800_bbp_write(rt2x00dev, 162, 0x77);
722 + rt2800_bbp_write(rt2x00dev, 163, 0xF9);
723 + rt2800_bbp_write(rt2x00dev, 164, 0x00);
724 + rt2800_bbp_write(rt2x00dev, 165, 0x00);
725 + rt2800_bbp_write(rt2x00dev, 186, 0x00);
726 + rt2800_bbp_write(rt2x00dev, 187, 0x00);
727 + rt2800_bbp_write(rt2x00dev, 188, 0x00);
728 + rt2800_bbp_write(rt2x00dev, 186, 0x00);
729 + rt2800_bbp_write(rt2x00dev, 187, 0x01);
730 + rt2800_bbp_write(rt2x00dev, 188, 0x00);
731 + rt2800_bbp_write(rt2x00dev, 189, 0x00);
732 +
733 + rt2800_bbp_write(rt2x00dev, 91, 0x06);
734 + rt2800_bbp_write(rt2x00dev, 92, 0x04);
735 + rt2800_bbp_write(rt2x00dev, 93, 0x54);
736 + rt2800_bbp_write(rt2x00dev, 99, 0x50);
737 + rt2800_bbp_write(rt2x00dev, 148, 0x84);
738 + rt2800_bbp_write(rt2x00dev, 167, 0x80);
739 + rt2800_bbp_write(rt2x00dev, 178, 0xFF);
740 + rt2800_bbp_write(rt2x00dev, 106, 0x13);
741 +
742 + /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
743 + rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
744 + rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); /* ? see above */
745 + rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
746 + rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
747 + rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
748 + rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
749 + rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
750 + rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
751 + rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
752 + rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
753 + rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
754 + rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
755 + rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
756 + rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
757 + rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
758 + rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
759 + rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
760 + rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
761 + rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
762 + rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
763 + rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
764 + rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
765 + rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
766 + rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
767 + rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
768 + rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
769 + rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
770 + rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
771 + rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
772 + rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
773 + rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
774 + rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
775 + rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
776 + rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
777 + rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
778 + rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
779 + rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
780 + rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
781 + rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
782 + rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
783 + rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
784 + rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
785 + rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
786 + rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
787 + rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
788 + rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
789 + rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
790 + rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
791 + rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
792 + rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
793 + rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
794 + rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
795 + rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
796 + rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
797 + rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
798 + rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
799 + rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
800 + rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
801 + rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
802 + rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
803 + rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
804 + rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
805 + rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
806 + rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
807 + rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
808 + rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
809 + rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
810 + rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
811 + rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
812 + rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
813 + rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
814 + rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
815 + rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
816 + rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
817 + rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
818 + rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
819 + rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
820 + rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
821 + rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
822 + rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
823 + rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
824 + rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
825 + rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
826 +
827 + /* BBP for G band DCOC function */
828 + rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
829 + rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
830 + rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
831 + rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
832 + rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
833 + rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
834 + rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
835 + rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
836 + rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
837 + rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
838 + rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
839 + rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
840 + rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
841 + rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
842 + rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
843 + rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
844 + rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
845 + rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
846 + rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
847 + rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
848 +
849 + rt2800_bbp4_mac_if_ctrl(rt2x00dev);
850 +}
851 +
852 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
853 {
854 unsigned int i;
855 @@ -6186,7 +6826,10 @@ static void rt2800_init_bbp(struct rt2x0
856 return;
857 case RT5390:
858 case RT5392:
859 - rt2800_init_bbp_53xx(rt2x00dev);
860 + if (rt2x00dev->chip.rf == RF7620)
861 + rt2800_init_bbp_7620(rt2x00dev);
862 + else
863 + rt2800_init_bbp_53xx(rt2x00dev);
864 break;
865 case RT5592:
866 rt2800_init_bbp_5592(rt2x00dev);
867 @@ -7400,6 +8043,295 @@ static void rt2800_init_rfcsr_5592(struc
868 rt2800_led_open_drain_enable(rt2x00dev);
869 }
870
871 +static void rt2800_init_rfcsr_7620(struct rt2x00_dev *rt2x00dev)
872 +{
873 + u16 freq;
874 + u8 rfvalue;
875 + /* Initialize RF central register to default value */
876 + rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
877 + rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
878 + rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
879 + rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
880 + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
881 + rt2800_rfcsr_write(rt2x00dev, 5, 0x40); /* Read only */
882 + rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
883 + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
884 + rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
885 + rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
886 + rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
887 + rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
888 + /* rt2800_rfcsr_write(rt2x00dev, 12, 0x43); *//* EEPROM */
889 + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
890 + rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
891 + rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
892 + rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
893 + rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
894 + rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
895 + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
896 + rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
897 + rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
898 + rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
899 + rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
900 + rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
901 + rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
902 + rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
903 + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
904 + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
905 + rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
906 + rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
907 + rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
908 + rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
909 + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
910 + rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
911 + rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
912 + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
913 + rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
914 + rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
915 + rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
916 + rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
917 + rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
918 + rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
919 + rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
920 +
921 + struct hw_mode_spec *spec = &rt2x00dev->spec;
922 + rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
923 + if (spec->clk_is_20mhz)
924 + rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
925 + else
926 + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
927 + rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
928 + rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
929 + rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
930 + rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
931 + rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
932 + rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
933 + rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
934 + rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
935 + rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
936 + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
937 + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
938 + rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
939 + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
940 + rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
941 + rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
942 + rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
943 +
944 + rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
945 + rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
946 + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
947 + /* RTMP_TEMPERATURE_CALIBRATION */
948 + /* rt2800_rfcsr_write(rt2x00dev, 34, 0x23); */
949 + /* rt2800_rfcsr_write(rt2x00dev, 35, 0x01); */
950 +
951 + /* use rt2800_adjust_freq_offset ? */
952 + rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &freq);
953 + rfvalue = freq & 0xff;
954 + rt2800_rfcsr_write(rt2x00dev, 12, rfvalue);
955 +
956 + /* Initialize RF channel register to default value */
957 + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
958 + rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
959 + rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
960 + rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
961 + rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
962 + rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
963 + rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
964 + rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
965 + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
966 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
967 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
968 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
969 + rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
970 + /* rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); */ /* fails */
971 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
972 + rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
973 + rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
974 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
975 + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
976 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
977 + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
978 + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
979 + rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
980 + rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
981 + rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
982 + rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
983 + rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
984 + rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
985 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
986 + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
987 + rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
988 + rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
989 + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
990 + rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
991 + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
992 + rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
993 + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
994 + rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
995 + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
996 + rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
997 + rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
998 + rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
999 + rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
1000 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
1001 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
1002 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1003 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
1004 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
1005 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
1006 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
1007 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
1008 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
1009 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
1010 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
1011 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
1012 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
1013 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
1014 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
1015 + rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
1016 + rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
1017 +
1018 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
1019 +
1020 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
1021 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
1022 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
1023 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
1024 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
1025 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
1026 + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
1027 + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
1028 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
1029 + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
1030 + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
1031 + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
1032 + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
1033 + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
1034 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1035 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
1036 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1037 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
1038 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
1039 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
1040 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
1041 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1042 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
1043 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
1044 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
1045 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1046 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
1047 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
1048 +
1049 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
1050 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1051 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1052 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
1053 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1054 + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
1055 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
1056 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1057 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
1058 +
1059 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
1060 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
1061 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
1062 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
1063 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1064 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1065 +
1066 + /* Initialize RF channel register for DRQFN */
1067 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1068 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
1069 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
1070 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
1071 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
1072 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
1073 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
1074 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
1075 +
1076 + /* reduce power consumption */
1077 +/* rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x53);
1078 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x53);
1079 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x53);
1080 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x64);
1081 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0x4F);
1082 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x02);
1083 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1084 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x4F);
1085 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x02);
1086 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
1087 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x64);
1088 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x4F);
1089 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x02);
1090 +*/
1091 + /* Initialize RF DC calibration register to default value */
1092 + rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
1093 + rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
1094 + rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
1095 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
1096 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
1097 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1098 + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
1099 + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
1100 + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
1101 + rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
1102 + rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
1103 + rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
1104 + rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
1105 + rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
1106 + rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
1107 + rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
1108 + rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
1109 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
1110 + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
1111 + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
1112 + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
1113 + rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
1114 + rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
1115 + rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
1116 + rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
1117 + rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
1118 + rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
1119 + rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
1120 + rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
1121 + rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
1122 + rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
1123 + rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
1124 + rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
1125 + rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
1126 + rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
1127 + rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
1128 + rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
1129 + rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
1130 + rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
1131 + rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
1132 + rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
1133 + rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
1134 + rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
1135 + rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
1136 + rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
1137 + rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
1138 + rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
1139 + rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
1140 + rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
1141 + rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
1142 + rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
1143 + rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
1144 + rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
1145 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
1146 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
1147 + rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
1148 + rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
1149 + rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
1150 + rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
1151 +
1152 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
1153 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
1154 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
1155 +
1156 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1157 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
1158 +}
1159 +
1160 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1161 {
1162 if (rt2800_is_305x_soc(rt2x00dev)) {
1163 @@ -7435,7 +8367,10 @@ static void rt2800_init_rfcsr(struct rt2
1164 rt2800_init_rfcsr_5350(rt2x00dev);
1165 break;
1166 case RT5390:
1167 - rt2800_init_rfcsr_5390(rt2x00dev);
1168 + if (rt2x00dev->chip.rf == RF7620)
1169 + rt2800_init_rfcsr_7620(rt2x00dev);
1170 + else
1171 + rt2800_init_rfcsr_5390(rt2x00dev);
1172 break;
1173 case RT5392:
1174 rt2800_init_rfcsr_5392(rt2x00dev);
1175 @@ -7866,6 +8801,7 @@ static int rt2800_init_eeprom(struct rt2
1176 case RF5390:
1177 case RF5392:
1178 case RF5592:
1179 + case RF7620:
1180 break;
1181 default:
1182 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
1183 @@ -8431,6 +9367,7 @@ static int rt2800_probe_hw_mode(struct r
1184 case RF5372:
1185 case RF5390:
1186 case RF5392:
1187 + case RF7620:
1188 spec->num_channels = 14;
1189 if (spec->clk_is_20mhz)
1190 spec->channels = rf_vals_xtal20mhz_3x;
1191 @@ -8570,6 +9507,7 @@ static int rt2800_probe_hw_mode(struct r
1192 case RF5372:
1193 case RF5390:
1194 case RF5392:
1195 + case RF7620:
1196 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
1197 break;
1198 }
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