package/uboot-lantiq/files/board/arcadyan/board.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Thomas Langer, Ralph Hempel
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <command.h>
  29 #include <netdev.h>
  30 #include <miiphy.h>
  31 #include <asm/addrspace.h>
  32 #include <asm/danube.h>
  33 #include <asm/reboot.h>
  34 #include <asm/io.h>
  35 #if defined(CONFIG_CMD_HTTPD)
  36 #include <httpd.h>
  37 #endif
  38 #if defined(CONFIG_PCI)
  39 #include <pci.h>
  40 #endif
  41 #if defined(CONFIG_AR8216_SWITCH)
  42 #include "athrs26_phy.h"
  43 #endif
  44
  45 extern ulong ifx_get_ddr_hz(void);
  46 extern ulong ifx_get_cpuclk(void);
  47
  48 /* IDs and registers of known external switches */
  49 void _machine_restart(void)
  50 {
  51         *DANUBE_RCU_RST_REQ |=1<<30;
  52 }
  53
  54 #ifdef CONFIG_SYS_RAMBOOT
  55 phys_size_t initdram(int board_type)
  56 {
  57         return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
  58 }
  59 #elif defined(CONFIG_USE_DDR_RAM)
  60 phys_size_t initdram(int board_type)
  61 {
  62         return (CONFIG_SYS_MAX_RAM);
  63 }
  64 #else
  65
  66 static ulong max_sdram_size(void)     /* per Chip Select */
  67 {
  68         /* The only supported SDRAM data width is 16bit.
  69          */
  70 #define CFG_DW  4
  71
  72         /* The only supported number of SDRAM banks is 4.
  73          */
  74 #define CFG_NB  4
  75
  76         ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
  77         int   cols   = cfgpb0 & 0xF;
  78         int   rows   = (cfgpb0 & 0xF0) >> 4;
  79         ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
  80
  81         return size;
  82 }
  83
  84 /*
  85  * Check memory range for valid RAM. A simple memory test determines
  86  * the actually available RAM size between addresses `base' and
  87  * `base + maxsize'.
  88  */
  89
  90 static long int dram_size(long int *base, long int maxsize)
  91 {
  92         volatile long int *addr;
  93         ulong cnt, val;
  94         ulong save[32];                 /* to make test non-destructive */
  95         unsigned char i = 0;
  96
  97         for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
  98                 addr = base + cnt;              /* pointer arith! */
  99
 100                 save[i++] = *addr;
 101                 *addr = ~cnt;
 102         }
 103
 104         /* write 0 to base address */
 105         addr = base;
 106         save[i] = *addr;
 107         *addr = 0;
 108
 109         /* check at base address */
 110         if ((val = *addr) != 0) {
 111                 *addr = save[i];
 112                 return (0);
 113         }
 114
 115         for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
 116                 addr = base + cnt;              /* pointer arith! */
 117
 118                 val = *addr;
 119                 *addr = save[--i];
 120
 121                 if (val != (~cnt)) {
 122                         return (cnt * sizeof (long));
 123                 }
 124         }
 125         return (maxsize);
 126 }
 127
 128 phys_size_t initdram(int board_type)
 129 {
 130         int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
 131         ulong size, max_size       = 0;
 132         ulong our_address;
 133
 134         /* load t9 into our_address */
 135         asm volatile ("move %0, $25" : "=r" (our_address) :);
 136
 137         /* Can't probe for RAM size unless we are running from Flash.
 138          * find out whether running from DRAM or Flash.
 139          */
 140         if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
 141         {
 142                 return max_sdram_size();
 143         }
 144
 145         for (cols = 0x8; cols <= 0xC; cols++)
 146         {
 147                 for (rows = 0xB; rows <= 0xD; rows++)
 148                 {
 149                         *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 150                                                   (rows << 4) | cols;
 151                         size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 152                                                   max_sdram_size());
 153
 154                         if (size > max_size)
 155                         {
 156                                 best_val = *DANUBE_SDRAM_MC_CFGPB0;
 157                                 max_size = size;
 158                         }
 159                 }
 160         }
 161
 162         *DANUBE_SDRAM_MC_CFGPB0 = best_val;
 163         return max_size;
 164 }
 165 #endif
 166
 167 static void gpio_default(void)
 168 {
 169 #ifdef CONFIG_SWITCH_PORT0
 170         *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
 171         *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
 172         *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
 173         *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
 174         *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
 175 #elif defined(CONFIG_SWITCH_PORT1)
 176         *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
 177         *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
 178         *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
 179         *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
 180         *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
 181 #endif
 182 #ifdef CONFIG_EBU_GPIO
 183         {
 184                 int i = 0;
 185                 printf ("bring up ebu gpio\n");
 186                 *DANUBE_EBU_BUSCON1 = 0x1e7ff;
 187                 *DANUBE_EBU_ADDSEL1 = 0x14000001;
 188
 189                 *((volatile u16*)0xb4000000) = 0x0;
 190                 for(i = 0; i < 1000; i++)
 191                         udelay(1000);
 192                 *((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
 193                 *DANUBE_EBU_BUSCON1 = 0x8001e7ff;
 194         }
 195 #endif
 196 #ifdef CONFIG_BUTTON_PORT0
 197         *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
 198         *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
 199         *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
 200         if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
 201         {
 202                 printf("button is pressed\n");
 203                 setenv("bootdelay", "0");
 204                 setenv("bootcmd", "httpd");
 205         }
 206 #elif defined(CONFIG_BUTTON_PORT1)
 207         *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
 208         *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
 209         *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
 210         if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
 211         {
 212                 printf("button is pressed\n");
 213                 setenv("bootdelay", "0");
 214                 setenv("bootcmd", "httpd");
 215         }
 216 #endif
 217 #ifdef CONFIG_ARV4525
 218         *DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
 219         *DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
 220         *DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
 221         *DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
 222         *DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
 223 #endif
 224 }
 225
 226 int checkboard (void)
 227 {
 228         unsigned long chipid = *DANUBE_MPS_CHIPID;
 229         int part_num;
 230
 231         puts ("Board: "CONFIG_ARCADYAN"\n");
 232         puts ("SoC: ");
 233
 234         part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
 235         switch (part_num)
 236         {
 237         case 0x129:
 238         case 0x12D:
 239         case 0x12b:
 240                 puts("Danube/Twinpass/Vinax-VE ");
 241                 break;
 242         default:
 243                 printf ("unknown, chip part number 0x%03X ", part_num);
 244                 break;
 245         }
 246         printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
 247
 248         printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
 249         printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
 250
 251
 252         return 0;
 253 }
 254
 255 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 256 int board_early_init_f(void)
 257 {
 258 #ifdef CONFIG_EBU_ADDSEL0
 259         (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
 260 #endif
 261 #ifdef CONFIG_EBU_ADDSEL1
 262         (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
 263 #endif
 264 #ifdef CONFIG_EBU_ADDSEL2
 265         (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
 266 #endif
 267 #ifdef CONFIG_EBU_ADDSEL3
 268         (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
 269 #endif
 270 #ifdef CONFIG_EBU_BUSCON0
 271         (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
 272 #endif
 273 #ifdef CONFIG_EBU_BUSCON1
 274         (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
 275 #endif
 276 #ifdef CONFIG_EBU_BUSCON2
 277         (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
 278 #endif
 279 #ifdef CONFIG_EBU_BUSCON3
 280         (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
 281 #endif
 282
 283         return 0;
 284 }
 285 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 286
 287 #ifdef CONFIG_RTL8306_SWITCH
 288 #define ID_RTL8306      0x5988
 289 static int external_switch_rtl8306(void)
 290 {
 291         unsigned short chipid;
 292         static char * const name = "lq_cpe_eth";
 293
 294         udelay(100000);
 295
 296         puts("\nsearching for rtl8306 switch ... ");
 297         if (miiphy_read(name, 4, 30, &chipid) == 0) {
 298                 if (chipid == ID_RTL8306) {
 299                         puts("found");
 300                         /* set led mode */
 301                         miiphy_write(name, 0, 19, 0xffff);
 302                         /* magic */
 303                         miiphy_write(name, 4, 22, 0x877f);
 304                         puts("\n");
 305                         return 0;
 306                 }
 307                 puts("failed\n");
 308         }
 309         puts("\nno known switch found ... \n");
 310
 311         return 0;
 312 }
 313 #endif
 314
 315 #ifdef CONFIG_RTL8306G_SWITCH
 316 #define ID_RTL8306      0x5988
 317
 318 static int external_switch_rtl8306G(void)
 319 {
 320         unsigned short chipid,val;
 321         int i;
 322         static char * const name = "lq_cpe_eth";
 323         unsigned int chipid2, chipver, chiptype;
 324         char str[128];
 325         int cpu_mask = 1 << 5;
 326         udelay(100000);
 327
 328         puts("\nsearching for rtl8306 switch ... ");
 329         if (miiphy_read(name, 4, 30, &chipid) == 0) {
 330                 if (chipid == ID_RTL8306) {
 331                         puts("found\nReset Hard\n");
 332 #ifdef CONFIG_ARV752DPW
 333                         //gpio 19
 334                         //reset reset ping to high
 335                         *DANUBE_GPIO_P1_DIR |= 8;
 336                         *DANUBE_GPIO_P1_OUT |= 8;
 337                         udelay(500*1000);
 338                         *DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
 339                         udelay(500*1000);
 340                         *DANUBE_GPIO_P1_OUT |= 8;
 341                         udelay(500*1000);
 342                         puts("Done\n");
 343 #endif
 344                         /* set led mode */
 345
 346                         miiphy_write(name, 0, 0, 0x3100);
 347                         miiphy_write(name, 0, 18, 0x7fff);
 348                         miiphy_write(name, 0, 19, 0xffff);
 349                         miiphy_write(name, 0, 22, 0x877f);
 350                         miiphy_write(name, 0, 24, 0x0ed1);
 351
 352                         miiphy_write(name, 1, 0, 0x3100);
 353                         miiphy_write(name, 1, 22, 0x877f);
 354                         miiphy_write(name, 1, 24, 0x1ed2);
 355
 356                         miiphy_write(name, 2, 0, 0x3100);
 357                         miiphy_write(name, 2, 22, 0x877f);
 358                         miiphy_write(name, 2, 23, 0x0020);
 359                         miiphy_write(name, 2, 24, 0x2ed4);
 360
 361                         miiphy_write(name, 3, 0, 0x3100);
 362                         miiphy_write(name, 3, 22, 0x877f);
 363                         miiphy_write(name, 3, 24, 0x3ed8);
 364
 365                         miiphy_write(name, 4, 0, 0x3100);
 366                         miiphy_write(name, 4, 22, 0x877f);
 367                         miiphy_write(name, 4, 24, 0x4edf);
 368
 369                         miiphy_write(name, 5, 0, 0x3100);
 370                         miiphy_write(name, 6, 0, 0x2100);
 371
 372                         //important. enable phy 5 link status, for rmii
 373                         miiphy_write(name, 6, 22, 0x873f);
 374
 375                         miiphy_write(name, 6, 24, 0x8eff);
 376                         //disable ports
 377                         for (i=0;i<5;i++) {
 378                                 miiphy_read(name, 0, 24, &val);
 379                                 val&=~(1<<10);
 380                                 val&=~(1<<11);
 381                                 miiphy_write(name, 0, 24, val);
 382                         }
 383
 384                         puts("Reset Soft\n");
 385                         miiphy_write(name,0 ,0 ,1<<15);
 386                         for (i=0;i<1000;i++)
 387                         {
 388                                 miiphy_read(name,0 ,0 ,&val);
 389                                 if (!(val&1<<15))
 390                                         break;
 391                                 udelay(1000);
 392                         }
 393                         if (i==1000)
 394                                 puts("Failed\n");
 395                         else
 396                                 puts("Success\n");
 397                         //enable ports egain
 398                         for (i=0;i<5;i++) // enable ports
 399                         {
 400                                 miiphy_read(name, 0, 24, &val);
 401                                 val|=(1<<10);
 402                                 val|=(1<<11);
 403                                 miiphy_write(name, 0, 24, val);
 404                         }
 405                         puts("\n");
 406                         return 0;
 407                 }
 408                 puts("failed\n");
 409         }
 410         puts("\nno known switch found ... \n");
 411
 412         return 0;
 413 }
 414 #endif
 415
 416 #ifdef CONFIG_AR8216_SWITCH
 417 static int external_switch_ar8216(void)
 418 {
 419         puts("initializing ar8216 switch... ");
 420         if (athrs26_phy_setup(0)==0) {
 421            printf("initialized\n");
 422            return 0;
 423         }
 424         puts("failed ... \n");
 425         return 0;
 426 }
 427 #endif
 428
 429 int board_eth_init(bd_t *bis)
 430 {
 431         gpio_default();
 432
 433 #if defined(CONFIG_IFX_ETOP)
 434         uchar enetaddr[6];
 435         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 436                eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
 437
 438         *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
 439         *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
 440
 441         if (lq_eth_initialize(bis))
 442                 return -1;
 443
 444         *DANUBE_RCU_RST_REQ |=1;
 445         udelay(200000);
 446         *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
 447         udelay(1000);
 448
 449 #ifdef CONFIG_RTL8306G_SWITCH
 450         if (external_switch_rtl8306G()<0)
 451                 return -1;
 452 #endif
 453 #ifdef CONFIG_RTL8306_SWITCH
 454         if (external_switch_rtl8306()<0)
 455                 return -1;
 456 #endif
 457 #ifdef CONFIG_AR8216_SWITCH
 458         if (external_switch_ar8216()<0)
 459                 return -1;
 460 #endif
 461 #endif
 462         return 0;
 463 }
 464
 465 #if defined(CONFIG_CMD_HTTPD)
 466 int do_http_upgrade(const unsigned char *data, const ulong size)
 467 {
 468         char buf[128];
 469
 470         if(getenv ("ram_addr") == NULL)
 471                 return -1;
 472         if(getenv ("kernel_addr") == NULL)
 473                 return -1;
 474         /* check the image */
 475         if(run_command("imi ${ram_addr}", 0) < 0) {
 476                 return -1;
 477         }
 478         /* write the image to the flash */
 479         puts("http ugrade ...\n");
 480         sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
 481         return run_command(buf, 0);
 482 }
 483
 484 int do_http_progress(const int state)
 485 {
 486         /* toggle LED's here */
 487         switch(state) {
 488                 case HTTP_PROGRESS_START:
 489                 puts("http start\n");
 490                 break;
 491                 case HTTP_PROGRESS_TIMEOUT:
 492                 puts(".");
 493                 break;
 494                 case HTTP_PROGRESS_UPLOAD_READY:
 495                 puts("http upload ready\n");
 496                 break;
 497                 case HTTP_PROGRESS_UGRADE_READY:
 498                 puts("http ugrade ready\n");
 499                 break;
 500                 case HTTP_PROGRESS_UGRADE_FAILED:
 501                 puts("http ugrade failed\n");
 502                 break;
 503         }
 504         return 0;
 505 }
 506
 507 unsigned long do_http_tmp_address(void)
 508 {
 509         char *s = getenv ("ram_addr");
 510         if (s) {
 511                 ulong tmp = simple_strtoul (s, NULL, 16);
 512                 return tmp;
 513         }
 514         return 0 /*0x80a00000*/;
 515 }
 516
 517 #endif