target/linux/adm5120-2.6/image/lzma-loader/src/decompress.c

   1 /*
   2  * LZMA compressed kernel decompressor for bcm947xx boards
   3  *
   4  * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19  *
  20  *
  21  * Please note, this was code based on the bunzip2 decompressor code
  22  * by Manuel Novoa III  (mjn3@codepoet.org), although the only thing left
  23  * is an idea and part of original vendor code
  24  *
  25  *
  26  * 12-Mar-2005  Mineharu Takahara <mtakahar@yahoo.com>
  27  *   pass actual output size to decoder (stream mode
  28  *   compressed input is not a requirement anymore)
  29  *
  30  * 24-Apr-2005 Oleg I. Vdovikin
  31  *   reordered functions using lds script, removed forward decl
  32  *
  33  * 24-Mar-2007 Gabor Juhos
  34  *   pass original values of the a0,a1,a2,a3 registers to the kernel
  35  *
  36  */
  37
  38 #include "LzmaDecode.h"
  39
  40 #define BCM4710_FLASH           0x1fc00000      /* Flash */
  41
  42 #define KSEG0                   0x80000000
  43 #define KSEG1                   0xa0000000
  44
  45 #define KSEG1ADDR(a)            ((((unsigned)(a)) & 0x1fffffffU) | KSEG1)
  46
  47 #define Index_Invalidate_I      0x00
  48 #define Index_Writeback_Inv_D   0x01
  49
  50 #define cache_unroll(base,op)   \
  51         __asm__ __volatile__(           \
  52                 ".set noreorder;\n"             \
  53                 ".set mips3;\n"                 \
  54                 "cache %1, (%0);\n"             \
  55                 ".set mips0;\n"                 \
  56                 ".set reorder\n"                \
  57                 :                                               \
  58                 : "r" (base),                   \
  59                   "i" (op));
  60
  61 static __inline__ void blast_icache(unsigned long size, unsigned long lsize)
  62 {
  63         unsigned long start = KSEG0;
  64         unsigned long end = (start + size);
  65
  66         while(start < end) {
  67                 cache_unroll(start,Index_Invalidate_I);
  68                 start += lsize;
  69         }
  70 }
  71
  72 static __inline__ void blast_dcache(unsigned long size, unsigned long lsize)
  73 {
  74         unsigned long start = KSEG0;
  75         unsigned long end = (start + size);
  76
  77         while(start < end) {
  78                 cache_unroll(start,Index_Writeback_Inv_D);
  79                 start += lsize;
  80         }
  81 }
  82
  83 #define TRX_MAGIC       0x30524448      /* "HDR0" */
  84
  85 struct trx_header {
  86         unsigned int magic;             /* "HDR0" */
  87         unsigned int len;               /* Length of file including header */
  88         unsigned int crc32;             /* 32-bit CRC from flag_version to end of file */
  89         unsigned int flag_version;      /* 0:15 flags, 16:31 version */
  90         unsigned int offsets[3];        /* Offsets of partitions from start of header */
  91 };
  92
  93 /* beyound the image end, size not known in advance */
  94 extern unsigned char workspace[];
  95
  96 unsigned int offset;
  97 unsigned char *data;
  98
  99 typedef void (*kernel_entry)(unsigned long reg_a0, unsigned long reg_a1,
 100         unsigned long reg_a2, unsigned long reg_a3);
 101
 102 /* flash access should be aligned, so wrapper is used */
 103 /* read byte from the flash, all accesses are 32-bit aligned */
 104 static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize)
 105 {
 106         static unsigned int val;
 107
 108         if (((unsigned int)offset % 4) == 0) {
 109                 val = *(unsigned int *)data;
 110                 data += 4;
 111         }
 112
 113         *bufferSize = 1;
 114         *buffer = ((unsigned char *)&val) + (offset++ & 3);
 115
 116         return LZMA_RESULT_OK;
 117 }
 118
 119 static __inline__ unsigned char get_byte(void)
 120 {
 121         unsigned char *buffer;
 122         UInt32 fake;
 123
 124         return read_byte(0, &buffer, &fake), *buffer;
 125 }
 126
 127 int uart_write_str(char * str);
 128
 129 /* should be the first function */
 130 void decompress_entry(unsigned long reg_a0, unsigned long reg_a1,
 131         unsigned long reg_a2, unsigned long reg_a3,
 132         unsigned long icache_size, unsigned long icache_lsize,
 133         unsigned long dcache_size, unsigned long dcache_lsize)
 134 {
 135         unsigned int i;  /* temp value */
 136         unsigned int lc; /* literal context bits */
 137         unsigned int lp; /* literal pos state bits */
 138         unsigned int pb; /* pos state bits */
 139         unsigned int osize; /* uncompressed size */
 140
 141         ILzmaInCallback callback;
 142         callback.Read = read_byte;
 143
 144     uart_write_str("decompress kernel ... ");
 145
 146         /* look for trx header, 32-bit data access */
 147         for (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH));
 148                 ((struct trx_header *)data)->magic != TRX_MAGIC; data += 65536);
 149
 150         /* compressed kernel is in the partition 0 or 1 */
 151         if (((struct trx_header *)data)->offsets[1] > 65536)
 152                 data += ((struct trx_header *)data)->offsets[0];
 153         else
 154                 data += ((struct trx_header *)data)->offsets[1];
 155
 156         offset = 0;
 157
 158         /* lzma args */
 159         i = get_byte();
 160         lc = i % 9, i = i / 9;
 161         lp = i % 5, pb = i / 5;
 162
 163         /* skip rest of the LZMA coder property */
 164         for (i = 0; i < 4; i++)
 165                 get_byte();
 166
 167         /* read the lower half of uncompressed size in the header */
 168         osize = ((unsigned int)get_byte()) +
 169                 ((unsigned int)get_byte() << 8) +
 170                 ((unsigned int)get_byte() << 16) +
 171                 ((unsigned int)get_byte() << 24);
 172
 173         /* skip rest of the header (upper half of uncompressed size) */
 174         for (i = 0; i < 4; i++)
 175                 get_byte();
 176
 177         /* decompress kernel */
 178         if (LzmaDecode(workspace, ~0, lc, lp, pb, &callback,
 179                 (unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK)
 180         {
 181                 blast_dcache(dcache_size, dcache_lsize);
 182                 blast_icache(icache_size, icache_lsize);
 183
 184                 /* Jump to load address */
 185         uart_write_str("ok\r\n");
 186                 ((kernel_entry) LOADADDR)(reg_a0, reg_a1, reg_a2, reg_a3);
 187         }
 188     uart_write_str("failed\r\n");
 189     while (1 );
 190 }
 191
 192 /*  *********************************************************************
 193     *
 194     *  ADM5120 UART driver                      File: dev_adm_uart.c
 195     *
 196     *  This is a console device driver for an ADM5120 UART
 197     *
 198     *********************************************************************
 199     *
 200     *  Copyright 2006
 201     *  Compex Systems. All rights reserved.
 202     *
 203     ********************************************************************* */
 204
 205 #define READCSR(r)      *(volatile UInt32 *)(0xB2600000+(r))
 206 #define WRITECSR(r,v)   *(volatile UInt32 *)(0xB2600000+(r)) = v
 207
 208 #define UART_DR_REG         0x00
 209 #define UART_FR_REG         0x18
 210 #define UART_TX_FIFO_FULL   0x20
 211
 212 int uart_write(int val)
 213 {
 214         WRITECSR(UART_DR_REG, val);
 215     while ( (READCSR(UART_FR_REG) & UART_TX_FIFO_FULL) );
 216     return 0;
 217 }
 218
 219 int uart_write_str(char * str)
 220 {
 221     while ( *str != 0 ) {
 222         uart_write ( *str++ );
 223     }
 224     return 0;
 225 }
 226
 227 int uart_write_hex(int val)
 228 {
 229     int i;
 230     int tmp;
 231
 232     uart_write_str("0x");
 233     for ( i=0 ; i<8 ; i++ ) {
 234         tmp = (val >> ((7-i) * 4 )) & 0xf;
 235         tmp = tmp < 10 ? (tmp + '0') : (tmp + 'A' - 10);
 236         uart_write(tmp);
 237     }
 238     uart_write_str("\r\n");
 239     return 0;
 240 }
 241