target/linux/adm5120/files/arch/mips/adm5120/platform.c

   1 /*
   2  *  $Id$
   3  *
   4  *  Generic ADM5120 platform devices
   5  *
   6  *  Copyright (C) 2007-2008 OpenWrt.org
   7  *  Copyright (C) 2007-2008 Gabor Juhos <juhosg at openwrt.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/gpio.h>
  24
  25 #include <adm5120_defs.h>
  26 #include <adm5120_info.h>
  27 #include <adm5120_irq.h>
  28 #include <adm5120_switch.h>
  29 #include <adm5120_nand.h>
  30 #include <adm5120_platform.h>
  31
  32 #if 1
  33 /*
  34  * TODO:remove global adm5120_eth* variables when the switch driver will be
  35  *      converted into a real platform driver
  36  */
  37 unsigned int adm5120_eth_num_ports = 6;
  38 EXPORT_SYMBOL_GPL(adm5120_eth_num_ports);
  39
  40 unsigned char adm5120_eth_macs[6][6] = {
  41         {'\00', 'A', 'D', 'M', '\x51', '\x20' },
  42         {'\00', 'A', 'D', 'M', '\x51', '\x21' },
  43         {'\00', 'A', 'D', 'M', '\x51', '\x22' },
  44         {'\00', 'A', 'D', 'M', '\x51', '\x23' },
  45         {'\00', 'A', 'D', 'M', '\x51', '\x24' },
  46         {'\00', 'A', 'D', 'M', '\x51', '\x25' }
  47 };
  48 EXPORT_SYMBOL_GPL(adm5120_eth_macs);
  49
  50 unsigned char adm5120_eth_vlans[6] = {
  51         0x41, 0x42, 0x44, 0x48, 0x50, 0x60
  52 };
  53 EXPORT_SYMBOL_GPL(adm5120_eth_vlans);
  54 #endif
  55
  56 /* Built-in ethernet switch */
  57 struct resource adm5120_switch_resources[] = {
  58         [0] = {
  59                 .start  = ADM5120_SWITCH_BASE,
  60                 .end    = ADM5120_SWITCH_BASE+ADM5120_SWITCH_SIZE-1,
  61                 .flags  = IORESOURCE_MEM,
  62         },
  63         [1] = {
  64                 .start  = ADM5120_IRQ_SWITCH,
  65                 .end    = ADM5120_IRQ_SWITCH,
  66                 .flags  = IORESOURCE_IRQ,
  67         },
  68 };
  69
  70 struct adm5120_switch_platform_data adm5120_switch_data;
  71 struct platform_device adm5120_switch_device = {
  72         .name   = "adm5120-switch",
  73         .id     = -1,
  74         .num_resources  = ARRAY_SIZE(adm5120_switch_resources),
  75         .resource       = adm5120_switch_resources,
  76         .dev.platform_data = &adm5120_switch_data,
  77 };
  78
  79 /* USB Host Controller */
  80 struct resource adm5120_hcd_resources[] = {
  81         [0] = {
  82                 .start  = ADM5120_USBC_BASE,
  83                 .end    = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1,
  84                 .flags  = IORESOURCE_MEM,
  85         },
  86         [1] = {
  87                 .start  = ADM5120_IRQ_USBC,
  88                 .end    = ADM5120_IRQ_USBC,
  89                 .flags  = IORESOURCE_IRQ,
  90         },
  91 };
  92
  93 static u64 adm5120_hcd_dma_mask = DMA_BIT_MASK(24);
  94 struct platform_device adm5120_hcd_device = {
  95         .name           = "adm5120-hcd",
  96         .id             = -1,
  97         .num_resources  = ARRAY_SIZE(adm5120_hcd_resources),
  98         .resource       = adm5120_hcd_resources,
  99         .dev = {
 100                 .dma_mask       = &adm5120_hcd_dma_mask,
 101                 .coherent_dma_mask = DMA_BIT_MASK(24),
 102         }
 103 };
 104
 105 /* NOR flash 0 */
 106 struct adm5120_flash_platform_data adm5120_flash0_data;
 107 struct platform_device adm5120_flash0_device =  {
 108         .name   = "adm5120-flash",
 109         .id     = 0,
 110         .dev.platform_data = &adm5120_flash0_data,
 111 };
 112
 113 /* NOR flash 1 */
 114 struct adm5120_flash_platform_data adm5120_flash1_data;
 115 struct platform_device adm5120_flash1_device =  {
 116         .name   = "adm5120-flash",
 117         .id     = 1,
 118         .dev.platform_data = &adm5120_flash1_data,
 119 };
 120
 121 /* NAND flash */
 122 struct resource adm5120_nand_resource[] = {
 123         [0] = {
 124                 .start  = ADM5120_NAND_BASE,
 125                 .end    = ADM5120_NAND_BASE + ADM5120_NAND_SIZE-1,
 126                 .flags  = IORESOURCE_MEM,
 127         },
 128 };
 129
 130 struct platform_nand_data adm5120_nand_data = {
 131         .ctrl.dev_ready = adm5120_nand_ready,
 132         .ctrl.cmd_ctrl  = adm5120_nand_cmd_ctrl,
 133 };
 134
 135 struct platform_device adm5120_nand_device = {
 136         .name           = "gen_nand",
 137         .id             = -1,
 138         .num_resources  = ARRAY_SIZE(adm5120_nand_resource),
 139         .resource       = adm5120_nand_resource,
 140         .dev.platform_data = &adm5120_nand_data,
 141 };
 142
 143 /* built-in UARTs */
 144 struct amba_pl010_data adm5120_uart0_data = {
 145         .set_mctrl = adm5120_uart_set_mctrl
 146 };
 147
 148 struct amba_device adm5120_uart0_device = {
 149         .dev            = {
 150                 .bus_id = "APB:UART0",
 151                 .platform_data = &adm5120_uart0_data,
 152         },
 153         .res            = {
 154                 .start  = ADM5120_UART0_BASE,
 155                 .end    = ADM5120_UART0_BASE + ADM5120_UART_SIZE - 1,
 156                 .flags  = IORESOURCE_MEM,
 157         },
 158         .irq            = { ADM5120_IRQ_UART0, -1 },
 159         .periphid       = 0x0041010,
 160 };
 161
 162 struct amba_pl010_data adm5120_uart1_data = {
 163         .set_mctrl = adm5120_uart_set_mctrl
 164 };
 165
 166 struct amba_device adm5120_uart1_device = {
 167         .dev            = {
 168                 .bus_id = "APB:UART1",
 169                 .platform_data = &adm5120_uart1_data,
 170         },
 171         .res            = {
 172                 .start  = ADM5120_UART1_BASE,
 173                 .end    = ADM5120_UART1_BASE + ADM5120_UART_SIZE - 1,
 174                 .flags  = IORESOURCE_MEM,
 175         },
 176         .irq            = { ADM5120_IRQ_UART1, -1 },
 177         .periphid       = 0x0041010,
 178 };
 179
 180 #define ADM5120_BUTTON_THRESHOLD        5
 181 #define ADM5120_BUTTON_INTERVAL         20
 182
 183 struct gpio_button adm5120_buttons[ADM5120_NUM_BUTTONS] = {
 184         {
 185                 .type           = EV_KEY,
 186                 .code           = BTN_0,
 187                 .threshold      = ADM5120_BUTTON_THRESHOLD,
 188         }, {
 189                 .type           = EV_KEY,
 190                 .code           = BTN_1,
 191                 .threshold      = ADM5120_BUTTON_THRESHOLD,
 192         }, {
 193                 .type           = EV_KEY,
 194                 .code           = BTN_2,
 195                 .threshold      = ADM5120_BUTTON_THRESHOLD,
 196         }, {
 197                 .type           = EV_KEY,
 198                 .code           = BTN_3,
 199                 .threshold      = ADM5120_BUTTON_THRESHOLD,
 200         }, {
 201                 .type           = EV_KEY,
 202                 .code           = BTN_4,
 203                 .threshold      = ADM5120_BUTTON_THRESHOLD,
 204         }
 205 };
 206
 207 struct gpio_buttons_platform_data adm5120_buttons_data = {
 208         .poll_interval  = ADM5120_BUTTON_INTERVAL,
 209         .nbuttons       = ARRAY_SIZE(adm5120_buttons),
 210         .buttons        = adm5120_buttons,
 211 };
 212
 213 struct platform_device adm5120_buttons_device = {
 214         .name           = "gpio-buttons",
 215         .id             = 0,
 216         .dev.platform_data = &adm5120_buttons_data,
 217 };
 218
 219 void adm5120_uart_set_mctrl(struct amba_device *dev, void __iomem *base,
 220                 unsigned int mctrl)
 221 {
 222 }
 223
 224 int adm5120_nand_ready(struct mtd_info *mtd)
 225 {
 226         return ((adm5120_nand_get_status() & ADM5120_NAND_STATUS_READY) != 0);
 227 }
 228
 229 void adm5120_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 230 {
 231         if (ctrl & NAND_CTRL_CHANGE) {
 232                 adm5120_nand_set_cle(ctrl & NAND_CLE);
 233                 adm5120_nand_set_ale(ctrl & NAND_ALE);
 234                 adm5120_nand_set_cen(ctrl & NAND_NCE);
 235         }
 236
 237         if (cmd != NAND_CMD_NONE)
 238                 NAND_WRITE_REG(NAND_REG_DATA, cmd);
 239 }
 240