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checkin a new, experimental USB driver
[openwrt/openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ahcd fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
17 *
18 * This file is licenced under the GPL.
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "v0.01"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #define ADMHC_VERBOSE_DEBUG /* not always helpful */
55 #undef LATE_ED_SCHEDULE
56
57 /* For initializing controller (mask in an HCFS mode too) */
58 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59
60 #define ADMHC_INTR_INIT \
61 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
62 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
63
64 /*-------------------------------------------------------------------------*/
65
66 static const char hcd_name [] = "admhc-hcd";
67
68 #define STATECHANGE_DELAY msecs_to_jiffies(300)
69
70 #include "adm5120.h"
71
72 static void admhc_dump(struct admhcd *ahcd, int verbose);
73 static int admhc_init(struct admhcd *ahcd);
74 static void admhc_stop(struct usb_hcd *hcd);
75
76 #include "adm5120-hub.c"
77 #include "adm5120-dbg.c"
78 #include "adm5120-mem.c"
79 #include "adm5120-q.c"
80
81 /*-------------------------------------------------------------------------*/
82
83 /*
84 * queue up an urb for anything except the root hub
85 */
86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
87 struct urb *urb, gfp_t mem_flags)
88 {
89 struct admhcd *ahcd = hcd_to_admhcd(hcd);
90 struct ed *ed;
91 struct urb_priv *urb_priv;
92 unsigned int pipe = urb->pipe;
93 int i, td_cnt = 0;
94 unsigned long flags;
95 int retval = 0;
96
97 #ifdef ADMHC_VERBOSE_DEBUG
98 urb_print(urb, "ENQ", usb_pipein(pipe));
99 #endif
100
101 /* every endpoint has an ed, locate and maybe (re)initialize it */
102 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
103 if (!ed)
104 return -ENOMEM;
105
106 /* for the private part of the URB we need the number of TDs */
107 switch (ed->type) {
108 case PIPE_CONTROL:
109 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
110 /* td_submit_urb() doesn't yet handle these */
111 return -EMSGSIZE;
112
113 /* 1 TD for setup, 1 for ACK, plus ... */
114 td_cnt = 2;
115 /* FALLTHROUGH */
116 case PIPE_BULK:
117 /* one TD for every 4096 Bytes (can be upto 8K) */
118 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
119 /* ... and for any remaining bytes ... */
120 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
121 td_cnt++;
122 /* ... and maybe a zero length packet to wrap it up */
123 if (td_cnt == 0)
124 td_cnt++;
125 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
126 && (urb->transfer_buffer_length
127 % usb_maxpacket(urb->dev, pipe,
128 usb_pipeout (pipe))) == 0)
129 td_cnt++;
130 break;
131 case PIPE_INTERRUPT:
132 /*
133 * for Interrupt IN/OUT transactions, each ED contains
134 * only 1 TD.
135 * TODO: check transfer_buffer_length?
136 */
137 td_cnt = 1;
138 break;
139 case PIPE_ISOCHRONOUS:
140 /* number of packets from URB */
141 td_cnt = urb->number_of_packets;
142 break;
143 default:
144 /* paranoia */
145 admhc_err(ahcd, "bad EP type %d", ed->type);
146 return -EINVAL;
147 }
148
149 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
150 if (!urb_priv)
151 return -ENOMEM;
152
153 urb_priv->ed = ed;
154
155 spin_lock_irqsave(&ahcd->lock, flags);
156 /* don't submit to a dead HC */
157 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
158 retval = -ENODEV;
159 goto fail;
160 }
161 if (!HC_IS_RUNNING(hcd->state)) {
162 retval = -ENODEV;
163 goto fail;
164 }
165
166 /* in case of unlink-during-submit */
167 spin_lock(&urb->lock);
168 if (urb->status != -EINPROGRESS) {
169 spin_unlock(&urb->lock);
170 urb->hcpriv = urb_priv;
171 finish_urb(ahcd, urb);
172 retval = 0;
173 goto fail;
174 }
175
176 /* schedule the ed if needed */
177 if (ed->state == ED_IDLE) {
178 #ifndef LATE_ED_SCHEDULE
179 retval = ed_schedule(ahcd, ed);
180 if (retval < 0)
181 goto fail0;
182 #endif
183 if (ed->type == PIPE_ISOCHRONOUS) {
184 u16 frame = admhc_frame_no(ahcd);
185
186 /* delay a few frames before the first TD */
187 frame += max_t (u16, 8, ed->interval);
188 frame &= ~(ed->interval - 1);
189 frame |= ed->branch;
190 urb->start_frame = frame;
191
192 /* yes, only URB_ISO_ASAP is supported, and
193 * urb->start_frame is never used as input.
194 */
195 }
196 } else if (ed->type == PIPE_ISOCHRONOUS)
197 urb->start_frame = ed->last_iso + ed->interval;
198
199 /* fill the TDs and link them to the ed; and
200 * enable that part of the schedule, if needed
201 * and update count of queued periodic urbs
202 */
203 urb->hcpriv = urb_priv;
204 td_submit_urb(ahcd, urb);
205
206 #ifdef LATE_ED_SCHEDULE
207 if (ed->state == ED_IDLE)
208 retval = ed_schedule(ahcd, ed);
209 #endif
210
211 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
212
213 fail0:
214 spin_unlock(&urb->lock);
215 fail:
216 if (retval)
217 urb_priv_free(ahcd, urb_priv);
218
219 spin_unlock_irqrestore(&ahcd->lock, flags);
220 return retval;
221 }
222
223 /*
224 * decouple the URB from the HC queues (TDs, urb_priv); it's
225 * already marked using urb->status. reporting is always done
226 * asynchronously, and we might be dealing with an urb that's
227 * partially transferred, or an ED with other urbs being unlinked.
228 */
229 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
230 {
231 struct admhcd *ahcd = hcd_to_admhcd(hcd);
232 unsigned long flags;
233
234 #ifdef ADMHC_VERBOSE_DEBUG
235 urb_print(urb, "DEQ", 1);
236 #endif
237
238 spin_lock_irqsave(&ahcd->lock, flags);
239 if (HC_IS_RUNNING(hcd->state)) {
240 struct urb_priv *urb_priv;
241
242 /* Unless an IRQ completed the unlink while it was being
243 * handed to us, flag it for unlink and giveback, and force
244 * some upcoming INTR_SF to call finish_unlinks()
245 */
246 urb_priv = urb->hcpriv;
247 if (urb_priv) {
248 if (urb_priv->ed->state == ED_OPER)
249 start_ed_unlink(ahcd, urb_priv->ed);
250 }
251 } else {
252 /*
253 * with HC dead, we won't respect hc queue pointers
254 * any more ... just clean up every urb's memory.
255 */
256 if (urb->hcpriv)
257 finish_urb(ahcd, urb);
258 }
259 spin_unlock_irqrestore(&ahcd->lock, flags);
260
261 return 0;
262 }
263
264 /*-------------------------------------------------------------------------*/
265
266 /* frees config/altsetting state for endpoints,
267 * including ED memory, dummy TD, and bulk/intr data toggle
268 */
269
270 static void
271 admhc_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
272 {
273 struct admhcd *ahcd = hcd_to_admhcd(hcd);
274 unsigned long flags;
275 struct ed *ed = ep->hcpriv;
276 unsigned limit = 1000;
277
278 /* ASSERT: any requests/urbs are being unlinked */
279 /* ASSERT: nobody can be submitting urbs for this any more */
280
281 if (!ed)
282 return;
283
284 #ifdef ADMHC_VERBOSE_DEBUG
285 spin_lock_irqsave(&ahcd->lock, flags);
286 admhc_dump_ed(ahcd, "ep_disable", ed, 1);
287 spin_unlock_irqrestore(&ahcd->lock, flags);
288 #endif
289
290 rescan:
291 spin_lock_irqsave(&ahcd->lock, flags);
292
293 if (!HC_IS_RUNNING(hcd->state)) {
294 sanitize:
295 ed->state = ED_IDLE;
296 finish_unlinks(ahcd, 0);
297 }
298
299 switch (ed->state) {
300 case ED_UNLINK: /* wait for hw to finish? */
301 /* major IRQ delivery trouble loses INTR_SOFI too... */
302 if (limit-- == 0) {
303 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
304 goto sanitize;
305 }
306 spin_unlock_irqrestore(&ahcd->lock, flags);
307 schedule_timeout_uninterruptible(1);
308 goto rescan;
309 case ED_IDLE: /* fully unlinked */
310 if (list_empty(&ed->td_list)) {
311 td_free (ahcd, ed->dummy);
312 ed_free (ahcd, ed);
313 break;
314 }
315 /* else FALL THROUGH */
316 default:
317 /* caller was supposed to have unlinked any requests;
318 * that's not our job. can't recover; must leak ed.
319 */
320 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
321 ed, ep->desc.bEndpointAddress, ed->state,
322 list_empty(&ed->td_list) ? "" : " (has tds)");
323 td_free(ahcd, ed->dummy);
324 break;
325 }
326 ep->hcpriv = NULL;
327 spin_unlock_irqrestore(&ahcd->lock, flags);
328 return;
329 }
330
331 static int admhc_get_frame(struct usb_hcd *hcd)
332 {
333 struct admhcd *ahcd = hcd_to_admhcd(hcd);
334
335 return admhc_frame_no(ahcd);
336 }
337
338 static void admhc_usb_reset(struct admhcd *ahcd)
339 {
340 #if 0
341 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
342 ahcd->hc_control &= OHCI_CTRL_RWC;
343 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
344 #else
345 /* FIXME */
346 ahcd->host_control = ADMHC_BUSS_RESET;
347 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
348 #endif
349 }
350
351 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
352 * other cases where the next software may expect clean state from the
353 * "firmware". this is bus-neutral, unlike shutdown() methods.
354 */
355 static void
356 admhc_shutdown(struct usb_hcd *hcd)
357 {
358 struct admhcd *ahcd;
359
360 ahcd = hcd_to_admhcd(hcd);
361 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
362 admhc_dma_disable(ahcd);
363 admhc_usb_reset(ahcd);
364 /* flush the writes */
365 admhc_writel_flush(ahcd);
366 }
367
368 /*-------------------------------------------------------------------------*
369 * HC functions
370 *-------------------------------------------------------------------------*/
371
372 static void admhc_eds_cleanup(struct admhcd *ahcd)
373 {
374 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
375 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
376 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
377 }
378
379 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
380 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
381 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
382 }
383
384 if (ahcd->ed_tails[PIPE_CONTROL]) {
385 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
386 ahcd->ed_tails[PIPE_CONTROL] = NULL;
387 }
388
389 if (ahcd->ed_tails[PIPE_BULK]) {
390 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
391 ahcd->ed_tails[PIPE_BULK] = NULL;
392 }
393
394 ahcd->ed_head = NULL;
395 }
396
397 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
398
399 static int admhc_eds_init(struct admhcd *ahcd)
400 {
401 struct ed *ed;
402
403 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
404 if (!ed)
405 goto err;
406
407 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
408
409 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
410 if (!ed)
411 goto err;
412
413 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
414 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
415 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
416 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
417
418 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
419 if (!ed)
420 goto err;
421
422 ahcd->ed_tails[PIPE_CONTROL] = ed;
423 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
424 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
425 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
426
427 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
428 if (!ed)
429 goto err;
430
431 ahcd->ed_tails[PIPE_BULK] = ed;
432 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
433 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
434 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
435
436 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
437
438 #ifdef ADMHC_VERBOSE_DEBUG
439 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
440 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
441 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
442 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
443 #endif
444
445 return 0;
446
447 err:
448 admhc_eds_cleanup(ahcd);
449 return -ENOMEM;
450 }
451
452 /* init memory, and kick BIOS/SMM off */
453
454 static int admhc_init(struct admhcd *ahcd)
455 {
456 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
457 int ret;
458
459 admhc_disable(ahcd);
460 ahcd->regs = hcd->regs;
461
462 /* Disable HC interrupts */
463 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
464
465 /* Read the number of ports unless overridden */
466 if (ahcd->num_ports == 0)
467 ahcd->num_ports = admhc_get_rhdesc(ahcd) & ADMHC_RH_NUMP;
468
469 ret = admhc_mem_init(ahcd);
470 if (ret)
471 goto err;
472
473 /* init dummy endpoints */
474 ret = admhc_eds_init(ahcd);
475 if (ret)
476 goto err;
477
478 create_debug_files(ahcd);
479
480 return 0;
481
482 err:
483 admhc_stop(hcd);
484 return ret;
485 }
486
487 /*-------------------------------------------------------------------------*/
488
489 /* Start an OHCI controller, set the BUS operational
490 * resets USB and controller
491 * enable interrupts
492 */
493 static int admhc_run(struct admhcd *ahcd)
494 {
495 u32 temp;
496 int first = ahcd->fminterval == 0;
497 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
498
499 admhc_disable(ahcd);
500
501 /* boot firmware should have set this up (5.1.1.3.1) */
502 if (first) {
503 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
504 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
505 if (ahcd->fminterval != FI)
506 admhc_dbg(ahcd, "fminterval delta %d\n",
507 ahcd->fminterval - FI);
508 ahcd->fminterval |=
509 (FSLDP (ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
510 /* also: power/overcurrent flags in rhdesc */
511 }
512
513 #if 0 /* TODO: not applicable */
514 /* Reset USB nearly "by the book". RemoteWakeupConnected was
515 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
516 * or if bus glue did the same (e.g. for PCI add-in cards with
517 * PCI PM support).
518 */
519 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
520 && !device_may_wakeup(hcd->self.controller))
521 device_init_wakeup(hcd->self.controller, 1);
522 #endif
523
524 switch (ahcd->host_control & ADMHC_HC_BUSS) {
525 case ADMHC_BUSS_OPER:
526 temp = 0;
527 break;
528 case ADMHC_BUSS_SUSPEND:
529 /* FALLTHROUGH ? */
530 case ADMHC_BUSS_RESUME:
531 ahcd->host_control = ADMHC_BUSS_RESUME;
532 temp = 10 /* msec wait */;
533 break;
534 /* case ADMHC_BUSS_RESET: */
535 default:
536 ahcd->host_control = ADMHC_BUSS_RESET;
537 temp = 50 /* msec wait */;
538 break;
539 }
540 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
541
542 /* flush the writes */
543 admhc_writel_flush(ahcd);
544
545 msleep(temp);
546 temp = admhc_get_rhdesc(ahcd);
547 if (!(temp & ADMHC_RH_NPS)) {
548 /* power down each port */
549 for (temp = 0; temp < ahcd->num_ports; temp++)
550 admhc_writel(ahcd, ADMHC_PS_CPP,
551 &ahcd->regs->portstatus[temp]);
552 }
553 /* flush those writes */
554 admhc_writel_flush(ahcd);
555
556 /* 2msec timelimit here means no irqs/preempt */
557 spin_lock_irq(&ahcd->lock);
558
559 retry:
560 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
561 temp = 30; /* ... allow extra time */
562 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
563 if (--temp == 0) {
564 spin_unlock_irq(&ahcd->lock);
565 admhc_err(ahcd, "USB HC reset timed out!\n");
566 return -1;
567 }
568 udelay (1);
569 }
570
571 /* enable HOST mode, before access any host specific register */
572 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
573
574 /* Tell the controller where the descriptor list is */
575 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
576
577 periodic_reinit(ahcd);
578
579 /* use rhsc irqs after khubd is fully initialized */
580 hcd->poll_rh = 1;
581 hcd->uses_new_polling = 1;
582
583 #if 0
584 /* wake on ConnectStatusChange, matching external hubs */
585 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
586 #else
587 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
588 #endif
589
590 /* Choose the interrupts we care about now, others later on demand */
591 admhc_intr_ack(ahcd, ~0);
592 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
593
594 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
595
596 /* flush those writes */
597 admhc_writel_flush(ahcd);
598
599 /* start controller operations */
600 ahcd->host_control = ADMHC_BUSS_OPER;
601 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
602
603 temp = 20;
604 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
605 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
606 if (--temp == 0) {
607 spin_unlock_irq(&ahcd->lock);
608 admhc_err(ahcd, "unable to setup operational mode!\n");
609 return -1;
610 }
611 mdelay(1);
612 }
613
614 hcd->state = HC_STATE_RUNNING;
615
616 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
617
618 #if 0
619 /* FIXME: enabling DMA is always failed here for an unknown reason */
620 admhc_dma_enable(ahcd);
621
622 temp = 200;
623 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
624 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
625 if (--temp == 0) {
626 spin_unlock_irq(&ahcd->lock);
627 admhc_err(ahcd, "unable to enable DMA!\n");
628 admhc_dump(ahcd, 1);
629 return -1;
630 }
631 mdelay(1);
632 }
633
634 #endif
635
636 spin_unlock_irq(&ahcd->lock);
637
638 mdelay(ADMHC_POTPGT);
639
640 return 0;
641 }
642
643 /*-------------------------------------------------------------------------*/
644
645 /* an interrupt happens */
646
647 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
648 {
649 struct admhcd *ahcd = hcd_to_admhcd(hcd);
650 struct admhcd_regs __iomem *regs = ahcd->regs;
651 u32 ints;
652
653 ints = admhc_readl(ahcd, &regs->int_status);
654 if ((ints & ADMHC_INTR_INTA) == 0) {
655 /* no unmasked interrupt status is set */
656 return IRQ_NONE;
657 }
658
659 ints &= admhc_readl(ahcd, &regs->int_enable);
660
661 if (ints & ADMHC_INTR_FATI) {
662 /* e.g. due to PCI Master/Target Abort */
663 admhc_disable(ahcd);
664 admhc_err(ahcd, "Fatal Error, controller disabled\n");
665 admhc_dump(ahcd, 1);
666 admhc_usb_reset(ahcd);
667 }
668
669 if (ints & ADMHC_INTR_INSM) {
670 admhc_vdbg(ahcd, "Root Hub Status Change\n");
671 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
672 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
673
674 /* NOTE: Vendors didn't always make the same implementation
675 * choices for RHSC. Many followed the spec; RHSC triggers
676 * on an edge, like setting and maybe clearing a port status
677 * change bit. With others it's level-triggered, active
678 * until khubd clears all the port status change bits. We'll
679 * always disable it here and rely on polling until khubd
680 * re-enables it.
681 */
682 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
683 usb_hcd_poll_rh_status(hcd);
684 } else if (ints & ADMHC_INTR_RESI) {
685 /* For connect and disconnect events, we expect the controller
686 * to turn on RHSC along with RD. But for remote wakeup events
687 * this might not happen.
688 */
689 admhc_vdbg(ahcd, "Resume Detect\n");
690 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
691 hcd->poll_rh = 1;
692 if (ahcd->autostop) {
693 spin_lock(&ahcd->lock);
694 admhc_rh_resume(ahcd);
695 spin_unlock(&ahcd->lock);
696 } else
697 usb_hcd_resume_root_hub(hcd);
698 }
699
700 if (ints & ADMHC_INTR_TDC) {
701 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
702 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
703 if (HC_IS_RUNNING(hcd->state))
704 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
705 spin_lock(&ahcd->lock);
706 admhc_td_complete(ahcd);
707 spin_unlock(&ahcd->lock);
708 if (HC_IS_RUNNING(hcd->state))
709 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
710 }
711
712 if (ints & ADMHC_INTR_SO) {
713 /* could track INTR_SO to reduce available PCI/... bandwidth */
714 admhc_vdbg(ahcd, "Schedule Overrun\n");
715 }
716
717 if (ints & ADMHC_INTR_BABI) {
718 admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
719 admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
720 admhc_err(ahcd, "Babble Detected\n");
721 }
722
723 #if 1
724 spin_lock(&ahcd->lock);
725 if (ahcd->ed_rm_list)
726 finish_unlinks(ahcd, admhc_frame_no(ahcd));
727
728 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
729 && HC_IS_RUNNING(hcd->state))
730 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
731 spin_unlock(&ahcd->lock);
732 #else
733 if (ints & ADMHC_INTR_SOFI) {
734 admhc_vdbg(ahcd, "Start Of Frame\n");
735 spin_lock(&ahcd->lock);
736
737 /* handle any pending ED removes */
738 finish_unlinks(ahcd, admhc_frameno(ahcd));
739
740 /* leaving INTR_SOFI enabled when there's still unlinking
741 * to be done in the (next frame).
742 */
743 if ((ahcd->ed_rm_list == NULL) ||
744 HC_IS_RUNNING(hcd->state) == 0)
745 /*
746 * disable INTR_SOFI if there are no unlinking to be
747 * done (in the next frame)
748 */
749 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
750
751 spin_unlock(&ahcd->lock);
752 }
753 #endif
754
755 if (HC_IS_RUNNING(hcd->state)) {
756 admhc_intr_ack(ahcd, ints);
757 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
758 admhc_writel_flush(ahcd);
759 }
760
761 return IRQ_HANDLED;
762 }
763
764 /*-------------------------------------------------------------------------*/
765
766 static void admhc_stop(struct usb_hcd *hcd)
767 {
768 struct admhcd *ahcd = hcd_to_admhcd(hcd);
769
770 admhc_dump(ahcd, 1);
771
772 flush_scheduled_work();
773
774 admhc_usb_reset(ahcd);
775 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
776
777 free_irq(hcd->irq, hcd);
778 hcd->irq = -1;
779
780 remove_debug_files(ahcd);
781 admhc_eds_cleanup(ahcd);
782 admhc_mem_cleanup(ahcd);
783 }
784
785 /*-------------------------------------------------------------------------*/
786
787 /* must not be called from interrupt context */
788
789 #ifdef CONFIG_PM
790
791 static int admhc_restart(struct admhcd *ahcd)
792 {
793 int temp;
794 int i;
795 struct urb_priv *priv;
796
797 /* mark any devices gone, so they do nothing till khubd disconnects.
798 * recycle any "live" eds/tds (and urbs) right away.
799 * later, khubd disconnect processing will recycle the other state,
800 * (either as disconnect/reconnect, or maybe someday as a reset).
801 */
802 spin_lock_irq(&ahcd->lock);
803 admhc_disable(ahcd);
804 usb_root_hub_lost_power(admhcd_to_hcd(ahcd)->self.root_hub);
805 if (!list_empty(&ahcd->pending))
806 admhc_dbg(ahcd, "abort schedule...\n");
807 list_for_each_entry (priv, &ahcd->pending, pending) {
808 struct urb *urb = priv->td[0]->urb;
809 struct ed *ed = priv->ed;
810
811 switch (ed->state) {
812 case ED_OPER:
813 ed->state = ED_UNLINK;
814 ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
815 ed_deschedule (ahcd, ed);
816
817 ed->ed_next = ahcd->ed_rm_list;
818 ed->ed_prev = NULL;
819 ahcd->ed_rm_list = ed;
820 /* FALLTHROUGH */
821 case ED_UNLINK:
822 break;
823 default:
824 admhc_dbg(ahcd, "bogus ed %p state %d\n",
825 ed, ed->state);
826 }
827
828 spin_lock(&urb->lock);
829 urb->status = -ESHUTDOWN;
830 spin_unlock(&urb->lock);
831 }
832 finish_unlinks (ahcd, 0);
833 spin_unlock_irq(&ahcd->lock);
834
835 /* paranoia, in case that didn't work: */
836
837 /* empty the interrupt branches */
838 for (i = 0; i < NUM_INTS; i++) ahcd->load[i] = 0;
839 for (i = 0; i < NUM_INTS; i++) ahcd->hcca->int_table[i] = 0;
840
841 /* no EDs to remove */
842 ahcd->ed_rm_list = NULL;
843
844 /* empty control and bulk lists */
845 ahcd->ed_controltail = NULL;
846 ahcd->ed_bulktail = NULL;
847
848 if ((temp = admhc_run(ahcd)) < 0) {
849 admhc_err(ahcd, "can't restart, %d\n", temp);
850 return temp;
851 } else {
852 /* here we "know" root ports should always stay powered,
853 * and that if we try to turn them back on the root hub
854 * will respond to CSC processing.
855 */
856 i = ahcd->num_ports;
857 while (i--)
858 admhc_writel(ahcd, RH_PS_PSS,
859 &ahcd->regs->portstatus[i]);
860 admhc_dbg(ahcd, "restart complete\n");
861 }
862 return 0;
863 }
864 #endif
865
866 /*-------------------------------------------------------------------------*/
867
868 #ifdef CONFIG_MIPS_ADM5120
869 #include "adm5120-drv.c"
870 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
871 #endif
872
873 #if !defined(PLATFORM_DRIVER)
874 #error "missing bus glue for admhc-hcd"
875 #endif
876
877 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
878
879 static int __init admhc_hcd_mod_init(void)
880 {
881 int retval = 0;
882
883 if (usb_disabled())
884 return -ENODEV;
885
886 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
887 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
888 sizeof (struct ed), sizeof (struct td));
889
890 #ifdef PLATFORM_DRIVER
891 retval = platform_driver_register(&PLATFORM_DRIVER);
892 if (retval < 0)
893 goto error_platform;
894 #endif
895
896 return retval;
897
898 #ifdef PLATFORM_DRIVER
899 platform_driver_unregister(&PLATFORM_DRIVER);
900 error_platform:
901 #endif
902 return retval;
903 }
904 module_init(admhc_hcd_mod_init);
905
906 static void __exit admhc_hcd_mod_exit(void)
907 {
908 platform_driver_unregister(&PLATFORM_DRIVER);
909 }
910 module_exit(admhc_hcd_mod_exit);
911
912 MODULE_AUTHOR(DRIVER_AUTHOR);
913 MODULE_DESCRIPTION(DRIVER_INFO);
914 MODULE_LICENSE("GPL");
OpenWrt Source Repository