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USB driver fixes
[openwrt/openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ahcd fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
17 *
18 * This file is licenced under the GPL.
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "v0.03"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #define ADMHC_VERBOSE_DEBUG /* not always helpful */
55 #undef ADMHC_LOCK_DMA
56
57 /* For initializing controller (mask in an HCFS mode too) */
58 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59
60 #define ADMHC_INTR_INIT \
61 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
62 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
63
64 /*-------------------------------------------------------------------------*/
65
66 static const char hcd_name [] = "admhc-hcd";
67
68 #define STATECHANGE_DELAY msecs_to_jiffies(300)
69
70 #include "adm5120.h"
71
72 static void admhc_dump(struct admhcd *ahcd, int verbose);
73 static int admhc_init(struct admhcd *ahcd);
74 static void admhc_stop(struct usb_hcd *hcd);
75
76 #include "adm5120-dbg.c"
77 #include "adm5120-mem.c"
78 #include "adm5120-pm.c"
79 #include "adm5120-hub.c"
80 #include "adm5120-q.c"
81
82 /*-------------------------------------------------------------------------*/
83
84 /*
85 * queue up an urb for anything except the root hub
86 */
87 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
88 struct urb *urb, gfp_t mem_flags)
89 {
90 struct admhcd *ahcd = hcd_to_admhcd(hcd);
91 struct ed *ed;
92 struct urb_priv *urb_priv;
93 unsigned int pipe = urb->pipe;
94 int td_cnt = 0;
95 unsigned long flags;
96 int ret = 0;
97
98 #ifdef ADMHC_VERBOSE_DEBUG
99 spin_lock_irqsave(&ahcd->lock, flags);
100 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
101 spin_unlock_irqrestore(&ahcd->lock, flags);
102 #endif
103
104 /* every endpoint has an ed, locate and maybe (re)initialize it */
105 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
106 if (!ed)
107 return -ENOMEM;
108
109 /* for the private part of the URB we need the number of TDs */
110 switch (ed->type) {
111 case PIPE_CONTROL:
112 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
113 /* td_submit_urb() doesn't yet handle these */
114 return -EMSGSIZE;
115
116 /* 1 TD for setup, 1 for ACK, plus ... */
117 td_cnt = 2;
118 if (urb->transfer_buffer_length)
119 td_cnt++;
120 break;
121 case PIPE_BULK:
122 /* one TD for every 4096 Bytes (can be upto 8K) */
123 td_cnt = urb->transfer_buffer_length / TD_DATALEN_MAX;
124 /* ... and for any remaining bytes ... */
125 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
126 td_cnt++;
127 /* ... and maybe a zero length packet to wrap it up */
128 if (td_cnt == 0)
129 td_cnt++;
130 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
131 && (urb->transfer_buffer_length
132 % usb_maxpacket(urb->dev, pipe,
133 usb_pipeout (pipe))) == 0)
134 td_cnt++;
135 break;
136 case PIPE_INTERRUPT:
137 /*
138 * for Interrupt IN/OUT transactions, each ED contains
139 * only 1 TD.
140 * TODO: check transfer_buffer_length?
141 */
142 td_cnt = 1;
143 break;
144 case PIPE_ISOCHRONOUS:
145 /* number of packets from URB */
146 td_cnt = urb->number_of_packets;
147 break;
148 default:
149 /* paranoia */
150 admhc_err(ahcd, "bad EP type %d", ed->type);
151 return -EINVAL;
152 }
153
154 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
155 if (!urb_priv)
156 return -ENOMEM;
157
158 urb_priv->ed = ed;
159 urb_priv->urb = urb;
160
161 spin_lock_irqsave(&ahcd->lock, flags);
162 /* don't submit to a dead HC */
163 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
164 ret = -ENODEV;
165 goto fail;
166 }
167 if (!HC_IS_RUNNING(hcd->state)) {
168 ret = -ENODEV;
169 goto fail;
170 }
171
172 /* in case of unlink-during-submit */
173 spin_lock(&urb->lock);
174 if (urb->status != -EINPROGRESS) {
175 spin_unlock(&urb->lock);
176 urb->hcpriv = urb_priv;
177 finish_urb(ahcd, urb);
178 ret = 0;
179 goto fail;
180 }
181
182 if (ed->type == PIPE_ISOCHRONOUS) {
183 if (ed->state == ED_NEW) {
184 u16 frame = admhc_frame_no(ahcd);
185
186 /* delay a few frames before the first TD */
187 frame += max_t (u16, 8, ed->interval);
188 frame &= ~(ed->interval - 1);
189 frame |= ed->branch;
190 urb->start_frame = frame;
191
192 /* yes, only URB_ISO_ASAP is supported, and
193 * urb->start_frame is never used as input.
194 */
195 } else
196 urb->start_frame = ed->last_iso + ed->interval;
197 }
198
199 urb->hcpriv = urb_priv;
200 td_submit_urb(ahcd, urb_priv->urb);
201
202 /* append it to the ED's queue */
203 list_add_tail(&urb_priv->pending, &ed->urb_pending);
204
205 /* schedule the ED */
206 ret = ed_schedule(ahcd, ed);
207
208 fail0:
209 spin_unlock(&urb->lock);
210 fail:
211 if (ret) {
212 urb_priv = urb->hcpriv;
213 urb_priv_free(ahcd, urb_priv);
214 }
215
216 spin_unlock_irqrestore(&ahcd->lock, flags);
217 return ret;
218 }
219
220 /*
221 * decouple the URB from the HC queues (TDs, urb_priv); it's
222 * already marked using urb->status. reporting is always done
223 * asynchronously, and we might be dealing with an urb that's
224 * partially transferred, or an ED with other urbs being unlinked.
225 */
226 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
227 {
228 struct admhcd *ahcd = hcd_to_admhcd(hcd);
229 struct urb_priv *up;
230 unsigned long flags;
231
232 up = urb->hcpriv;
233 if (!up)
234 return 0;
235
236 spin_lock_irqsave(&ahcd->lock, flags);
237
238 #ifdef ADMHC_VERBOSE_DEBUG
239 urb_print(ahcd, urb, "DEQEUE", 1);
240 #endif
241
242 if (HC_IS_RUNNING(hcd->state)) {
243 /* Unless an IRQ completed the unlink while it was being
244 * handed to us, flag it for unlink and giveback, and force
245 * some upcoming INTR_SF to call finish_unlinks()
246 */
247 if (up->ed->urb_active != up) {
248 list_del(&up->pending);
249 finish_urb(ahcd, urb);
250 } else {
251 ed_start_deschedule(ahcd, up->ed);
252 }
253 } else {
254 /*
255 * with HC dead, we won't respect hc queue pointers
256 * any more ... just clean up every urb's memory.
257 */
258 if (up->ed->urb_active != up) {
259 list_del(&up->pending);
260 finish_urb(ahcd, urb);
261 } else {
262 finish_urb(ahcd, urb);
263 up->ed->urb_active = NULL;
264 up->ed->state = ED_IDLE;
265 }
266 }
267 spin_unlock_irqrestore(&ahcd->lock, flags);
268
269 return 0;
270 }
271
272 /*-------------------------------------------------------------------------*/
273
274 /* frees config/altsetting state for endpoints,
275 * including ED memory, dummy TD, and bulk/intr data toggle
276 */
277 static void admhc_endpoint_disable(struct usb_hcd *hcd,
278 struct usb_host_endpoint *ep)
279 {
280 struct admhcd *ahcd = hcd_to_admhcd(hcd);
281 unsigned long flags;
282 struct ed *ed = ep->hcpriv;
283 unsigned limit = 1000;
284
285 /* ASSERT: any requests/urbs are being unlinked */
286 /* ASSERT: nobody can be submitting urbs for this any more */
287
288 if (!ed)
289 return;
290
291 #ifdef ADMHC_VERBOSE_DEBUG
292 spin_lock_irqsave(&ahcd->lock, flags);
293 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
294 spin_unlock_irqrestore(&ahcd->lock, flags);
295 #endif
296
297 rescan:
298 spin_lock_irqsave(&ahcd->lock, flags);
299
300 if (!HC_IS_RUNNING(hcd->state)) {
301 sanitize:
302 ed->state = ED_UNLINK;
303 admhc_finish_unlinks(ahcd, 0);
304 }
305
306 switch (ed->state) {
307 case ED_UNLINK: /* wait for hw to finish? */
308 /* major IRQ delivery trouble loses INTR_SOFI too... */
309 if (limit-- == 0) {
310 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
311 goto sanitize;
312 }
313 spin_unlock_irqrestore(&ahcd->lock, flags);
314 schedule_timeout_uninterruptible(1);
315 goto rescan;
316 case ED_IDLE:
317 case ED_NEW: /* fully unlinked */
318 if (list_empty(&ed->urb_pending)) {
319 td_free(ahcd, ed->dummy);
320 ed_free(ahcd, ed);
321 break;
322 }
323 /* else FALL THROUGH */
324 default:
325 /* caller was supposed to have unlinked any requests;
326 * that's not our job. can't recover; must leak ed.
327 */
328 admhc_err(ahcd, "leak ed %p (#%02x) %s act %p%s\n",
329 ed, ep->desc.bEndpointAddress,
330 ed_statestring(ed->state),
331 ed->urb_active,
332 list_empty(&ed->urb_pending) ? "" : " (has urbs)");
333 break;
334 }
335
336 ep->hcpriv = NULL;
337
338 spin_unlock_irqrestore(&ahcd->lock, flags);
339 return;
340 }
341
342 static int admhc_get_frame_number(struct usb_hcd *hcd)
343 {
344 struct admhcd *ahcd = hcd_to_admhcd(hcd);
345
346 return admhc_frame_no(ahcd);
347 }
348
349 static void admhc_usb_reset(struct admhcd *ahcd)
350 {
351 ahcd->host_control = ADMHC_BUSS_RESET;
352 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
353 }
354
355 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
356 * other cases where the next software may expect clean state from the
357 * "firmware". this is bus-neutral, unlike shutdown() methods.
358 */
359 static void
360 admhc_shutdown(struct usb_hcd *hcd)
361 {
362 struct admhcd *ahcd;
363
364 ahcd = hcd_to_admhcd(hcd);
365 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
366 admhc_dma_disable(ahcd);
367 admhc_usb_reset(ahcd);
368 }
369
370 /*-------------------------------------------------------------------------*
371 * HC functions
372 *-------------------------------------------------------------------------*/
373
374 static void admhc_eds_cleanup(struct admhcd *ahcd)
375 {
376 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
377 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
378 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
379 }
380
381 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
382 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
383 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
384 }
385
386 if (ahcd->ed_tails[PIPE_CONTROL]) {
387 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
388 ahcd->ed_tails[PIPE_CONTROL] = NULL;
389 }
390
391 if (ahcd->ed_tails[PIPE_BULK]) {
392 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
393 ahcd->ed_tails[PIPE_BULK] = NULL;
394 }
395
396 ahcd->ed_head = NULL;
397 }
398
399 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
400
401 static int admhc_eds_init(struct admhcd *ahcd)
402 {
403 struct ed *ed;
404
405 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
406 if (!ed)
407 goto err;
408
409 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
410
411 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
412 if (!ed)
413 goto err;
414
415 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
416 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
417 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
418 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
419
420 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
421 if (!ed)
422 goto err;
423
424 ahcd->ed_tails[PIPE_CONTROL] = ed;
425 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
426 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
427 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
428
429 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
430 if (!ed)
431 goto err;
432
433 ahcd->ed_tails[PIPE_BULK] = ed;
434 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
435 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
436 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
437
438 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
439
440 #ifdef ADMHC_VERBOSE_DEBUG
441 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
442 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
443 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
444 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
445 #endif
446
447 return 0;
448
449 err:
450 admhc_eds_cleanup(ahcd);
451 return -ENOMEM;
452 }
453
454 /* init memory, and kick BIOS/SMM off */
455
456 static int admhc_init(struct admhcd *ahcd)
457 {
458 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
459 int ret;
460
461 admhc_disable(ahcd);
462 ahcd->regs = hcd->regs;
463
464 /* Disable HC interrupts */
465 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
466
467 /* Read the number of ports unless overridden */
468 if (ahcd->num_ports == 0)
469 ahcd->num_ports = admhc_get_rhdesc(ahcd) & ADMHC_RH_NUMP;
470
471 ret = admhc_mem_init(ahcd);
472 if (ret)
473 goto err;
474
475 /* init dummy endpoints */
476 ret = admhc_eds_init(ahcd);
477 if (ret)
478 goto err;
479
480 create_debug_files(ahcd);
481
482 return 0;
483
484 err:
485 admhc_stop(hcd);
486 return ret;
487 }
488
489 /*-------------------------------------------------------------------------*/
490
491 /* Start an OHCI controller, set the BUS operational
492 * resets USB and controller
493 * enable interrupts
494 */
495 static int admhc_run(struct admhcd *ahcd)
496 {
497 u32 temp;
498 int first = ahcd->fminterval == 0;
499 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
500
501 admhc_disable(ahcd);
502
503 /* boot firmware should have set this up (5.1.1.3.1) */
504 if (first) {
505 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
506 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
507 if (ahcd->fminterval != FI)
508 admhc_dbg(ahcd, "fminterval delta %d\n",
509 ahcd->fminterval - FI);
510 ahcd->fminterval |=
511 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
512 /* also: power/overcurrent flags in rhdesc */
513 }
514
515 switch (ahcd->host_control & ADMHC_HC_BUSS) {
516 case ADMHC_BUSS_OPER:
517 temp = 0;
518 break;
519 case ADMHC_BUSS_SUSPEND:
520 /* FALLTHROUGH ? */
521 case ADMHC_BUSS_RESUME:
522 ahcd->host_control = ADMHC_BUSS_RESUME;
523 temp = 10 /* msec wait */;
524 break;
525 /* case ADMHC_BUSS_RESET: */
526 default:
527 ahcd->host_control = ADMHC_BUSS_RESET;
528 temp = 50 /* msec wait */;
529 break;
530 }
531 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
532
533 msleep(temp);
534 temp = admhc_get_rhdesc(ahcd);
535 if (!(temp & ADMHC_RH_NPS)) {
536 /* power down each port */
537 for (temp = 0; temp < ahcd->num_ports; temp++)
538 admhc_writel(ahcd, ADMHC_PS_CPP,
539 &ahcd->regs->portstatus[temp]);
540 }
541
542 /* 2msec timelimit here means no irqs/preempt */
543 spin_lock_irq(&ahcd->lock);
544
545 retry:
546 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
547 temp = 30; /* ... allow extra time */
548 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
549 if (--temp == 0) {
550 spin_unlock_irq(&ahcd->lock);
551 admhc_err(ahcd, "USB HC reset timed out!\n");
552 return -1;
553 }
554 udelay (1);
555 }
556
557 /* enable HOST mode, before access any host specific register */
558 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
559
560 /* Tell the controller where the descriptor list is */
561 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
562
563 periodic_reinit(ahcd);
564
565 /* use rhsc irqs after khubd is fully initialized */
566 hcd->poll_rh = 1;
567 hcd->uses_new_polling = 1;
568
569 #if 0
570 /* wake on ConnectStatusChange, matching external hubs */
571 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
572 #else
573 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
574 #endif
575
576 /* Choose the interrupts we care about now, others later on demand */
577 admhc_intr_ack(ahcd, ~0);
578 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
579
580 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
581
582 /* start controller operations */
583 ahcd->host_control = ADMHC_BUSS_OPER;
584 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
585
586 temp = 20;
587 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
588 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
589 if (--temp == 0) {
590 spin_unlock_irq(&ahcd->lock);
591 admhc_err(ahcd, "unable to setup operational mode!\n");
592 return -1;
593 }
594 mdelay(1);
595 }
596
597 hcd->state = HC_STATE_RUNNING;
598 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
599
600 spin_unlock_irq(&ahcd->lock);
601
602 mdelay(ADMHC_POTPGT);
603
604 return 0;
605 }
606
607 /*-------------------------------------------------------------------------*/
608
609 /* an interrupt happens */
610
611 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
612 {
613 struct admhcd *ahcd = hcd_to_admhcd(hcd);
614 struct admhcd_regs __iomem *regs = ahcd->regs;
615 u32 ints;
616
617 ints = admhc_readl(ahcd, &regs->int_status);
618 if ((ints & ADMHC_INTR_INTA) == 0) {
619 /* no unmasked interrupt status is set */
620 return IRQ_NONE;
621 }
622
623 ints &= admhc_readl(ahcd, &regs->int_enable);
624
625 if (ints & ADMHC_INTR_FATI) {
626 /* e.g. due to PCI Master/Target Abort */
627 admhc_disable(ahcd);
628 admhc_err(ahcd, "Fatal Error, controller disabled\n");
629 admhc_dump(ahcd, 1);
630 admhc_usb_reset(ahcd);
631 }
632
633 if (ints & ADMHC_INTR_BABI) {
634 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
635 admhc_err(ahcd, "Babble Detected\n");
636 admhc_disable(ahcd);
637 admhc_usb_reset(ahcd);
638 }
639
640 if (ints & ADMHC_INTR_INSM) {
641 admhc_vdbg(ahcd, "Root Hub Status Change\n");
642 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
643 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
644
645 /* NOTE: Vendors didn't always make the same implementation
646 * choices for RHSC. Many followed the spec; RHSC triggers
647 * on an edge, like setting and maybe clearing a port status
648 * change bit. With others it's level-triggered, active
649 * until khubd clears all the port status change bits. We'll
650 * always disable it here and rely on polling until khubd
651 * re-enables it.
652 */
653 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
654 usb_hcd_poll_rh_status(hcd);
655 } else if (ints & ADMHC_INTR_RESI) {
656 /* For connect and disconnect events, we expect the controller
657 * to turn on RHSC along with RD. But for remote wakeup events
658 * this might not happen.
659 */
660 admhc_vdbg(ahcd, "Resume Detect\n");
661 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
662 hcd->poll_rh = 1;
663 if (ahcd->autostop) {
664 admhc_rh_resume(ahcd);
665 } else
666 usb_hcd_resume_root_hub(hcd);
667 }
668
669 if (ints & ADMHC_INTR_TDC) {
670 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
671 if (HC_IS_RUNNING(hcd->state))
672 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
673 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
674 spin_lock(&ahcd->lock);
675 admhc_td_complete(ahcd);
676 spin_unlock(&ahcd->lock);
677 if (HC_IS_RUNNING(hcd->state))
678 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
679 }
680
681 if (ints & ADMHC_INTR_SO) {
682 /* could track INTR_SO to reduce available PCI/... bandwidth */
683 admhc_vdbg(ahcd, "Schedule Overrun\n");
684 }
685
686 if (ints & ADMHC_INTR_SOFI) {
687 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
688 /* handle any pending ED removes */
689 admhc_finish_unlinks(ahcd, admhc_frame_no(ahcd));
690 spin_lock(&ahcd->lock);
691 admhc_sof_refill(ahcd);
692 spin_unlock(&ahcd->lock);
693 }
694
695 if (HC_IS_RUNNING(hcd->state)) {
696 admhc_intr_ack(ahcd, ints);
697 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
698 }
699
700 return IRQ_HANDLED;
701 }
702
703 /*-------------------------------------------------------------------------*/
704
705 static void admhc_stop(struct usb_hcd *hcd)
706 {
707 struct admhcd *ahcd = hcd_to_admhcd(hcd);
708
709 admhc_dump(ahcd, 1);
710
711 flush_scheduled_work();
712
713 admhc_usb_reset(ahcd);
714 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
715
716 free_irq(hcd->irq, hcd);
717 hcd->irq = -1;
718
719 remove_debug_files(ahcd);
720 admhc_eds_cleanup(ahcd);
721 admhc_mem_cleanup(ahcd);
722 }
723
724 /*-------------------------------------------------------------------------*/
725
726 #ifdef CONFIG_MIPS_ADM5120
727 #include "adm5120-drv.c"
728 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
729 #endif
730
731 #if !defined(PLATFORM_DRIVER)
732 #error "missing bus glue for admhc-hcd"
733 #endif
734
735 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
736
737 static int __init admhc_hcd_mod_init(void)
738 {
739 int ret = 0;
740
741 if (usb_disabled())
742 return -ENODEV;
743
744 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
745 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
746 sizeof (struct ed), sizeof (struct td));
747
748 #ifdef PLATFORM_DRIVER
749 ret = platform_driver_register(&PLATFORM_DRIVER);
750 if (ret < 0)
751 goto error_platform;
752 #endif
753
754 return ret;
755
756 #ifdef PLATFORM_DRIVER
757 platform_driver_unregister(&PLATFORM_DRIVER);
758 error_platform:
759 #endif
760 return ret;
761 }
762 module_init(admhc_hcd_mod_init);
763
764 static void __exit admhc_hcd_mod_exit(void)
765 {
766 platform_driver_unregister(&PLATFORM_DRIVER);
767 }
768 module_exit(admhc_hcd_mod_exit);
769
770 MODULE_AUTHOR(DRIVER_AUTHOR);
771 MODULE_DESCRIPTION(DRIVER_INFO);
772 MODULE_LICENSE("GPL");
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