target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch

   1 --- a/drivers/spi/Kconfig
   2 +++ b/drivers/spi/Kconfig
   3 @@ -307,6 +307,12 @@ config SPI_DLN2
   4          This driver can also be built as a module.  If so, the module
   5          will be called spi-dln2.
   6
   7 +config SPI_AIROHA_EN7523
   8 +       bool "Airoha EN7523 SPI controller support"
   9 +       depends on ARCH_AIROHA
  10 +       help
  11 +         This enables SPI controller support for the Airoha EN7523 SoC.
  12 +
  13  config SPI_EP93XX
  14         tristate "Cirrus Logic EP93xx SPI controller"
  15         depends on ARCH_EP93XX || COMPILE_TEST
  16 --- a/drivers/spi/Makefile
  17 +++ b/drivers/spi/Makefile
  18 @@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_DW_BT1)              += spi-dw-bt1.
  19  obj-$(CONFIG_SPI_DW_MMIO)              += spi-dw-mmio.o
  20  obj-$(CONFIG_SPI_DW_PCI)               += spi-dw-pci.o
  21  obj-$(CONFIG_SPI_EP93XX)               += spi-ep93xx.o
  22 +obj-$(CONFIG_SPI_AIROHA_EN7523)                += spi-en7523.o
  23  obj-$(CONFIG_SPI_FALCON)               += spi-falcon.o
  24  obj-$(CONFIG_SPI_FSI)                  += spi-fsi.o
  25  obj-$(CONFIG_SPI_FSL_CPM)              += spi-fsl-cpm.o
  26 --- /dev/null
  27 +++ b/drivers/spi/spi-en7523.c
  28 @@ -0,0 +1,311 @@
  29 +// SPDX-License-Identifier: GPL-2.0
  30 +
  31 +#include <linux/module.h>
  32 +#include <linux/platform_device.h>
  33 +#include <linux/mod_devicetable.h>
  34 +#include <linux/spi/spi.h>
  35 +
  36 +
  37 +#define ENSPI_READ_IDLE_EN                     0x0004
  38 +#define ENSPI_MTX_MODE_TOG                     0x0014
  39 +#define ENSPI_RDCTL_FSM                                0x0018
  40 +#define ENSPI_MANUAL_EN                                0x0020
  41 +#define ENSPI_MANUAL_OPFIFO_EMPTY              0x0024
  42 +#define ENSPI_MANUAL_OPFIFO_WDATA              0x0028
  43 +#define ENSPI_MANUAL_OPFIFO_FULL               0x002C
  44 +#define ENSPI_MANUAL_OPFIFO_WR                 0x0030
  45 +#define ENSPI_MANUAL_DFIFO_FULL                        0x0034
  46 +#define ENSPI_MANUAL_DFIFO_WDATA               0x0038
  47 +#define ENSPI_MANUAL_DFIFO_EMPTY               0x003C
  48 +#define ENSPI_MANUAL_DFIFO_RD                  0x0040
  49 +#define ENSPI_MANUAL_DFIFO_RDATA               0x0044
  50 +#define ENSPI_IER                              0x0090
  51 +#define ENSPI_NFI2SPI_EN                       0x0130
  52 +
  53 +// TODO not in spi block
  54 +#define ENSPI_CLOCK_DIVIDER                    ((void __iomem *)0x1fa201c4)
  55 +
  56 +#define        OP_CSH                                  0x00
  57 +#define        OP_CSL                                  0x01
  58 +#define        OP_CK                                   0x02
  59 +#define        OP_OUTS                                 0x08
  60 +#define        OP_OUTD                                 0x09
  61 +#define        OP_OUTQ                                 0x0A
  62 +#define        OP_INS                                  0x0C
  63 +#define        OP_INS0                                 0x0D
  64 +#define        OP_IND                                  0x0E
  65 +#define        OP_INQ                                  0x0F
  66 +#define        OP_OS2IS                                0x10
  67 +#define        OP_OS2ID                                0x11
  68 +#define        OP_OS2IQ                                0x12
  69 +#define        OP_OD2IS                                0x13
  70 +#define        OP_OD2ID                                0x14
  71 +#define        OP_OD2IQ                                0x15
  72 +#define        OP_OQ2IS                                0x16
  73 +#define        OP_OQ2ID                                0x17
  74 +#define        OP_OQ2IQ                                0x18
  75 +#define        OP_OSNIS                                0x19
  76 +#define        OP_ODNID                                0x1A
  77 +
  78 +#define MATRIX_MODE_AUTO               1
  79 +#define   CONF_MTX_MODE_AUTO           0
  80 +#define   MANUALEN_AUTO                        0
  81 +#define MATRIX_MODE_MANUAL             0
  82 +#define   CONF_MTX_MODE_MANUAL         9
  83 +#define   MANUALEN_MANUAL              1
  84 +
  85 +#define _ENSPI_MAX_XFER                        0x1ff
  86 +
  87 +#define REG(x)                 (iobase + x)
  88 +
  89 +
  90 +static void __iomem *iobase;
  91 +
  92 +
  93 +static void opfifo_write(u32 cmd, u32 len)
  94 +{
  95 +       u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
  96 +
  97 +       writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
  98 +
  99 +       /* Wait for room in OPFIFO */
 100 +       while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
 101 +               ;
 102 +
 103 +       /* Shift command into OPFIFO */
 104 +       writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
 105 +
 106 +       /* Wait for command to finish */
 107 +       while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
 108 +               ;
 109 +}
 110 +
 111 +static void set_cs(int state)
 112 +{
 113 +       if (state)
 114 +               opfifo_write(OP_CSH, 1);
 115 +       else
 116 +               opfifo_write(OP_CSL, 1);
 117 +}
 118 +
 119 +static void manual_begin_cmd(void)
 120 +{
 121 +       /* Disable read idle state */
 122 +       writel(0, REG(ENSPI_READ_IDLE_EN));
 123 +
 124 +       /* Wait for FSM to reach idle state */
 125 +       while (readl(REG(ENSPI_RDCTL_FSM)))
 126 +               ;
 127 +
 128 +       /* Set SPI core to manual mode */
 129 +       writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
 130 +       writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
 131 +}
 132 +
 133 +static void manual_end_cmd(void)
 134 +{
 135 +       /* Set SPI core to auto mode */
 136 +       writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
 137 +       writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
 138 +
 139 +       /* Enable read idle state */
 140 +       writel(1, REG(ENSPI_READ_IDLE_EN));
 141 +}
 142 +
 143 +static void dfifo_read(u8 *buf, int len)
 144 +{
 145 +       int i;
 146 +
 147 +       for (i = 0; i < len; i++) {
 148 +               /* Wait for requested data to show up in DFIFO */
 149 +               while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
 150 +                       ;
 151 +               buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
 152 +               /* Queue up next byte */
 153 +               writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
 154 +       }
 155 +}
 156 +
 157 +static void dfifo_write(const u8 *buf, int len)
 158 +{
 159 +       int i;
 160 +
 161 +       for (i = 0; i < len; i++) {
 162 +               /* Wait for room in DFIFO */
 163 +               while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
 164 +                       ;
 165 +               writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
 166 +       }
 167 +}
 168 +
 169 +static void set_spi_clock_speed(int freq_mhz)
 170 +{
 171 +       u32 tmp, val;
 172 +
 173 +       tmp = readl(ENSPI_CLOCK_DIVIDER);
 174 +       tmp &= 0xffff0000;
 175 +       writel(tmp, ENSPI_CLOCK_DIVIDER);
 176 +
 177 +       val = (400 / (freq_mhz * 2));
 178 +       tmp |= (val << 8) | 1;
 179 +       writel(tmp, ENSPI_CLOCK_DIVIDER);
 180 +}
 181 +
 182 +static void init_hw(void)
 183 +{
 184 +       /* Disable manual/auto mode clash interrupt */
 185 +       writel(0, REG(ENSPI_IER));
 186 +
 187 +       // TODO via clk framework
 188 +       // set_spi_clock_speed(50);
 189 +
 190 +       /* Disable DMA */
 191 +       writel(0, REG(ENSPI_NFI2SPI_EN));
 192 +}
 193 +
 194 +static int xfer_read(struct spi_transfer *xfer)
 195 +{
 196 +       int opcode;
 197 +       uint8_t *buf = xfer->rx_buf;
 198 +
 199 +       switch (xfer->rx_nbits) {
 200 +       case SPI_NBITS_SINGLE:
 201 +               opcode = OP_INS;
 202 +               break;
 203 +       case SPI_NBITS_DUAL:
 204 +               opcode = OP_IND;
 205 +               break;
 206 +       case SPI_NBITS_QUAD:
 207 +               opcode = OP_INQ;
 208 +               break;
 209 +       }
 210 +
 211 +       opfifo_write(opcode, xfer->len);
 212 +       dfifo_read(buf, xfer->len);
 213 +
 214 +       return xfer->len;
 215 +}
 216 +
 217 +static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
 218 +{
 219 +       int opcode;
 220 +       const uint8_t *buf = xfer->tx_buf;
 221 +
 222 +       if (next_xfer_is_rx) {
 223 +               /* need to use Ox2Ix opcode to set the core to input afterwards */
 224 +               switch (xfer->tx_nbits) {
 225 +               case SPI_NBITS_SINGLE:
 226 +                       opcode = OP_OS2IS;
 227 +                       break;
 228 +               case SPI_NBITS_DUAL:
 229 +                       opcode = OP_OS2ID;
 230 +                       break;
 231 +               case SPI_NBITS_QUAD:
 232 +                       opcode = OP_OS2IQ;
 233 +                       break;
 234 +               }
 235 +       } else {
 236 +               switch (xfer->tx_nbits) {
 237 +               case SPI_NBITS_SINGLE:
 238 +                       opcode = OP_OUTS;
 239 +                       break;
 240 +               case SPI_NBITS_DUAL:
 241 +                       opcode = OP_OUTD;
 242 +                       break;
 243 +               case SPI_NBITS_QUAD:
 244 +                       opcode = OP_OUTQ;
 245 +                       break;
 246 +               }
 247 +       }
 248 +
 249 +       opfifo_write(opcode, xfer->len);
 250 +       dfifo_write(buf, xfer->len);
 251 +
 252 +       return xfer->len;
 253 +}
 254 +
 255 +size_t max_transfer_size(struct spi_device *spi)
 256 +{
 257 +       return _ENSPI_MAX_XFER;
 258 +}
 259 +
 260 +int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
 261 +{
 262 +       struct spi_transfer *xfer;
 263 +       int next_xfer_is_rx = 0;
 264 +
 265 +       manual_begin_cmd();
 266 +       set_cs(0);
 267 +       list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 268 +               if (xfer->tx_buf) {
 269 +                       if (!list_is_last(&xfer->transfer_list, &msg->transfers)
 270 +                           && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
 271 +                               next_xfer_is_rx = 1;
 272 +                       else
 273 +                               next_xfer_is_rx = 0;
 274 +                       msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
 275 +               } else if (xfer->rx_buf) {
 276 +                       msg->actual_length += xfer_read(xfer);
 277 +               }
 278 +       }
 279 +       set_cs(1);
 280 +       manual_end_cmd();
 281 +
 282 +       msg->status = 0;
 283 +       spi_finalize_current_message(ctrl);
 284 +
 285 +       return 0;
 286 +}
 287 +
 288 +static int spi_probe(struct platform_device *pdev)
 289 +{
 290 +       struct spi_controller *ctrl;
 291 +       int err;
 292 +
 293 +       ctrl = devm_spi_alloc_master(&pdev->dev, 0);
 294 +       if (!ctrl) {
 295 +               dev_err(&pdev->dev, "Error allocating SPI controller\n");
 296 +               return -ENOMEM;
 297 +       }
 298 +
 299 +       iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
 300 +       if (IS_ERR(iobase)) {
 301 +               dev_err(&pdev->dev, "Could not map SPI register address");
 302 +               return -ENOMEM;
 303 +       }
 304 +
 305 +       init_hw();
 306 +
 307 +       ctrl->dev.of_node = pdev->dev.of_node;
 308 +       ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
 309 +       ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
 310 +       ctrl->max_transfer_size = max_transfer_size;
 311 +       ctrl->transfer_one_message = transfer_one_message;
 312 +       err = devm_spi_register_controller(&pdev->dev, ctrl);
 313 +       if (err) {
 314 +               dev_err(&pdev->dev, "Could not register SPI controller\n");
 315 +               return -ENODEV;
 316 +       }
 317 +
 318 +       return 0;
 319 +}
 320 +
 321 +static const struct of_device_id spi_of_ids[] = {
 322 +       { .compatible = "airoha,en7523-spi" },
 323 +       { /* sentinel */ }
 324 +};
 325 +MODULE_DEVICE_TABLE(of, spi_of_ids);
 326 +
 327 +static struct platform_driver spi_driver = {
 328 +       .probe = spi_probe,
 329 +       .driver = {
 330 +               .name = "airoha-en7523-spi",
 331 +               .of_match_table = spi_of_ids,
 332 +       },
 333 +};
 334 +
 335 +module_platform_driver(spi_driver);
 336 +
 337 +MODULE_LICENSE("GPL v2");
 338 +MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
 339 +MODULE_DESCRIPTION("Airoha EN7523 SPI driver");