target/linux/amazon-2.6/files/include/asm-mips/amazon/ifx_peripheral_definitions.h

   1 //*************************************************************************
   2 //* Summary of definitions which are used in each peripheral              *
   3 //*************************************************************************
   4
   5 #ifndef peripheral_definitions_h
   6 #define peripheral_definitions_h
   7
   8 typedef unsigned char           UINT8;
   9 typedef signed char             INT8;
  10 typedef unsigned short          UINT16;
  11 typedef signed short            INT16;
  12 typedef unsigned int            UINT32;
  13 typedef signed int              INT32;
  14 typedef unsigned long long      UINT64;
  15 typedef signed long long        INT64;
  16
  17 #define REG8( addr )              (*(volatile UINT8 *) (addr))
  18 #define REG16( addr )             (*(volatile UINT16 *)(addr))
  19 #define REG32( addr )             (*(volatile UINT32 *)(addr))
  20 #define REG64( addr )             (*(volatile UINT64 *)(addr))
  21
  22 /* define routine to set FPI access in Supervisor Mode */
  23 #define IFX_SUPERVISOR_ON()                         REG32(FB0_CFG) = 0x01
  24 /* Supervisor mode ends, following functions will be done in User mode */
  25 #define IFX_SUPERVISOR_OFF()                        REG32(FB0_CFG) = 0x00
  26 /* Supervisor mode ends, following functions will be done in User mode */
  27 #define IFX_SUPERVISOR_MODE()                       REG32(FB0_CFG)
  28 /* Supervisor mode ends, following functions will be done in User mode */
  29 #define IFX_SUPERVISOR_SET(svm)                     REG32(FB0_CFG) = svm
  30 /* enable all Interrupts in IIU */
  31 //#define IFX_ENABLE_IRQ(irq_mask, im_base)           REG32(im_base | IIU_MASK) = irq_mask
  32 ///* get all high priority interrupt bits in IIU */
  33 //#define IFX_GET_IRQ_MASKED(im_base)                 REG32(im_base | IIU_IRMASKED)
  34 ///* signal ends of interrupt to IIU */
  35 //#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base)      REG32(im_base | IIU_IR) = irq_bit
  36 ///* force IIU interrupt register */
  37 //#define IFX_FORCE_IIU_REGISTER(data, im_base)       REG32(im_base | IIU_IRDEBUG) = data
  38 ///* get all bits of interrupt register */
  39 //#define IFX_GET_IRQ_UNMASKED(im_base)               REG32(im_base | IIU_IR)
  40 /* insert a NOP instruction */
  41 #define NOP                                     _nop()
  42 /* CPU goes to power down mode until interrupt occurs */
  43 #define IFX_CPU_SLEEP                               _sleep()
  44 /* enable all interrupts to CPU */
  45 #define IFX_CPU_ENABLE_ALL_INTERRUPT                sys_enable_int()
  46 /* get all low priority interrupt bits in peripheral */
  47 #define IFX_GET_LOW_PRIO_IRQ(int_reg)               REG32(int_reg)
  48 /* clear low priority interrupt bit in peripheral */
  49 #define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg)    REG32(int_reg) = irq_bit
  50 /* write FPI bus */
  51 #define WRITE_FPI_BYTE(data, addr)              REG8(addr) = data
  52 #define WRITE_FPI_16BIT(data, addr)             REG16(addr) = data
  53 #define WRITE_FPI_32BIT(data, addr)             REG32(addr) = data
  54 /* read FPI bus */
  55 #define READ_FPI_BYTE(addr)                     REG8(addr)
  56 #define READ_FPI_16BIT(addr)                    REG16(addr)
  57 #define READ_FPI_32BIT(addr)                    REG32(addr)
  58 /* write peripheral register */
  59 #define WRITE_PERIPHERAL_REGISTER(data, addr)   REG32(addr) = data
  60
  61 #ifdef  CONFIG_CPU_LITTLE_ENDIAN
  62 #define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
  63 #define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
  64 #else //not CONFIG_CPU_LITTLE_ENDIAN
  65 #define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
  66 #define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
  67 #endif //CONFIG_CPU_LITTLE_ENDIAN
  68
  69 /* read peripheral register */
  70 #define READ_PERIPHERAL_REGISTER(addr)          REG32(addr)
  71
  72 /* read/modify(or)/write peripheral register */
  73 #define RMW_OR_PERIPHERAL_REGISTER(data, addr)  REG32(addr) = REG32(addr) | data
  74 /* read/modify(and)/write peripheral register */
  75 #define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
  76
  77 /* CPU-independent mnemonic constants */
  78 /* CLC register bits */
  79 #define IFX_CLC_ENABLE                0x00000000
  80 #define IFX_CLC_DISABLE               0x00000001
  81 #define IFX_CLC_DISABLE_STATUS        0x00000002
  82 #define IFX_CLC_SUSPEND_ENABLE        0x00000004
  83 #define IFX_CLC_CLOCK_OFF_DISABLE     0x00000008
  84 #define IFX_CLC_OVERWRITE_SPEN_FSOE   0x00000010
  85 #define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
  86 #define IFX_CLC_RUN_DIVIDER_MASK      0x0000FF00
  87 #define IFX_CLC_RUN_DIVIDER_OFFSET    8
  88 #define IFX_CLC_SLEEP_DIVIDER_MASK    0x00FF0000
  89 #define IFX_CLC_SLEEP_DIVIDER_OFFSET  16
  90 #define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
  91 #define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
  92
  93 /* number of cycles to wait for interrupt service routine to be called */
  94 #define WAIT_CYCLES   50
  95
  96 #endif /* PERIPHERAL_DEFINITIONS_H not yet defined */