target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 #ifdef CONFIG_PCI
  25 static void ar71xx_pci_irq_dispatch(void)
  26 {
  27         u32 pending;
  28
  29         pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
  30                   ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  31
  32         if (pending & PCI_INT_DEV0)
  33                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
  34
  35         else if (pending & PCI_INT_DEV1)
  36                 do_IRQ(AR71XX_PCI_IRQ_DEV1);
  37
  38         else if (pending & PCI_INT_DEV2)
  39                 do_IRQ(AR71XX_PCI_IRQ_DEV2);
  40
  41         else if (pending & PCI_INT_CORE)
  42                 do_IRQ(AR71XX_PCI_IRQ_CORE);
  43
  44         else
  45                 spurious_interrupt();
  46 }
  47
  48 static void ar71xx_pci_irq_unmask(unsigned int irq)
  49 {
  50         irq -= AR71XX_PCI_IRQ_BASE;
  51         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  52                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
  53
  54         /* flush write */
  55         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  56 }
  57
  58 static void ar71xx_pci_irq_mask(unsigned int irq)
  59 {
  60         irq -= AR71XX_PCI_IRQ_BASE;
  61         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  62                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
  63
  64         /* flush write */
  65         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  66 }
  67
  68 static struct irq_chip ar71xx_pci_irq_chip = {
  69         .name           = "AR71XX PCI ",
  70         .mask           = ar71xx_pci_irq_mask,
  71         .unmask         = ar71xx_pci_irq_unmask,
  72         .mask_ack       = ar71xx_pci_irq_mask,
  73 };
  74
  75 static struct irqaction ar71xx_pci_irqaction = {
  76         .handler        = no_action,
  77         .name           = "cascade [AR71XX PCI]",
  78 };
  79
  80 static void __init ar71xx_pci_irq_init(void)
  81 {
  82         int i;
  83
  84         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
  85         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
  86
  87         for (i = AR71XX_PCI_IRQ_BASE;
  88              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
  89                 irq_desc[i].status = IRQ_DISABLED;
  90                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
  91                                          handle_level_irq);
  92         }
  93
  94         setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
  95 }
  96 #endif /* CONFIG_PCI */
  97
  98 static void ar71xx_gpio_irq_dispatch(void)
  99 {
 100         u32 pending;
 101
 102         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
 103                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 104
 105         if (pending)
 106                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
 107         else
 108                 spurious_interrupt();
 109 }
 110
 111 static void ar71xx_gpio_irq_unmask(unsigned int irq)
 112 {
 113         irq -= AR71XX_GPIO_IRQ_BASE;
 114         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 115                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
 116
 117         /* flush write */
 118         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 119 }
 120
 121 static void ar71xx_gpio_irq_mask(unsigned int irq)
 122 {
 123         irq -= AR71XX_GPIO_IRQ_BASE;
 124         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 125                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
 126
 127         /* flush write */
 128         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 129 }
 130
 131 #if 0
 132 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 133 {
 134         /* TODO: implement */
 135         return 0;
 136 }
 137 #else
 138 #define ar71xx_gpio_irq_set_type        NULL
 139 #endif
 140
 141 struct irq_chip ar71xx_gpio_irq_chip = {
 142         .name           = "AR71XX GPIO",
 143         .unmask         = ar71xx_gpio_irq_unmask,
 144         .mask           = ar71xx_gpio_irq_mask,
 145         .mask_ack       = ar71xx_gpio_irq_mask,
 146         .set_type       = ar71xx_gpio_irq_set_type,
 147 };
 148
 149 static struct irqaction ar71xx_gpio_irqaction = {
 150         .handler        = no_action,
 151         .name           = "cascade [AR71XX GPIO]",
 152 };
 153
 154 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 155 #define GPIO_INT_ALL    0xffff
 156
 157 static void __init ar71xx_gpio_irq_init(void)
 158 {
 159         int i;
 160
 161         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
 162         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
 163
 164         /* setup type of all GPIO interrupts to level sensitive */
 165         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
 166
 167         /* setup polarity of all GPIO interrupts to active high */
 168         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
 169
 170         for (i = AR71XX_GPIO_IRQ_BASE;
 171              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
 172                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
 173                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 174                                          handle_level_irq);
 175         }
 176
 177         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 178 }
 179
 180 static void ar71xx_misc_irq_dispatch(void)
 181 {
 182         u32 pending;
 183
 184         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 185             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 186
 187         if (pending & MISC_INT_UART)
 188                 do_IRQ(AR71XX_MISC_IRQ_UART);
 189
 190         else if (pending & MISC_INT_DMA)
 191                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 192
 193         else if (pending & MISC_INT_PERFC)
 194                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 195
 196         else if (pending & MISC_INT_TIMER)
 197                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 198
 199         else if (pending & MISC_INT_OHCI)
 200                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 201
 202         else if (pending & MISC_INT_ERROR)
 203                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 204
 205         else if (pending & MISC_INT_GPIO)
 206                 ar71xx_gpio_irq_dispatch();
 207
 208         else if (pending & MISC_INT_WDOG)
 209                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 210
 211         else
 212                 spurious_interrupt();
 213 }
 214
 215 static void ar71xx_misc_irq_unmask(unsigned int irq)
 216 {
 217         irq -= AR71XX_MISC_IRQ_BASE;
 218         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 219                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 220
 221         /* flush write */
 222         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 223 }
 224
 225 static void ar71xx_misc_irq_mask(unsigned int irq)
 226 {
 227         irq -= AR71XX_MISC_IRQ_BASE;
 228         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 229                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 230
 231         /* flush write */
 232         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 233 }
 234
 235 struct irq_chip ar71xx_misc_irq_chip = {
 236         .name           = "AR71XX MISC",
 237         .unmask         = ar71xx_misc_irq_unmask,
 238         .mask           = ar71xx_misc_irq_mask,
 239         .mask_ack       = ar71xx_misc_irq_mask,
 240 };
 241
 242 static struct irqaction ar71xx_misc_irqaction = {
 243         .handler        = no_action,
 244         .name           = "cascade [AR71XX MISC]",
 245 };
 246
 247 static void __init ar71xx_misc_irq_init(void)
 248 {
 249         int i;
 250
 251         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 252         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 253
 254         for (i = AR71XX_MISC_IRQ_BASE;
 255              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 256                 irq_desc[i].status = IRQ_DISABLED;
 257                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 258                                          handle_level_irq);
 259         }
 260
 261         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 262 }
 263
 264 static void ar913x_wmac_irq_dispatch(void)
 265 {
 266         do_IRQ(AR71XX_CPU_IRQ_WMAC);
 267 }
 268
 269 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
 270
 271 asmlinkage void plat_irq_dispatch(void)
 272 {
 273         unsigned long pending;
 274
 275         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 276
 277         if (pending & STATUSF_IP7)
 278                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 279
 280         else if (pending & STATUSF_IP2)
 281                 ar71xx_ip2_irq_handler();
 282
 283         else if (pending & STATUSF_IP4)
 284                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 285
 286         else if (pending & STATUSF_IP5)
 287                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 288
 289         else if (pending & STATUSF_IP3)
 290                 do_IRQ(AR71XX_CPU_IRQ_USB);
 291
 292         else if (pending & STATUSF_IP6)
 293                 ar71xx_misc_irq_dispatch();
 294
 295         else
 296                 spurious_interrupt();
 297 }
 298
 299 void __init arch_init_irq(void)
 300 {
 301         mips_cpu_irq_init();
 302
 303         ar71xx_misc_irq_init();
 304
 305         switch (ar71xx_soc) {
 306         case AR71XX_SOC_AR7130:
 307         case AR71XX_SOC_AR7141:
 308         case AR71XX_SOC_AR7161:
 309         case AR71XX_SOC_AR7240:
 310 #ifdef CONFIG_PCI
 311                 ar71xx_pci_irq_init();
 312                 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
 313 #endif
 314                 break;
 315         case AR71XX_SOC_AR9130:
 316         case AR71XX_SOC_AR9132:
 317                 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
 318                 break;
 319         default:
 320                 BUG();
 321         }
 322
 323         ar71xx_gpio_irq_init();
 324 }