target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c

   1 /*
   2  * Wallys DR344 board support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  * Copyright (c) 2015 Philippe Duchein <wireless-dev@duchein.net>
   7  *
   8  * Permission to use, copy, modify, and/or distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  */
  21
  22 #include <linux/gpio.h>
  23 #include <linux/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/ath9k_platform.h>
  26 #include <linux/platform_data/phy-at803x.h>
  27
  28 #include <asm/mach-ath79/ar71xx_regs.h>
  29
  30 #include "common.h"
  31 #include "pci.h"
  32 #include "dev-ap9x-pci.h"
  33 #include "dev-gpio-buttons.h"
  34 #include "dev-eth.h"
  35 #include "dev-usb.h"
  36 #include "dev-leds-gpio.h"
  37 #include "dev-m25p80.h"
  38 #include "dev-spi.h"
  39 #include "dev-wmac.h"
  40 #include "machtypes.h"
  41
  42 #define DR344_GPIO_LED_SIG1             12
  43 #define DR344_GPIO_LED_SIG2             13
  44 #define DR344_GPIO_LED_SIG3             14
  45 #define DR344_GPIO_LED_SIG4             15
  46 #define DR344_GPIO_LED_STATUS           11
  47 #define DR344_GPIO_LED_LAN              17
  48 #define DR344_GPIO_EXTERNAL_LNA0        18
  49 #define DR344_GPIO_EXTERNAL_LNA1        19
  50
  51 #define DR344_GPIO_BTN_RESET            16
  52
  53 #define DR344_KEYS_POLL_INTERVAL        20      /* msecs */
  54 #define DR344_KEYS_DEBOUNCE_INTERVAL    (3 * DR344_KEYS_POLL_INTERVAL)
  55
  56 #define DR344_MAC0_OFFSET               0
  57 #define DR344_MAC1_OFFSET               8
  58 #define DR344_WMAC_CALDATA_OFFSET       0x1000
  59 #define DR344_PCIE_CALDATA_OFFSET       0x5000
  60
  61 static struct gpio_led dr344_leds_gpio[] __initdata = {
  62         {
  63                 .name           = "dr344:green:lan",
  64                 .gpio           = DR344_GPIO_LED_LAN,
  65                 .active_low     = 1,
  66         },
  67         {
  68                 .name           = "dr344:green:status",
  69                 .gpio           = DR344_GPIO_LED_STATUS,
  70                 .active_low     = 1,
  71         },
  72         {
  73                 .name           = "dr344:green:sig1",
  74                 .gpio           = DR344_GPIO_LED_SIG1,
  75                 .active_low     = 1,
  76         },
  77         {
  78                 .name           = "dr344:green:sig2",
  79                 .gpio           = DR344_GPIO_LED_SIG2,
  80                 .active_low     = 1,
  81         },
  82         {
  83                 .name           = "dr344:green:sig3",
  84                 .gpio           = DR344_GPIO_LED_SIG3,
  85                 .active_low     = 1,
  86         },
  87         {
  88                 .name           = "dr344:green:sig4",
  89                 .gpio           = DR344_GPIO_LED_SIG4,
  90                 .active_low     = 1,
  91         }
  92 };
  93
  94 static struct gpio_keys_button dr344_gpio_keys[] __initdata = {
  95         {
  96                 .desc           = "reset",
  97                 .type           = EV_KEY,
  98                 .code           = KEY_RESTART,
  99                 .debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL,
 100                 .gpio           = DR344_GPIO_BTN_RESET,
 101                 .active_low     = 1,
 102         },
 103 };
 104
 105 static struct at803x_platform_data dr344_at803x_data = {
 106         .disable_smarteee = 1,
 107         .enable_rgmii_rx_delay = 1,
 108         .enable_rgmii_tx_delay = 1,
 109 };
 110
 111 static struct mdio_board_info dr344_mdio0_info[] = {
 112         {
 113                 .bus_id = "ag71xx-mdio.0",
 114                 .phy_addr = 0,
 115                 .platform_data = &dr344_at803x_data,
 116         },
 117 };
 118
 119 static void __init dr344_setup(void)
 120 {
 121         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 122         u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
 123
 124         ath79_register_m25p80(NULL);
 125
 126         ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true);
 127         gpio_set_value(DR344_GPIO_LED_STATUS, 1);
 128         ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0);
 129
 130         ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
 131         gpio_set_value(DR344_GPIO_LED_LAN, 1);
 132         ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
 133
 134         ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
 135                                  dr344_leds_gpio);
 136         ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
 137                                         ARRAY_SIZE(dr344_gpio_keys),
 138                                         dr344_gpio_keys);
 139
 140         ath79_register_usb();
 141
 142         ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
 143
 144         ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
 145
 146         ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
 147
 148         ath79_register_pci();
 149
 150         mdiobus_register_board_info(dr344_mdio0_info,
 151                                         ARRAY_SIZE(dr344_mdio0_info));
 152
 153         ath79_register_mdio(1, 0x0);
 154         ath79_register_mdio(0, 0x0);
 155
 156         ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
 157         ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
 158
 159         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
 160                                    AR934X_ETH_CFG_SW_ONLY_MODE);
 161
 162         /* GMAC0 is connected to an AR8035 Gbps PHY */
 163         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 164         ath79_eth0_data.phy_mask = BIT(0);
 165         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 166         ath79_eth0_pll_data.pll_1000 = 0x02000000;
 167         ath79_eth0_pll_data.pll_100 = 0x0101;
 168         ath79_eth0_pll_data.pll_10 = 0x1313;
 169
 170         /* GMAC1 is connected to the internal switch */
 171         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 172         ath79_eth1_data.speed = SPEED_1000;
 173         ath79_eth1_data.duplex = DUPLEX_FULL;
 174
 175         ath79_register_eth(0);
 176         ath79_register_eth(1);
 177 }
 178
 179 MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup);