target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c

   1 /*
   2  * MR900 board support
   3  *
   4  * Copyright (c) 2012 Qualcomm Atheros
   5  * Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include <linux/platform_device.h>
  22 #include <linux/ar8216_platform.h>
  23 #include <linux/ath9k_platform.h>
  24
  25 #include <asm/mach-ath79/ar71xx_regs.h>
  26
  27 #include "common.h"
  28 #include "dev-ap9x-pci.h"
  29 #include "dev-gpio-buttons.h"
  30 #include "dev-eth.h"
  31 #include "dev-leds-gpio.h"
  32 #include "dev-m25p80.h"
  33 #include "dev-wmac.h"
  34 #include "machtypes.h"
  35 #include "pci.h"
  36
  37 #define MR900_GPIO_LED_LAN              12
  38 #define MR900_GPIO_LED_WLAN_2G          13
  39 #define MR900_GPIO_LED_STATUS_GREEN     19
  40 #define MR900_GPIO_LED_STATUS_RED       21
  41 #define MR900_GPIO_LED_POWER            22
  42 #define MR900_GPIO_LED_WLAN_5G          23
  43
  44 #define MR900_GPIO_BTN_RESET            17
  45
  46 #define MR900_KEYS_POLL_INTERVAL        20      /* msecs */
  47 #define MR900_KEYS_DEBOUNCE_INTERVAL    (3 * MR900_KEYS_POLL_INTERVAL)
  48
  49 #define MR900_MAC0_OFFSET               0
  50 #define MR900_WMAC_CALDATA_OFFSET       0x1000
  51 #define MR900_PCIE_CALDATA_OFFSET       0x5000
  52
  53 static struct gpio_led mr900_leds_gpio[] __initdata = {
  54         {
  55                 .name           = "mr900:blue:power",
  56                 .gpio           = MR900_GPIO_LED_POWER,
  57                 .active_low     = 1,
  58         },
  59         {
  60                 .name           = "mr900:blue:wan",
  61                 .gpio           = MR900_GPIO_LED_LAN,
  62                 .active_low     = 1,
  63         },
  64         {
  65                 .name           = "mr900:blue:wlan24",
  66                 .gpio           = MR900_GPIO_LED_WLAN_2G,
  67                 .active_low     = 1,
  68         },
  69         {
  70                 .name           = "mr900:blue:wlan58",
  71                 .gpio           = MR900_GPIO_LED_WLAN_5G,
  72                 .active_low     = 1,
  73         },
  74         {
  75                 .name           = "mr900:green:status",
  76                 .gpio           = MR900_GPIO_LED_STATUS_GREEN,
  77                 .active_low     = 1,
  78         },
  79         {
  80                 .name           = "mr900:red:status",
  81                 .gpio           = MR900_GPIO_LED_STATUS_RED,
  82                 .active_low     = 1,
  83         },
  84 };
  85
  86 static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
  87         {
  88                 .desc           = "Reset button",
  89                 .type           = EV_KEY,
  90                 .code           = KEY_RESTART,
  91                 .debounce_interval = MR900_KEYS_DEBOUNCE_INTERVAL,
  92                 .gpio           = MR900_GPIO_BTN_RESET,
  93                 .active_low     = 1,
  94         },
  95 };
  96
  97 static void __init mr900_setup(void)
  98 {
  99         u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
 100         u8 mac[6], pcie_mac[6];
 101         struct ath9k_platform_data *pdata;
 102
 103         ath79_eth0_pll_data.pll_1000 = 0xbe000101;
 104         ath79_eth0_pll_data.pll_100 = 0x80000101;
 105         ath79_eth0_pll_data.pll_10 = 0x80001313;
 106
 107         ath79_register_m25p80(NULL);
 108
 109         ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio),
 110                                  mr900_leds_gpio);
 111         ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL,
 112                                         ARRAY_SIZE(mr900_gpio_keys),
 113                                         mr900_gpio_keys);
 114
 115         ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1);
 116         ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac);
 117         ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16);
 118         ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac);
 119         pdata = ap9x_pci_get_wmac_data(0);
 120         if (!pdata) {
 121                 pr_err("mr900: unable to get address of wlan data\n");
 122                 return;
 123         }
 124         pdata->use_eeprom = true;
 125
 126         ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 127         ath79_register_mdio(0, 0x0);
 128
 129         ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
 130
 131         /* GMAC0 is connected to the RMGII interface */
 132         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 133         ath79_eth0_data.phy_mask = BIT(5);
 134         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 135
 136         ath79_register_eth(0);
 137 }
 138
 139 MIPS_MACHINE(ATH79_MACH_MR900, "MR900", "OpenMesh MR900", mr900_setup);
 140 MIPS_MACHINE(ATH79_MACH_MR900v2, "MR900v2", "OpenMesh MR900v2", mr900_setup);