move the trx parser out from the patch
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / mtd / wrt160nl_part.c
1 /*
2 * Copyright © 2009 Christian Daniel <cd@maintech.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 *
18 * TRX flash partition table.
19 * Based on ar7 map by Felix Fietkau <nbd@openwrt.org>
20 *
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/bootmem.h>
29 #include <linux/magic.h>
30
31 #define TRX_PARTS 6
32 #define TRX_MAGIC 0x30524448
33 #define TRX_MAX_OFFSET 3
34
35 struct trx_header {
36 uint32_t magic; /* "HDR0" */
37 uint32_t len; /* Length of file including header */
38 uint32_t crc32; /* 32-bit CRC from flag_version to end of file */
39 uint32_t flag_version; /* 0:15 flags, 16:31 version */
40 uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
41 };
42
43 #define IH_MAGIC 0x27051956 /* Image Magic Number */
44 #define IH_NMLEN 32 /* Image Name Length */
45
46 struct uimage_header {
47 uint32_t ih_magic; /* Image Header Magic Number */
48 uint32_t ih_hcrc; /* Image Header CRC Checksum */
49 uint32_t ih_time; /* Image Creation Timestamp */
50 uint32_t ih_size; /* Image Data Size */
51 uint32_t ih_load; /* Data» Load Address */
52 uint32_t ih_ep; /* Entry Point Address */
53 uint32_t ih_dcrc; /* Image Data CRC Checksum */
54 uint8_t ih_os; /* Operating System */
55 uint8_t ih_arch; /* CPU architecture */
56 uint8_t ih_type; /* Image Type */
57 uint8_t ih_comp; /* Compression Type */
58 uint8_t ih_name[IH_NMLEN]; /* Image Name */
59 };
60
61 static struct mtd_partition trx_parts[TRX_PARTS];
62
63 static int create_mtd_partitions(struct mtd_info *master,
64 struct mtd_partition **pparts,
65 unsigned long origin)
66 {
67 uint8_t buf[512];
68 int len;
69 struct trx_header* header;
70 struct uimage_header* uheader;
71 unsigned int kernel_len;
72
73 master->read(master, 4 * master->erasesize, sizeof(buf), &len, buf);
74 if(strncmp(buf, "NL16", 4) == 0) {
75 printk(KERN_INFO "TRX on WRT160NL detected\n");
76
77 header = (struct trx_header*)(buf + 32);
78
79 if(le32_to_cpu(header->magic) != TRX_MAGIC) {
80 printk(KERN_WARNING "TRX messed up\n");
81 return 0;
82 }
83
84 uheader = (struct uimage_header*)(buf + 60);
85
86 if(uheader->ih_magic != IH_MAGIC) {
87 printk(KERN_WARNING "uImage messed up\n");
88 return 0;
89 }
90
91 kernel_len = uheader->ih_size / master->erasesize;
92 if(uheader->ih_size % master->erasesize)
93 kernel_len++;
94 kernel_len++;
95 kernel_len *= master->erasesize;
96
97 trx_parts[0].name = "u-boot";
98 trx_parts[0].offset = 0;
99 trx_parts[0].size = 4 * master->erasesize;
100 trx_parts[0].mask_flags = MTD_WRITEABLE;
101
102 trx_parts[1].name = "kernel";
103 trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
104 trx_parts[1].size = kernel_len;
105 trx_parts[1].mask_flags = 0;
106
107 trx_parts[2].name = "rootfs";
108 trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
109 trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size;
110 trx_parts[2].mask_flags = 0;
111
112 trx_parts[3].name = "nvram";
113 trx_parts[3].offset = master->size - 2 * master->erasesize;
114 trx_parts[3].size = master->erasesize;
115 trx_parts[3].mask_flags = 0;
116
117 trx_parts[4].name = "ART";
118 trx_parts[4].offset = master->size - master->erasesize;
119 trx_parts[4].size = master->erasesize;
120 trx_parts[4].mask_flags = MTD_WRITEABLE;
121
122 trx_parts[5].name = "firmware";
123 trx_parts[5].offset = 4 * master->erasesize;
124 trx_parts[5].size = master->size - 6 * master->erasesize;
125 trx_parts[5].mask_flags = 0;
126
127 *pparts = trx_parts;
128
129 return TRX_PARTS;
130 } else {
131 return 0;
132 }
133 }
134
135 static struct mtd_part_parser trx_parser = {
136 .owner = THIS_MODULE,
137 .parse_fn = create_mtd_partitions,
138 .name = "wrt160nl",
139 };
140
141 static int __init trx_parser_init(void)
142 {
143 return register_mtd_parser(&trx_parser);
144 }
145
146 module_init(trx_parser_init);
147
148 MODULE_LICENSE("GPL");
149 MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");