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[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
40
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
57
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
61
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
64
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_RESERVED BIT(19)
70 #define AR7240_AT_CTRL_ARP_EN BIT(20)
71
72 #define AR7240_REG_TAG_PRIORITY 0x70
73
74 #define AR7240_REG_SERVICE_TAG 0x74
75 #define AR7240_SERVICE_TAG_M BITM(16)
76
77 #define AR7240_REG_CPU_PORT 0x78
78 #define AR7240_MIRROR_PORT_S 4
79 #define AR7240_CPU_PORT_EN BIT(8)
80
81 #define AR7240_REG_MIB_FUNCTION0 0x80
82 #define AR7240_MIB_TIMER_M BITM(16)
83 #define AR7240_MIB_AT_HALF_EN BIT(16)
84 #define AR7240_MIB_BUSY BIT(17)
85 #define AR7240_MIB_FUNC_S 24
86 #define AR7240_MIB_FUNC_NO_OP 0x0
87 #define AR7240_MIB_FUNC_FLUSH 0x1
88 #define AR7240_MIB_FUNC_CAPTURE 0x3
89
90 #define AR7240_REG_MDIO_CTRL 0x98
91 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
92 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
93 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
94 #define AR7240_MDIO_CTRL_CMD_WRITE 0
95 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
96 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
97 #define AR7240_MDIO_CTRL_BUSY BIT(31)
98
99 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100
101 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
102 #define AR7240_PORT_STATUS_SPEED_S 0
103 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
104 #define AR7240_PORT_STATUS_SPEED_10 0
105 #define AR7240_PORT_STATUS_SPEED_100 1
106 #define AR7240_PORT_STATUS_SPEED_1000 2
107 #define AR7240_PORT_STATUS_TXMAC BIT(2)
108 #define AR7240_PORT_STATUS_RXMAC BIT(3)
109 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
110 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
111 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
112 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
113 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
114 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115
116 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
117 #define AR7240_PORT_CTRL_STATE_M BITM(3)
118 #define AR7240_PORT_CTRL_STATE_DISABLED 0
119 #define AR7240_PORT_CTRL_STATE_BLOCK 1
120 #define AR7240_PORT_CTRL_STATE_LISTEN 2
121 #define AR7240_PORT_CTRL_STATE_LEARN 3
122 #define AR7240_PORT_CTRL_STATE_FORWARD 4
123 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
124 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
125 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
126 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
127 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
128 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
129 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
130 #define AR7240_PORT_CTRL_HEADER BIT(11)
131 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
132 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
133 #define AR7240_PORT_CTRL_LEARN BIT(14)
134 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
135 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
136 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137
138 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139
140 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
141 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
142 #define AR7240_PORT_VLAN_MODE_S 30
143 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
144 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
145 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
146 #define AR7240_PORT_VLAN_MODE_SECURE 3
147
148
149 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150
151 #define AR7240_STATS_RXBROAD 0x00
152 #define AR7240_STATS_RXPAUSE 0x04
153 #define AR7240_STATS_RXMULTI 0x08
154 #define AR7240_STATS_RXFCSERR 0x0c
155 #define AR7240_STATS_RXALIGNERR 0x10
156 #define AR7240_STATS_RXRUNT 0x14
157 #define AR7240_STATS_RXFRAGMENT 0x18
158 #define AR7240_STATS_RX64BYTE 0x1c
159 #define AR7240_STATS_RX128BYTE 0x20
160 #define AR7240_STATS_RX256BYTE 0x24
161 #define AR7240_STATS_RX512BYTE 0x28
162 #define AR7240_STATS_RX1024BYTE 0x2c
163 #define AR7240_STATS_RX1518BYTE 0x30
164 #define AR7240_STATS_RXMAXBYTE 0x34
165 #define AR7240_STATS_RXTOOLONG 0x38
166 #define AR7240_STATS_RXGOODBYTE 0x3c
167 #define AR7240_STATS_RXBADBYTE 0x44
168 #define AR7240_STATS_RXOVERFLOW 0x4c
169 #define AR7240_STATS_FILTERED 0x50
170 #define AR7240_STATS_TXBROAD 0x54
171 #define AR7240_STATS_TXPAUSE 0x58
172 #define AR7240_STATS_TXMULTI 0x5c
173 #define AR7240_STATS_TXUNDERRUN 0x60
174 #define AR7240_STATS_TX64BYTE 0x64
175 #define AR7240_STATS_TX128BYTE 0x68
176 #define AR7240_STATS_TX256BYTE 0x6c
177 #define AR7240_STATS_TX512BYTE 0x70
178 #define AR7240_STATS_TX1024BYTE 0x74
179 #define AR7240_STATS_TX1518BYTE 0x78
180 #define AR7240_STATS_TXMAXBYTE 0x7c
181 #define AR7240_STATS_TXOVERSIZE 0x80
182 #define AR7240_STATS_TXBYTE 0x84
183 #define AR7240_STATS_TXCOLLISION 0x8c
184 #define AR7240_STATS_TXABORTCOL 0x90
185 #define AR7240_STATS_TXMULTICOL 0x94
186 #define AR7240_STATS_TXSINGLECOL 0x98
187 #define AR7240_STATS_TXEXCDEFER 0x9c
188 #define AR7240_STATS_TXDEFER 0xa0
189 #define AR7240_STATS_TXLATECOL 0xa4
190
191 #define AR7240_PORT_CPU 0
192 #define AR7240_NUM_PORTS 6
193 #define AR7240_NUM_PHYS 5
194
195 #define AR7240_PHY_ID1 0x004d
196 #define AR7240_PHY_ID2 0xd041
197
198 #define AR934X_PHY_ID1 0x004d
199 #define AR934X_PHY_ID2 0xd042
200
201 #define AR7240_MAX_VLANS 16
202
203 #define AR934X_REG_OPER_MODE0 0x04
204 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
205 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
206
207 #define AR934X_REG_OPER_MODE1 0x08
208 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
209
210 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
211
212 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
213 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
214 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
215 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
216 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
217 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
218 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
219 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
220 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
221
222 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
223 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
224 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
225 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
226 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
227 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
228 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
229
230 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
231
232 struct ar7240sw {
233 struct mii_bus *mii_bus;
234 struct ag71xx_switch_platform_data *swdata;
235 struct switch_dev swdev;
236 int num_ports;
237 u8 ver;
238 bool vlan;
239 u16 vlan_id[AR7240_MAX_VLANS];
240 u8 vlan_table[AR7240_MAX_VLANS];
241 u8 vlan_tagged;
242 u16 pvid[AR7240_NUM_PORTS];
243 char buf[80];
244 };
245
246 struct ar7240sw_hw_stat {
247 char string[ETH_GSTRING_LEN];
248 int sizeof_stat;
249 int reg;
250 };
251
252 static DEFINE_MUTEX(reg_mutex);
253
254 static inline int sw_is_ar7240(struct ar7240sw *as)
255 {
256 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
257 }
258
259 static inline int sw_is_ar934x(struct ar7240sw *as)
260 {
261 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
262 }
263
264 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
265 {
266 return BIT(port);
267 }
268
269 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
270 {
271 return BIT(as->swdev.ports) - 1;
272 }
273
274 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
275 {
276 return ar7240sw_port_mask_all(as) & ~BIT(port);
277 }
278
279 static inline u16 mk_phy_addr(u32 reg)
280 {
281 return 0x17 & ((reg >> 4) | 0x10);
282 }
283
284 static inline u16 mk_phy_reg(u32 reg)
285 {
286 return (reg << 1) & 0x1e;
287 }
288
289 static inline u16 mk_high_addr(u32 reg)
290 {
291 return (reg >> 7) & 0x1ff;
292 }
293
294 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
295 {
296 unsigned long flags;
297 u16 phy_addr;
298 u16 phy_reg;
299 u32 hi, lo;
300
301 reg = (reg & 0xfffffffc) >> 2;
302 phy_addr = mk_phy_addr(reg);
303 phy_reg = mk_phy_reg(reg);
304
305 local_irq_save(flags);
306 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
307 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
308 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
309 local_irq_restore(flags);
310
311 return (hi << 16) | lo;
312 }
313
314 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
315 {
316 unsigned long flags;
317 u16 phy_addr;
318 u16 phy_reg;
319
320 reg = (reg & 0xfffffffc) >> 2;
321 phy_addr = mk_phy_addr(reg);
322 phy_reg = mk_phy_reg(reg);
323
324 local_irq_save(flags);
325 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
326 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
327 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
328 local_irq_restore(flags);
329 }
330
331 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
332 {
333 u32 ret;
334
335 mutex_lock(&reg_mutex);
336 ret = __ar7240sw_reg_read(mii, reg_addr);
337 mutex_unlock(&reg_mutex);
338
339 return ret;
340 }
341
342 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
343 {
344 mutex_lock(&reg_mutex);
345 __ar7240sw_reg_write(mii, reg_addr, reg_val);
346 mutex_unlock(&reg_mutex);
347 }
348
349 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
350 {
351 u32 t;
352
353 mutex_lock(&reg_mutex);
354 t = __ar7240sw_reg_read(mii, reg);
355 t &= ~mask;
356 t |= val;
357 __ar7240sw_reg_write(mii, reg, t);
358 mutex_unlock(&reg_mutex);
359
360 return t;
361 }
362
363 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
364 {
365 u32 t;
366
367 mutex_lock(&reg_mutex);
368 t = __ar7240sw_reg_read(mii, reg);
369 t |= val;
370 __ar7240sw_reg_write(mii, reg, t);
371 mutex_unlock(&reg_mutex);
372 }
373
374 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
375 unsigned timeout)
376 {
377 int i;
378
379 for (i = 0; i < timeout; i++) {
380 u32 t;
381
382 t = __ar7240sw_reg_read(mii, reg);
383 if ((t & mask) == val)
384 return 0;
385
386 msleep(1);
387 }
388
389 return -ETIMEDOUT;
390 }
391
392 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
393 unsigned timeout)
394 {
395 int ret;
396
397 mutex_lock(&reg_mutex);
398 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
399 mutex_unlock(&reg_mutex);
400 return ret;
401 }
402
403 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
404 unsigned reg_addr)
405 {
406 u32 t, val = 0xffff;
407 int err;
408
409 if (phy_addr >= AR7240_NUM_PHYS)
410 return 0xffff;
411
412 mutex_lock(&reg_mutex);
413 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
414 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
415 AR7240_MDIO_CTRL_MASTER_EN |
416 AR7240_MDIO_CTRL_BUSY |
417 AR7240_MDIO_CTRL_CMD_READ;
418
419 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
420 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
421 AR7240_MDIO_CTRL_BUSY, 0, 5);
422 if (!err)
423 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
424 mutex_unlock(&reg_mutex);
425
426 return val & AR7240_MDIO_CTRL_DATA_M;
427 }
428
429 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
430 unsigned reg_addr, u16 reg_val)
431 {
432 u32 t;
433 int ret;
434
435 if (phy_addr >= AR7240_NUM_PHYS)
436 return -EINVAL;
437
438 mutex_lock(&reg_mutex);
439 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
440 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
441 AR7240_MDIO_CTRL_MASTER_EN |
442 AR7240_MDIO_CTRL_BUSY |
443 AR7240_MDIO_CTRL_CMD_WRITE |
444 reg_val;
445
446 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
447 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
448 AR7240_MDIO_CTRL_BUSY, 0, 5);
449 mutex_unlock(&reg_mutex);
450
451 return ret;
452 }
453
454 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
455 {
456 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
457 AR7240_PORT_CTRL_STATE_DISABLED);
458 }
459
460 static void ar7240sw_setup(struct ar7240sw *as)
461 {
462 struct mii_bus *mii = as->mii_bus;
463
464 /* Enable CPU port, and disable mirror port */
465 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
466 AR7240_CPU_PORT_EN |
467 (15 << AR7240_MIRROR_PORT_S));
468
469 /* Setup TAG priority mapping */
470 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
471
472 /* Enable ARP frame acknowledge, aging, MAC replacing */
473 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
474 AR7240_AT_CTRL_RESERVED |
475 0x2b /* 5 min age time */ |
476 AR7240_AT_CTRL_AGE_EN |
477 AR7240_AT_CTRL_ARP_EN |
478 AR7240_AT_CTRL_LEARN_CHANGE);
479
480 /* Enable Broadcast frames transmitted to the CPU */
481 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
482 AR7240_FLOOD_MASK_BROAD_TO_CPU);
483
484 /* setup MTU */
485 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
486 1536);
487
488 /* setup Service TAG */
489 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
490 }
491
492 static int ar7240sw_reset(struct ar7240sw *as)
493 {
494 struct mii_bus *mii = as->mii_bus;
495 int ret;
496 int i;
497
498 /* Set all ports to disabled state. */
499 for (i = 0; i < AR7240_NUM_PORTS; i++)
500 ar7240sw_disable_port(as, i);
501
502 /* Wait for transmit queues to drain. */
503 msleep(2);
504
505 /* Reset the switch. */
506 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
507 AR7240_MASK_CTRL_SOFT_RESET);
508
509 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
510 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
511
512 ar7240sw_setup(as);
513 return ret;
514 }
515
516 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
517 {
518 struct mii_bus *mii = as->mii_bus;
519 u32 ctrl;
520 u32 vid, mode;
521
522 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
523 AR7240_PORT_CTRL_SINGLE_VLAN;
524
525 if (port == AR7240_PORT_CPU) {
526 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
527 AR7240_PORT_STATUS_SPEED_1000 |
528 AR7240_PORT_STATUS_TXFLOW |
529 AR7240_PORT_STATUS_RXFLOW |
530 AR7240_PORT_STATUS_TXMAC |
531 AR7240_PORT_STATUS_RXMAC |
532 AR7240_PORT_STATUS_DUPLEX);
533 } else {
534 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
535 AR7240_PORT_STATUS_LINK_AUTO);
536 }
537
538 /* Set the default VID for this port */
539 if (as->vlan) {
540 vid = as->vlan_id[as->pvid[port]];
541 mode = AR7240_PORT_VLAN_MODE_SECURE;
542 } else {
543 vid = port;
544 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
545 }
546
547 if (as->vlan && (as->vlan_tagged & BIT(port))) {
548 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
549 AR7240_PORT_CTRL_VLAN_MODE_S;
550 } else {
551 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
552 AR7240_PORT_CTRL_VLAN_MODE_S;
553 }
554
555 if (!portmask) {
556 if (port == AR7240_PORT_CPU)
557 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
558 else
559 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
560 }
561
562 /* allow the port to talk to all other ports, but exclude its
563 * own ID to prevent frames from being reflected back to the
564 * port that they came from */
565 portmask &= ar7240sw_port_mask_but(as, port);
566
567 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
568 if (sw_is_ar934x(as)) {
569 u32 vlan1, vlan2;
570
571 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
572 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
573 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
574 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
575 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
576 } else {
577 u32 vlan;
578
579 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
580 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
581
582 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
583 }
584 }
585
586 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
587 {
588 struct mii_bus *mii = as->mii_bus;
589 u32 t;
590
591 t = (addr[4] << 8) | addr[5];
592 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
593
594 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
595 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
596
597 return 0;
598 }
599
600 static int
601 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
602 struct switch_val *val)
603 {
604 struct ar7240sw *as = sw_to_ar7240(dev);
605 as->vlan_id[val->port_vlan] = val->value.i;
606 return 0;
607 }
608
609 static int
610 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
611 struct switch_val *val)
612 {
613 struct ar7240sw *as = sw_to_ar7240(dev);
614 val->value.i = as->vlan_id[val->port_vlan];
615 return 0;
616 }
617
618 static int
619 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
620 {
621 struct ar7240sw *as = sw_to_ar7240(dev);
622
623 /* make sure no invalid PVIDs get set */
624
625 if (vlan >= dev->vlans)
626 return -EINVAL;
627
628 as->pvid[port] = vlan;
629 return 0;
630 }
631
632 static int
633 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
634 {
635 struct ar7240sw *as = sw_to_ar7240(dev);
636 *vlan = as->pvid[port];
637 return 0;
638 }
639
640 static int
641 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
642 {
643 struct ar7240sw *as = sw_to_ar7240(dev);
644 u8 ports = as->vlan_table[val->port_vlan];
645 int i;
646
647 val->len = 0;
648 for (i = 0; i < as->swdev.ports; i++) {
649 struct switch_port *p;
650
651 if (!(ports & (1 << i)))
652 continue;
653
654 p = &val->value.ports[val->len++];
655 p->id = i;
656 if (as->vlan_tagged & (1 << i))
657 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
658 else
659 p->flags = 0;
660 }
661 return 0;
662 }
663
664 static int
665 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
666 {
667 struct ar7240sw *as = sw_to_ar7240(dev);
668 u8 *vt = &as->vlan_table[val->port_vlan];
669 int i, j;
670
671 *vt = 0;
672 for (i = 0; i < val->len; i++) {
673 struct switch_port *p = &val->value.ports[i];
674
675 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
676 as->vlan_tagged |= (1 << p->id);
677 else {
678 as->vlan_tagged &= ~(1 << p->id);
679 as->pvid[p->id] = val->port_vlan;
680
681 /* make sure that an untagged port does not
682 * appear in other vlans */
683 for (j = 0; j < AR7240_MAX_VLANS; j++) {
684 if (j == val->port_vlan)
685 continue;
686 as->vlan_table[j] &= ~(1 << p->id);
687 }
688 }
689
690 *vt |= 1 << p->id;
691 }
692 return 0;
693 }
694
695 static int
696 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
697 struct switch_val *val)
698 {
699 struct ar7240sw *as = sw_to_ar7240(dev);
700 as->vlan = !!val->value.i;
701 return 0;
702 }
703
704 static int
705 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
706 struct switch_val *val)
707 {
708 struct ar7240sw *as = sw_to_ar7240(dev);
709 val->value.i = as->vlan;
710 return 0;
711 }
712
713 static const char *
714 ar7240_speed_str(u32 status)
715 {
716 u32 speed;
717
718 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
719 AR7240_PORT_STATUS_SPEED_M;
720 switch (speed) {
721 case AR7240_PORT_STATUS_SPEED_10:
722 return "10baseT";
723 case AR7240_PORT_STATUS_SPEED_100:
724 return "100baseT";
725 case AR7240_PORT_STATUS_SPEED_1000:
726 return "1000baseT";
727 }
728
729 return "unknown";
730 }
731
732 static int
733 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
734 struct switch_val *val)
735 {
736 struct ar7240sw *as = sw_to_ar7240(dev);
737 struct mii_bus *mii = as->mii_bus;
738 u32 len;
739 u32 status;
740 int port;
741
742 port = val->port_vlan;
743
744 memset(as->buf, '\0', sizeof(as->buf));
745 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
746
747 if (status & AR7240_PORT_STATUS_LINK_UP) {
748 len = snprintf(as->buf, sizeof(as->buf),
749 "port:%d link:up speed:%s %s-duplex %s%s%s",
750 port,
751 ar7240_speed_str(status),
752 (status & AR7240_PORT_STATUS_DUPLEX) ?
753 "full" : "half",
754 (status & AR7240_PORT_STATUS_TXFLOW) ?
755 "txflow ": "",
756 (status & AR7240_PORT_STATUS_RXFLOW) ?
757 "rxflow " : "",
758 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
759 "auto ": "");
760 } else {
761 len = snprintf(as->buf, sizeof(as->buf),
762 "port:%d link:down", port);
763 }
764
765 val->value.s = as->buf;
766 val->len = len;
767
768 return 0;
769 }
770
771 static void
772 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
773 {
774 struct mii_bus *mii = as->mii_bus;
775
776 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
777 return;
778
779 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
780 val &= AR7240_VTUDATA_MEMBER;
781 val |= AR7240_VTUDATA_VALID;
782 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
783 }
784 op |= AR7240_VTU_ACTIVE;
785 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
786 }
787
788 static int
789 ar7240_hw_apply(struct switch_dev *dev)
790 {
791 struct ar7240sw *as = sw_to_ar7240(dev);
792 u8 portmask[AR7240_NUM_PORTS];
793 int i, j;
794
795 /* flush all vlan translation unit entries */
796 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
797
798 memset(portmask, 0, sizeof(portmask));
799 if (as->vlan) {
800 /* calculate the port destination masks and load vlans
801 * into the vlan translation unit */
802 for (j = 0; j < AR7240_MAX_VLANS; j++) {
803 u8 vp = as->vlan_table[j];
804
805 if (!vp)
806 continue;
807
808 for (i = 0; i < as->swdev.ports; i++) {
809 u8 mask = (1 << i);
810 if (vp & mask)
811 portmask[i] |= vp & ~mask;
812 }
813
814 ar7240_vtu_op(as,
815 AR7240_VTU_OP_LOAD |
816 (as->vlan_id[j] << AR7240_VTU_VID_S),
817 as->vlan_table[j]);
818 }
819 } else {
820 /* vlan disabled:
821 * isolate all ports, but connect them to the cpu port */
822 for (i = 0; i < as->swdev.ports; i++) {
823 if (i == AR7240_PORT_CPU)
824 continue;
825
826 portmask[i] = 1 << AR7240_PORT_CPU;
827 portmask[AR7240_PORT_CPU] |= (1 << i);
828 }
829 }
830
831 /* update the port destination mask registers and tag settings */
832 for (i = 0; i < as->swdev.ports; i++)
833 ar7240sw_setup_port(as, i, portmask[i]);
834
835 return 0;
836 }
837
838 static int
839 ar7240_reset_switch(struct switch_dev *dev)
840 {
841 struct ar7240sw *as = sw_to_ar7240(dev);
842 ar7240sw_reset(as);
843 return 0;
844 }
845
846 static struct switch_attr ar7240_globals[] = {
847 {
848 .type = SWITCH_TYPE_INT,
849 .name = "enable_vlan",
850 .description = "Enable VLAN mode",
851 .set = ar7240_set_vlan,
852 .get = ar7240_get_vlan,
853 .max = 1
854 },
855 };
856
857 static struct switch_attr ar7240_port[] = {
858 {
859 .type = SWITCH_TYPE_STRING,
860 .name = "link",
861 .description = "Get port link information",
862 .max = 1,
863 .set = NULL,
864 .get = ar7240_port_get_link,
865 },
866 };
867
868 static struct switch_attr ar7240_vlan[] = {
869 {
870 .type = SWITCH_TYPE_INT,
871 .name = "vid",
872 .description = "VLAN ID",
873 .set = ar7240_set_vid,
874 .get = ar7240_get_vid,
875 .max = 4094,
876 },
877 };
878
879 static const struct switch_dev_ops ar7240_ops = {
880 .attr_global = {
881 .attr = ar7240_globals,
882 .n_attr = ARRAY_SIZE(ar7240_globals),
883 },
884 .attr_port = {
885 .attr = ar7240_port,
886 .n_attr = ARRAY_SIZE(ar7240_port),
887 },
888 .attr_vlan = {
889 .attr = ar7240_vlan,
890 .n_attr = ARRAY_SIZE(ar7240_vlan),
891 },
892 .get_port_pvid = ar7240_get_pvid,
893 .set_port_pvid = ar7240_set_pvid,
894 .get_vlan_ports = ar7240_get_ports,
895 .set_vlan_ports = ar7240_set_ports,
896 .apply_config = ar7240_hw_apply,
897 .reset_switch = ar7240_reset_switch,
898 };
899
900 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
901 {
902 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
903 struct mii_bus *mii = ag->mii_bus;
904 struct ar7240sw *as;
905 struct switch_dev *swdev;
906 u32 ctrl;
907 u16 phy_id1;
908 u16 phy_id2;
909 int i;
910
911 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
912 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
913 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
914 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
915 pr_err("%s: unknown phy id '%04x:%04x'\n",
916 ag->dev->name, phy_id1, phy_id2);
917 return NULL;
918 }
919
920 as = kzalloc(sizeof(*as), GFP_KERNEL);
921 if (!as)
922 return NULL;
923
924 as->mii_bus = mii;
925 as->swdata = pdata->switch_data;
926
927 swdev = &as->swdev;
928
929 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
930 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
931 AR7240_MASK_CTRL_VERSION_M;
932
933 if (sw_is_ar7240(as)) {
934 swdev->name = "AR7240/AR9330 built-in switch";
935 } else if (sw_is_ar934x(as)) {
936 swdev->name = "AR934X built-in switch";
937
938 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
939 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
940 AR934X_OPER_MODE0_MAC_GMII_EN);
941 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
942 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
943 AR934X_OPER_MODE0_PHY_MII_EN);
944 } else {
945 pr_err("%s: invalid PHY interface mode\n",
946 ag->dev->name);
947 goto err_free;
948 }
949
950 if (as->swdata->phy4_mii_en)
951 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
952 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
953 } else {
954 pr_err("%s: unsupported chip, ctrl=%08x\n",
955 ag->dev->name, ctrl);
956 goto err_free;
957 }
958
959 swdev->ports = AR7240_NUM_PORTS - 1;
960 swdev->cpu_port = AR7240_PORT_CPU;
961 swdev->vlans = AR7240_MAX_VLANS;
962 swdev->ops = &ar7240_ops;
963
964 if (register_switch(&as->swdev, ag->dev) < 0)
965 goto err_free;
966
967 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
968
969 /* initialize defaults */
970 for (i = 0; i < AR7240_MAX_VLANS; i++)
971 as->vlan_id[i] = i;
972
973 as->vlan_table[0] = ar7240sw_port_mask_all(as);
974
975 return as;
976
977 err_free:
978 kfree(as);
979 return NULL;
980 }
981
982 static void link_function(struct work_struct *work) {
983 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
984 unsigned long flags;
985 int i;
986 int status = 0;
987
988 for (i = 0; i < 4; i++) {
989 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
990 if(link & BMSR_LSTATUS) {
991 status = 1;
992 break;
993 }
994 }
995
996 spin_lock_irqsave(&ag->lock, flags);
997 if(status != ag->link) {
998 ag->link = status;
999 ag71xx_link_adjust(ag);
1000 }
1001 spin_unlock_irqrestore(&ag->lock, flags);
1002
1003 schedule_delayed_work(&ag->link_work, HZ / 2);
1004 }
1005
1006 void ag71xx_ar7240_start(struct ag71xx *ag)
1007 {
1008 struct ar7240sw *as = ag->phy_priv;
1009
1010 ar7240sw_reset(as);
1011
1012 ag->speed = SPEED_1000;
1013 ag->duplex = 1;
1014
1015 ar7240_set_addr(as, ag->dev->dev_addr);
1016 ar7240_hw_apply(&as->swdev);
1017
1018 schedule_delayed_work(&ag->link_work, HZ / 10);
1019 }
1020
1021 void ag71xx_ar7240_stop(struct ag71xx *ag)
1022 {
1023 cancel_delayed_work_sync(&ag->link_work);
1024 }
1025
1026 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
1027 {
1028 struct ar7240sw *as;
1029
1030 as = ar7240_probe(ag);
1031 if (!as)
1032 return -ENODEV;
1033
1034 ag->phy_priv = as;
1035 ar7240sw_reset(as);
1036
1037 INIT_DELAYED_WORK(&ag->link_work, link_function);
1038
1039 return 0;
1040 }
1041
1042 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1043 {
1044 struct ar7240sw *as = ag->phy_priv;
1045
1046 if (!as)
1047 return;
1048
1049 unregister_switch(&as->swdev);
1050 kfree(as);
1051 ag->phy_priv = NULL;
1052 }
OpenWrt Source Repository