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[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33
34 #include <linux/bitops.h>
35
36 #include <asm/mach-ath79/ar71xx_regs.h>
37 #include <asm/mach-ath79/ath79.h>
38 #include <asm/mach-ath79/ag71xx_platform.h>
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.35"
42
43 #define AG71XX_OOM_REFILL (1 + HZ/10)
44
45 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
46 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
47 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
48
49 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
50 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
51
52 #define AG71XX_TX_MTU_LEN 1540
53
54 #define AG71XX_TX_RING_SPLIT 512
55 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
56 AG71XX_TX_RING_SPLIT)
57 #define AG71XX_TX_RING_SIZE_DEFAULT 128
58 #define AG71XX_RX_RING_SIZE_DEFAULT 256
59
60 #define AG71XX_TX_RING_SIZE_MAX 128
61 #define AG71XX_RX_RING_SIZE_MAX 256
62
63 #ifdef CONFIG_AG71XX_DEBUG
64 #define DBG(fmt, args...) pr_debug(fmt, ## args)
65 #else
66 #define DBG(fmt, args...) do {} while (0)
67 #endif
68
69 #define ag71xx_assert(_cond) \
70 do { \
71 if (_cond) \
72 break; \
73 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
74 BUG(); \
75 } while (0)
76
77 struct ag71xx_desc {
78 u32 data;
79 u32 ctrl;
80 #define DESC_EMPTY BIT(31)
81 #define DESC_MORE BIT(24)
82 #define DESC_PKTLEN_M 0xfff
83 u32 next;
84 u32 pad;
85 } __attribute__((aligned(4)));
86
87 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
88 L1_CACHE_BYTES)
89
90 struct ag71xx_buf {
91 union {
92 struct sk_buff *skb;
93 void *rx_buf;
94 };
95 union {
96 dma_addr_t dma_addr;
97 unsigned long timestamp;
98 };
99 unsigned int len;
100 };
101
102 struct ag71xx_ring {
103 struct ag71xx_buf *buf;
104 u8 *descs_cpu;
105 dma_addr_t descs_dma;
106 u16 desc_split;
107 u16 order;
108 unsigned int curr;
109 unsigned int dirty;
110 };
111
112 struct ag71xx_mdio {
113 struct mii_bus *mii_bus;
114 int mii_irq[PHY_MAX_ADDR];
115 void __iomem *mdio_base;
116 struct ag71xx_mdio_platform_data *pdata;
117 };
118
119 struct ag71xx_int_stats {
120 unsigned long rx_pr;
121 unsigned long rx_be;
122 unsigned long rx_of;
123 unsigned long tx_ps;
124 unsigned long tx_be;
125 unsigned long tx_ur;
126 unsigned long total;
127 };
128
129 struct ag71xx_napi_stats {
130 unsigned long napi_calls;
131 unsigned long rx_count;
132 unsigned long rx_packets;
133 unsigned long rx_packets_max;
134 unsigned long tx_count;
135 unsigned long tx_packets;
136 unsigned long tx_packets_max;
137
138 unsigned long rx[NAPI_POLL_WEIGHT + 1];
139 unsigned long tx[NAPI_POLL_WEIGHT + 1];
140 };
141
142 struct ag71xx_debug {
143 struct dentry *debugfs_dir;
144
145 struct ag71xx_int_stats int_stats;
146 struct ag71xx_napi_stats napi_stats;
147 };
148
149 struct ag71xx {
150 void __iomem *mac_base;
151
152 spinlock_t lock;
153 struct platform_device *pdev;
154 struct net_device *dev;
155 struct napi_struct napi;
156 u32 msg_enable;
157
158 struct ag71xx_desc *stop_desc;
159 dma_addr_t stop_desc_dma;
160
161 struct ag71xx_ring rx_ring;
162 struct ag71xx_ring tx_ring;
163
164 struct mii_bus *mii_bus;
165 struct phy_device *phy_dev;
166 void *phy_priv;
167
168 unsigned int link;
169 unsigned int speed;
170 int duplex;
171
172 unsigned int max_frame_len;
173 unsigned int desc_pktlen_mask;
174 unsigned int rx_buf_size;
175
176 struct delayed_work restart_work;
177 struct delayed_work link_work;
178 struct timer_list oom_timer;
179
180 #ifdef CONFIG_AG71XX_DEBUG_FS
181 struct ag71xx_debug debug;
182 #endif
183 };
184
185 extern struct ethtool_ops ag71xx_ethtool_ops;
186 void ag71xx_link_adjust(struct ag71xx *ag);
187
188 int ag71xx_mdio_driver_init(void) __init;
189 void ag71xx_mdio_driver_exit(void);
190
191 int ag71xx_phy_connect(struct ag71xx *ag);
192 void ag71xx_phy_disconnect(struct ag71xx *ag);
193 void ag71xx_phy_start(struct ag71xx *ag);
194 void ag71xx_phy_stop(struct ag71xx *ag);
195
196 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
197 {
198 return ag->pdev->dev.platform_data;
199 }
200
201 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
202 {
203 return (desc->ctrl & DESC_EMPTY) != 0;
204 }
205
206 static inline struct ag71xx_desc *
207 ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
208 {
209 return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];
210 }
211
212 static inline int
213 ag71xx_ring_size_order(int size)
214 {
215 return fls(size - 1);
216 }
217
218 /* Register offsets */
219 #define AG71XX_REG_MAC_CFG1 0x0000
220 #define AG71XX_REG_MAC_CFG2 0x0004
221 #define AG71XX_REG_MAC_IPG 0x0008
222 #define AG71XX_REG_MAC_HDX 0x000c
223 #define AG71XX_REG_MAC_MFL 0x0010
224 #define AG71XX_REG_MII_CFG 0x0020
225 #define AG71XX_REG_MII_CMD 0x0024
226 #define AG71XX_REG_MII_ADDR 0x0028
227 #define AG71XX_REG_MII_CTRL 0x002c
228 #define AG71XX_REG_MII_STATUS 0x0030
229 #define AG71XX_REG_MII_IND 0x0034
230 #define AG71XX_REG_MAC_IFCTL 0x0038
231 #define AG71XX_REG_MAC_ADDR1 0x0040
232 #define AG71XX_REG_MAC_ADDR2 0x0044
233 #define AG71XX_REG_FIFO_CFG0 0x0048
234 #define AG71XX_REG_FIFO_CFG1 0x004c
235 #define AG71XX_REG_FIFO_CFG2 0x0050
236 #define AG71XX_REG_FIFO_CFG3 0x0054
237 #define AG71XX_REG_FIFO_CFG4 0x0058
238 #define AG71XX_REG_FIFO_CFG5 0x005c
239 #define AG71XX_REG_FIFO_RAM0 0x0060
240 #define AG71XX_REG_FIFO_RAM1 0x0064
241 #define AG71XX_REG_FIFO_RAM2 0x0068
242 #define AG71XX_REG_FIFO_RAM3 0x006c
243 #define AG71XX_REG_FIFO_RAM4 0x0070
244 #define AG71XX_REG_FIFO_RAM5 0x0074
245 #define AG71XX_REG_FIFO_RAM6 0x0078
246 #define AG71XX_REG_FIFO_RAM7 0x007c
247
248 #define AG71XX_REG_TX_CTRL 0x0180
249 #define AG71XX_REG_TX_DESC 0x0184
250 #define AG71XX_REG_TX_STATUS 0x0188
251 #define AG71XX_REG_RX_CTRL 0x018c
252 #define AG71XX_REG_RX_DESC 0x0190
253 #define AG71XX_REG_RX_STATUS 0x0194
254 #define AG71XX_REG_INT_ENABLE 0x0198
255 #define AG71XX_REG_INT_STATUS 0x019c
256
257 #define AG71XX_REG_FIFO_DEPTH 0x01a8
258 #define AG71XX_REG_RX_SM 0x01b0
259 #define AG71XX_REG_TX_SM 0x01b4
260
261 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
262 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
263 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
264 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
265 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
266 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
267 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
268 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
269
270 #define MAC_CFG2_FDX BIT(0)
271 #define MAC_CFG2_CRC_EN BIT(1)
272 #define MAC_CFG2_PAD_CRC_EN BIT(2)
273 #define MAC_CFG2_LEN_CHECK BIT(4)
274 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
275 #define MAC_CFG2_IF_1000 BIT(9)
276 #define MAC_CFG2_IF_10_100 BIT(8)
277
278 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
279 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
280 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
281 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
282 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
283 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
284 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
285
286 #define FIFO_CFG0_ENABLE_SHIFT 8
287
288 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
289 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
290 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
291 #define FIFO_CFG4_CE BIT(3) /* Code Error */
292 #define FIFO_CFG4_CR BIT(4) /* CRC error */
293 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
294 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
295 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
296 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
297 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
298 #define FIFO_CFG4_DR BIT(10) /* Dribble */
299 #define FIFO_CFG4_LE BIT(11) /* Long Event */
300 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
301 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
302 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
303 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
304 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
305 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
306
307 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
308 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
309 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
310 #define FIFO_CFG5_CE BIT(3) /* Code Error */
311 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
312 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
313 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
314 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
315 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
316 #define FIFO_CFG5_DR BIT(9) /* Dribble */
317 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
318 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
319 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
320 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
321 #define FIFO_CFG5_LE BIT(14) /* Long Event */
322 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
323 #define FIFO_CFG5_16 BIT(16) /* unknown */
324 #define FIFO_CFG5_17 BIT(17) /* unknown */
325 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
326 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
327
328 #define AG71XX_INT_TX_PS BIT(0)
329 #define AG71XX_INT_TX_UR BIT(1)
330 #define AG71XX_INT_TX_BE BIT(3)
331 #define AG71XX_INT_RX_PR BIT(4)
332 #define AG71XX_INT_RX_OF BIT(6)
333 #define AG71XX_INT_RX_BE BIT(7)
334
335 #define MAC_IFCTL_SPEED BIT(16)
336
337 #define MII_CFG_CLK_DIV_4 0
338 #define MII_CFG_CLK_DIV_6 2
339 #define MII_CFG_CLK_DIV_8 3
340 #define MII_CFG_CLK_DIV_10 4
341 #define MII_CFG_CLK_DIV_14 5
342 #define MII_CFG_CLK_DIV_20 6
343 #define MII_CFG_CLK_DIV_28 7
344 #define MII_CFG_CLK_DIV_34 8
345 #define MII_CFG_CLK_DIV_42 9
346 #define MII_CFG_CLK_DIV_50 10
347 #define MII_CFG_CLK_DIV_58 11
348 #define MII_CFG_CLK_DIV_66 12
349 #define MII_CFG_CLK_DIV_74 13
350 #define MII_CFG_CLK_DIV_82 14
351 #define MII_CFG_CLK_DIV_98 15
352 #define MII_CFG_RESET BIT(31)
353
354 #define MII_CMD_WRITE 0x0
355 #define MII_CMD_READ 0x1
356 #define MII_ADDR_SHIFT 8
357 #define MII_IND_BUSY BIT(0)
358 #define MII_IND_INVALID BIT(2)
359
360 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
361
362 #define TX_STATUS_PS BIT(0) /* Packet Sent */
363 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
364 #define TX_STATUS_BE BIT(3) /* Bus Error */
365
366 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
367
368 #define RX_STATUS_PR BIT(0) /* Packet Received */
369 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
370 #define RX_STATUS_BE BIT(3) /* Bus Error */
371
372 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
373 {
374 switch (reg) {
375 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
376 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
377 case AG71XX_REG_MII_CFG:
378 break;
379
380 default:
381 BUG();
382 }
383 }
384
385 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
386 {
387 ag71xx_check_reg_offset(ag, reg);
388
389 __raw_writel(value, ag->mac_base + reg);
390 /* flush write */
391 (void) __raw_readl(ag->mac_base + reg);
392 }
393
394 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
395 {
396 ag71xx_check_reg_offset(ag, reg);
397
398 return __raw_readl(ag->mac_base + reg);
399 }
400
401 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
402 {
403 void __iomem *r;
404
405 ag71xx_check_reg_offset(ag, reg);
406
407 r = ag->mac_base + reg;
408 __raw_writel(__raw_readl(r) | mask, r);
409 /* flush write */
410 (void)__raw_readl(r);
411 }
412
413 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
414 {
415 void __iomem *r;
416
417 ag71xx_check_reg_offset(ag, reg);
418
419 r = ag->mac_base + reg;
420 __raw_writel(__raw_readl(r) & ~mask, r);
421 /* flush write */
422 (void) __raw_readl(r);
423 }
424
425 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
426 {
427 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
428 }
429
430 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
431 {
432 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
433 }
434
435 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
436 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
437 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
438 int pktlen);
439 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
440 {
441 return ag71xx_get_pdata(ag)->has_ar8216;
442 }
443 #else
444 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
445 struct sk_buff *skb)
446 {
447 }
448
449 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
450 struct sk_buff *skb,
451 int pktlen)
452 {
453 return 0;
454 }
455 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
456 {
457 return 0;
458 }
459 #endif
460
461 #ifdef CONFIG_AG71XX_DEBUG_FS
462 int ag71xx_debugfs_root_init(void);
463 void ag71xx_debugfs_root_exit(void);
464 int ag71xx_debugfs_init(struct ag71xx *ag);
465 void ag71xx_debugfs_exit(struct ag71xx *ag);
466 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
467 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
468 #else
469 static inline int ag71xx_debugfs_root_init(void) { return 0; }
470 static inline void ag71xx_debugfs_root_exit(void) {}
471 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
472 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
473 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
474 u32 status) {}
475 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
476 int rx, int tx) {}
477 #endif /* CONFIG_AG71XX_DEBUG_FS */
478
479 void ag71xx_ar7240_start(struct ag71xx *ag);
480 void ag71xx_ar7240_stop(struct ag71xx *ag);
481 int ag71xx_ar7240_init(struct ag71xx *ag);
482 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
483
484 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
485 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
486
487 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
488 unsigned reg_addr);
489 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
490 unsigned reg_addr, u16 reg_val);
491
492 #endif /* _AG71XX_H */
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