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ar71xx: enable flow control for ethernet MACs with built-in switch
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
17 static inline void skb_free_frag(void *data)
18 {
19 put_page(virt_to_head_page(data));
20 }
21 #endif
22
23 #define AG71XX_DEFAULT_MSG_ENABLE \
24 (NETIF_MSG_DRV \
25 | NETIF_MSG_PROBE \
26 | NETIF_MSG_LINK \
27 | NETIF_MSG_TIMER \
28 | NETIF_MSG_IFDOWN \
29 | NETIF_MSG_IFUP \
30 | NETIF_MSG_RX_ERR \
31 | NETIF_MSG_TX_ERR)
32
33 static int ag71xx_msg_level = -1;
34
35 module_param_named(msg_level, ag71xx_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define ETH_SWITCH_HEADER_LEN 2
39
40 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
41
42 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
43 {
44 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
45 }
46
47 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
48 {
49 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
54
55 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
58 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
59 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
60 }
61
62 static void ag71xx_dump_regs(struct ag71xx *ag)
63 {
64 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
65 ag->dev->name,
66 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
67 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
68 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
69 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
70 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
71 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
72 ag->dev->name,
73 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
74 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
75 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
76 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
77 ag->dev->name,
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
81 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
82 ag->dev->name,
83 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
84 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
85 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
86 }
87
88 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
89 {
90 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
91 ag->dev->name, label, intr,
92 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
93 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
94 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
95 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
96 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
97 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
98 }
99
100 static void ag71xx_ring_free(struct ag71xx_ring *ring)
101 {
102 int ring_size = BIT(ring->order);
103 kfree(ring->buf);
104
105 if (ring->descs_cpu)
106 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
107 ring->descs_cpu, ring->descs_dma);
108 }
109
110 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
111 {
112 int ring_size = BIT(ring->order);
113 int err;
114
115 ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
116 &ring->descs_dma, GFP_ATOMIC);
117 if (!ring->descs_cpu) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122
123 ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
124 if (!ring->buf) {
125 err = -ENOMEM;
126 goto err;
127 }
128
129 return 0;
130
131 err:
132 return err;
133 }
134
135 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 {
137 struct ag71xx_ring *ring = &ag->tx_ring;
138 struct net_device *dev = ag->dev;
139 int ring_mask = BIT(ring->order) - 1;
140 u32 bytes_compl = 0, pkts_compl = 0;
141
142 while (ring->curr != ring->dirty) {
143 struct ag71xx_desc *desc;
144 u32 i = ring->dirty & ring_mask;
145
146 desc = ag71xx_ring_desc(ring, i);
147 if (!ag71xx_desc_empty(desc)) {
148 desc->ctrl = 0;
149 dev->stats.tx_errors++;
150 }
151
152 if (ring->buf[i].skb) {
153 bytes_compl += ring->buf[i].len;
154 pkts_compl++;
155 dev_kfree_skb_any(ring->buf[i].skb);
156 }
157 ring->buf[i].skb = NULL;
158 ring->dirty++;
159 }
160
161 /* flush descriptors */
162 wmb();
163
164 netdev_completed_queue(dev, pkts_compl, bytes_compl);
165 }
166
167 static void ag71xx_ring_tx_init(struct ag71xx *ag)
168 {
169 struct ag71xx_ring *ring = &ag->tx_ring;
170 int ring_size = BIT(ring->order);
171 int ring_mask = ring_size - 1;
172 int i;
173
174 for (i = 0; i < ring_size; i++) {
175 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
176
177 desc->next = (u32) (ring->descs_dma +
178 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
179
180 desc->ctrl = DESC_EMPTY;
181 ring->buf[i].skb = NULL;
182 }
183
184 /* flush descriptors */
185 wmb();
186
187 ring->curr = 0;
188 ring->dirty = 0;
189 netdev_reset_queue(ag->dev);
190 }
191
192 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
193 {
194 struct ag71xx_ring *ring = &ag->rx_ring;
195 int ring_size = BIT(ring->order);
196 int i;
197
198 if (!ring->buf)
199 return;
200
201 for (i = 0; i < ring_size; i++)
202 if (ring->buf[i].rx_buf) {
203 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
204 ag->rx_buf_size, DMA_FROM_DEVICE);
205 skb_free_frag(ring->buf[i].rx_buf);
206 }
207 }
208
209 static int ag71xx_buffer_offset(struct ag71xx *ag)
210 {
211 int offset = NET_SKB_PAD;
212
213 /*
214 * On AR71xx/AR91xx packets must be 4-byte aligned.
215 *
216 * When using builtin AR8216 support, hardware adds a 2-byte header,
217 * so we don't need any extra alignment in that case.
218 */
219 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
220 return offset;
221
222 return offset + NET_IP_ALIGN;
223 }
224
225 static int ag71xx_buffer_size(struct ag71xx *ag)
226 {
227 return ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
229 }
230
231 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
232 int offset,
233 void *(*alloc)(unsigned int size))
234 {
235 struct ag71xx_ring *ring = &ag->rx_ring;
236 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
237 void *data;
238
239 data = alloc(ag71xx_buffer_size(ag));
240 if (!data)
241 return false;
242
243 buf->rx_buf = data;
244 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
245 DMA_FROM_DEVICE);
246 desc->data = (u32) buf->dma_addr + offset;
247 return true;
248 }
249
250 static int ag71xx_ring_rx_init(struct ag71xx *ag)
251 {
252 struct ag71xx_ring *ring = &ag->rx_ring;
253 int ring_size = BIT(ring->order);
254 int ring_mask = BIT(ring->order) - 1;
255 unsigned int i;
256 int ret;
257 int offset = ag71xx_buffer_offset(ag);
258
259 ret = 0;
260 for (i = 0; i < ring_size; i++) {
261 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
262
263 desc->next = (u32) (ring->descs_dma +
264 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
265
266 DBG("ag71xx: RX desc at %p, next is %08x\n",
267 desc, desc->next);
268 }
269
270 for (i = 0; i < ring_size; i++) {
271 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
272
273 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
274 netdev_alloc_frag)) {
275 ret = -ENOMEM;
276 break;
277 }
278
279 desc->ctrl = DESC_EMPTY;
280 }
281
282 /* flush descriptors */
283 wmb();
284
285 ring->curr = 0;
286 ring->dirty = 0;
287
288 return ret;
289 }
290
291 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
292 {
293 struct ag71xx_ring *ring = &ag->rx_ring;
294 int ring_mask = BIT(ring->order) - 1;
295 unsigned int count;
296 int offset = ag71xx_buffer_offset(ag);
297
298 count = 0;
299 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
300 struct ag71xx_desc *desc;
301 unsigned int i;
302
303 i = ring->dirty & ring_mask;
304 desc = ag71xx_ring_desc(ring, i);
305
306 if (!ring->buf[i].rx_buf &&
307 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
308 napi_alloc_frag))
309 break;
310
311 desc->ctrl = DESC_EMPTY;
312 count++;
313 }
314
315 /* flush descriptors */
316 wmb();
317
318 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
319
320 return count;
321 }
322
323 static int ag71xx_rings_init(struct ag71xx *ag)
324 {
325 int ret;
326
327 ret = ag71xx_ring_alloc(&ag->tx_ring);
328 if (ret)
329 return ret;
330
331 ag71xx_ring_tx_init(ag);
332
333 ret = ag71xx_ring_alloc(&ag->rx_ring);
334 if (ret)
335 return ret;
336
337 ret = ag71xx_ring_rx_init(ag);
338 return ret;
339 }
340
341 static void ag71xx_rings_cleanup(struct ag71xx *ag)
342 {
343 ag71xx_ring_rx_clean(ag);
344 ag71xx_ring_free(&ag->rx_ring);
345
346 ag71xx_ring_tx_clean(ag);
347 netdev_reset_queue(ag->dev);
348 ag71xx_ring_free(&ag->tx_ring);
349 }
350
351 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
352 {
353 switch (ag->speed) {
354 case SPEED_1000:
355 return "1000";
356 case SPEED_100:
357 return "100";
358 case SPEED_10:
359 return "10";
360 }
361
362 return "?";
363 }
364
365 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
366 {
367 u32 t;
368
369 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
370 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
371
372 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
373
374 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
375 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
376 }
377
378 static void ag71xx_dma_reset(struct ag71xx *ag)
379 {
380 u32 val;
381 int i;
382
383 ag71xx_dump_dma_regs(ag);
384
385 /* stop RX and TX */
386 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
387 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
388
389 /*
390 * give the hardware some time to really stop all rx/tx activity
391 * clearing the descriptors too early causes random memory corruption
392 */
393 mdelay(1);
394
395 /* clear descriptor addresses */
396 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
397 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
398
399 /* clear pending RX/TX interrupts */
400 for (i = 0; i < 256; i++) {
401 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
402 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
403 }
404
405 /* clear pending errors */
406 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
407 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
408
409 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
410 if (val)
411 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
412 ag->dev->name, val);
413
414 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
415
416 /* mask out reserved bits */
417 val &= ~0xff000000;
418
419 if (val)
420 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
421 ag->dev->name, val);
422
423 ag71xx_dump_dma_regs(ag);
424 }
425
426 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
427 MAC_CFG1_SRX | MAC_CFG1_STX)
428
429 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
430
431 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
432 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
433 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
434 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
435 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
436 FIFO_CFG4_VT)
437
438 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
439 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
440 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
441 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
442 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
443 FIFO_CFG5_17 | FIFO_CFG5_SF)
444
445 static void ag71xx_hw_stop(struct ag71xx *ag)
446 {
447 /* disable all interrupts and stop the rx/tx engine */
448 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
449 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
450 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
451 }
452
453 static void ag71xx_hw_setup(struct ag71xx *ag)
454 {
455 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
456 struct ag71xx_mdio_platform_data *mpdata;
457 u32 init = MAC_CFG1_INIT;
458
459 if (pdata->mii_bus_dev && ag->pdev->id == 0) {
460 mpdata = pdata->mii_bus_dev->platform_data;
461 if (mpdata && mpdata->builtin_switch)
462 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
463 }
464
465 /* setup MAC configuration registers */
466 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
467
468 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
469 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
470
471 /* setup max frame length to zero */
472 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
473
474 /* setup FIFO configuration registers */
475 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
476 if (pdata->is_ar724x) {
477 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
478 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
479 } else {
480 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
481 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
482 }
483 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
484 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
485 }
486
487 static void ag71xx_hw_init(struct ag71xx *ag)
488 {
489 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
490 u32 reset_mask = pdata->reset_bit;
491
492 ag71xx_hw_stop(ag);
493
494 if (pdata->is_ar724x) {
495 u32 reset_phy = reset_mask;
496
497 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
498 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
499
500 ath79_device_reset_set(reset_phy);
501 msleep(50);
502 ath79_device_reset_clear(reset_phy);
503 msleep(200);
504 }
505
506 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
507 udelay(20);
508
509 ath79_device_reset_set(reset_mask);
510 msleep(100);
511 ath79_device_reset_clear(reset_mask);
512 msleep(200);
513
514 ag71xx_hw_setup(ag);
515
516 ag71xx_dma_reset(ag);
517 }
518
519 static void ag71xx_fast_reset(struct ag71xx *ag)
520 {
521 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
522 struct net_device *dev = ag->dev;
523 u32 reset_mask = pdata->reset_bit;
524 u32 rx_ds;
525 u32 mii_reg;
526
527 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
528
529 ag71xx_hw_stop(ag);
530 wmb();
531
532 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
533 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
534
535 ath79_device_reset_set(reset_mask);
536 udelay(10);
537 ath79_device_reset_clear(reset_mask);
538 udelay(10);
539
540 ag71xx_dma_reset(ag);
541 ag71xx_hw_setup(ag);
542 ag71xx_tx_packets(ag, true);
543 ag->tx_ring.curr = 0;
544 ag->tx_ring.dirty = 0;
545 netdev_reset_queue(ag->dev);
546
547 /* setup max frame length */
548 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
549 ag71xx_max_frame_len(ag->dev->mtu));
550
551 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
552 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
553 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
554
555 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
556 }
557
558 static void ag71xx_hw_start(struct ag71xx *ag)
559 {
560 /* start RX engine */
561 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
562
563 /* enable interrupts */
564 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
565
566 netif_wake_queue(ag->dev);
567 }
568
569 static void
570 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
571 {
572 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
573 u32 cfg2;
574 u32 ifctl;
575 u32 fifo5;
576 u32 fifo3;
577
578 if (!ag->link && update) {
579 ag71xx_hw_stop(ag);
580 netif_carrier_off(ag->dev);
581 if (netif_msg_link(ag))
582 pr_info("%s: link down\n", ag->dev->name);
583 return;
584 }
585
586 if (pdata->is_ar724x)
587 ag71xx_fast_reset(ag);
588
589 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
590 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
591 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
592
593 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
594 ifctl &= ~(MAC_IFCTL_SPEED);
595
596 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
597 fifo5 &= ~FIFO_CFG5_BM;
598
599 switch (ag->speed) {
600 case SPEED_1000:
601 cfg2 |= MAC_CFG2_IF_1000;
602 fifo5 |= FIFO_CFG5_BM;
603 break;
604 case SPEED_100:
605 cfg2 |= MAC_CFG2_IF_10_100;
606 ifctl |= MAC_IFCTL_SPEED;
607 break;
608 case SPEED_10:
609 cfg2 |= MAC_CFG2_IF_10_100;
610 break;
611 default:
612 BUG();
613 return;
614 }
615
616 if (pdata->is_ar91xx)
617 fifo3 = 0x00780fff;
618 else if (pdata->is_ar724x)
619 fifo3 = pdata->fifo_cfg3;
620 else
621 fifo3 = 0x008001ff;
622
623 if (ag->tx_ring.desc_split) {
624 fifo3 &= 0xffff;
625 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
626 }
627
628 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
629
630 if (update && pdata->set_speed)
631 pdata->set_speed(ag->speed);
632
633 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
634 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
635 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
636 ag71xx_hw_start(ag);
637
638 netif_carrier_on(ag->dev);
639 if (update && netif_msg_link(ag))
640 pr_info("%s: link up (%sMbps/%s duplex)\n",
641 ag->dev->name,
642 ag71xx_speed_str(ag),
643 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
644
645 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
646 ag->dev->name,
647 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
648 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
649 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
650
651 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
652 ag->dev->name,
653 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
654 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
655 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
656
657 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
658 ag->dev->name,
659 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
660 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
661 }
662
663 void ag71xx_link_adjust(struct ag71xx *ag)
664 {
665 __ag71xx_link_adjust(ag, true);
666 }
667
668 static int ag71xx_hw_enable(struct ag71xx *ag)
669 {
670 int ret;
671
672 ret = ag71xx_rings_init(ag);
673 if (ret)
674 return ret;
675
676 napi_enable(&ag->napi);
677 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
678 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
679 netif_start_queue(ag->dev);
680
681 return 0;
682 }
683
684 static void ag71xx_hw_disable(struct ag71xx *ag)
685 {
686 unsigned long flags;
687
688 spin_lock_irqsave(&ag->lock, flags);
689
690 netif_stop_queue(ag->dev);
691
692 ag71xx_hw_stop(ag);
693 ag71xx_dma_reset(ag);
694
695 napi_disable(&ag->napi);
696 del_timer_sync(&ag->oom_timer);
697
698 spin_unlock_irqrestore(&ag->lock, flags);
699
700 ag71xx_rings_cleanup(ag);
701 }
702
703 static int ag71xx_open(struct net_device *dev)
704 {
705 struct ag71xx *ag = netdev_priv(dev);
706 unsigned int max_frame_len;
707 int ret;
708
709 netif_carrier_off(dev);
710 max_frame_len = ag71xx_max_frame_len(dev->mtu);
711 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
712
713 /* setup max frame length */
714 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
715 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
716
717 ret = ag71xx_hw_enable(ag);
718 if (ret)
719 goto err;
720
721 ag71xx_phy_start(ag);
722
723 return 0;
724
725 err:
726 ag71xx_rings_cleanup(ag);
727 return ret;
728 }
729
730 static int ag71xx_stop(struct net_device *dev)
731 {
732 struct ag71xx *ag = netdev_priv(dev);
733
734 netif_carrier_off(dev);
735 ag71xx_phy_stop(ag);
736 ag71xx_hw_disable(ag);
737
738 return 0;
739 }
740
741 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
742 {
743 int i;
744 struct ag71xx_desc *desc;
745 int ring_mask = BIT(ring->order) - 1;
746 int ndesc = 0;
747 int split = ring->desc_split;
748
749 if (!split)
750 split = len;
751
752 while (len > 0) {
753 unsigned int cur_len = len;
754
755 i = (ring->curr + ndesc) & ring_mask;
756 desc = ag71xx_ring_desc(ring, i);
757
758 if (!ag71xx_desc_empty(desc))
759 return -1;
760
761 if (cur_len > split) {
762 cur_len = split;
763
764 /*
765 * TX will hang if DMA transfers <= 4 bytes,
766 * make sure next segment is more than 4 bytes long.
767 */
768 if (len <= split + 4)
769 cur_len -= 4;
770 }
771
772 desc->data = addr;
773 addr += cur_len;
774 len -= cur_len;
775
776 if (len > 0)
777 cur_len |= DESC_MORE;
778
779 /* prevent early tx attempt of this descriptor */
780 if (!ndesc)
781 cur_len |= DESC_EMPTY;
782
783 desc->ctrl = cur_len;
784 ndesc++;
785 }
786
787 return ndesc;
788 }
789
790 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
791 struct net_device *dev)
792 {
793 struct ag71xx *ag = netdev_priv(dev);
794 struct ag71xx_ring *ring = &ag->tx_ring;
795 int ring_mask = BIT(ring->order) - 1;
796 int ring_size = BIT(ring->order);
797 struct ag71xx_desc *desc;
798 dma_addr_t dma_addr;
799 int i, n, ring_min;
800
801 if (ag71xx_has_ar8216(ag))
802 ag71xx_add_ar8216_header(ag, skb);
803
804 if (skb->len <= 4) {
805 DBG("%s: packet len is too small\n", ag->dev->name);
806 goto err_drop;
807 }
808
809 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
810 DMA_TO_DEVICE);
811
812 i = ring->curr & ring_mask;
813 desc = ag71xx_ring_desc(ring, i);
814
815 /* setup descriptor fields */
816 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
817 if (n < 0)
818 goto err_drop_unmap;
819
820 i = (ring->curr + n - 1) & ring_mask;
821 ring->buf[i].len = skb->len;
822 ring->buf[i].skb = skb;
823 ring->buf[i].timestamp = jiffies;
824
825 netdev_sent_queue(dev, skb->len);
826
827 desc->ctrl &= ~DESC_EMPTY;
828 ring->curr += n;
829
830 /* flush descriptor */
831 wmb();
832
833 ring_min = 2;
834 if (ring->desc_split)
835 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
836
837 if (ring->curr - ring->dirty >= ring_size - ring_min) {
838 DBG("%s: tx queue full\n", dev->name);
839 netif_stop_queue(dev);
840 }
841
842 DBG("%s: packet injected into TX queue\n", ag->dev->name);
843
844 /* enable TX engine */
845 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
846
847 return NETDEV_TX_OK;
848
849 err_drop_unmap:
850 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
851
852 err_drop:
853 dev->stats.tx_dropped++;
854
855 dev_kfree_skb(skb);
856 return NETDEV_TX_OK;
857 }
858
859 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
860 {
861 struct ag71xx *ag = netdev_priv(dev);
862 int ret;
863
864 switch (cmd) {
865 case SIOCETHTOOL:
866 if (ag->phy_dev == NULL)
867 break;
868
869 spin_lock_irq(&ag->lock);
870 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
871 spin_unlock_irq(&ag->lock);
872 return ret;
873
874 case SIOCSIFHWADDR:
875 if (copy_from_user
876 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
877 return -EFAULT;
878 return 0;
879
880 case SIOCGIFHWADDR:
881 if (copy_to_user
882 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
883 return -EFAULT;
884 return 0;
885
886 case SIOCGMIIPHY:
887 case SIOCGMIIREG:
888 case SIOCSMIIREG:
889 if (ag->phy_dev == NULL)
890 break;
891
892 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
893
894 default:
895 break;
896 }
897
898 return -EOPNOTSUPP;
899 }
900
901 static void ag71xx_oom_timer_handler(unsigned long data)
902 {
903 struct net_device *dev = (struct net_device *) data;
904 struct ag71xx *ag = netdev_priv(dev);
905
906 napi_schedule(&ag->napi);
907 }
908
909 static void ag71xx_tx_timeout(struct net_device *dev)
910 {
911 struct ag71xx *ag = netdev_priv(dev);
912
913 if (netif_msg_tx_err(ag))
914 pr_info("%s: tx timeout\n", ag->dev->name);
915
916 schedule_work(&ag->restart_work);
917 }
918
919 static void ag71xx_restart_work_func(struct work_struct *work)
920 {
921 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
922
923 rtnl_lock();
924 ag71xx_hw_disable(ag);
925 ag71xx_hw_enable(ag);
926 if (ag->link)
927 __ag71xx_link_adjust(ag, false);
928 rtnl_unlock();
929 }
930
931 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
932 {
933 u32 rx_sm, tx_sm, rx_fd;
934
935 if (likely(time_before(jiffies, timestamp + HZ/10)))
936 return false;
937
938 if (!netif_carrier_ok(ag->dev))
939 return false;
940
941 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
942 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
943 return true;
944
945 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
946 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
947 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
948 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
949 return true;
950
951 return false;
952 }
953
954 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
955 {
956 struct ag71xx_ring *ring = &ag->tx_ring;
957 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
958 int ring_mask = BIT(ring->order) - 1;
959 int ring_size = BIT(ring->order);
960 int sent = 0;
961 int bytes_compl = 0;
962 int n = 0;
963
964 DBG("%s: processing TX ring\n", ag->dev->name);
965
966 while (ring->dirty + n != ring->curr) {
967 unsigned int i = (ring->dirty + n) & ring_mask;
968 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
969 struct sk_buff *skb = ring->buf[i].skb;
970
971 if (!flush && !ag71xx_desc_empty(desc)) {
972 if (pdata->is_ar724x &&
973 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
974 schedule_work(&ag->restart_work);
975 break;
976 }
977
978 if (flush)
979 desc->ctrl |= DESC_EMPTY;
980
981 n++;
982 if (!skb)
983 continue;
984
985 dev_kfree_skb_any(skb);
986 ring->buf[i].skb = NULL;
987
988 bytes_compl += ring->buf[i].len;
989
990 sent++;
991 ring->dirty += n;
992
993 while (n > 0) {
994 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
995 n--;
996 }
997 }
998
999 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1000
1001 ag->dev->stats.tx_bytes += bytes_compl;
1002 ag->dev->stats.tx_packets += sent;
1003
1004 if (!sent)
1005 return 0;
1006
1007 netdev_completed_queue(ag->dev, sent, bytes_compl);
1008 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1009 netif_wake_queue(ag->dev);
1010
1011 return sent;
1012 }
1013
1014 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1015 {
1016 struct net_device *dev = ag->dev;
1017 struct ag71xx_ring *ring = &ag->rx_ring;
1018 int offset = ag71xx_buffer_offset(ag);
1019 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1020 int ring_mask = BIT(ring->order) - 1;
1021 int ring_size = BIT(ring->order);
1022 struct sk_buff_head queue;
1023 struct sk_buff *skb;
1024 int done = 0;
1025
1026 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1027 dev->name, limit, ring->curr, ring->dirty);
1028
1029 skb_queue_head_init(&queue);
1030
1031 while (done < limit) {
1032 unsigned int i = ring->curr & ring_mask;
1033 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1034 int pktlen;
1035 int err = 0;
1036
1037 if (ag71xx_desc_empty(desc))
1038 break;
1039
1040 if ((ring->dirty + ring_size) == ring->curr) {
1041 ag71xx_assert(0);
1042 break;
1043 }
1044
1045 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1046
1047 pktlen = desc->ctrl & pktlen_mask;
1048 pktlen -= ETH_FCS_LEN;
1049
1050 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1051 ag->rx_buf_size, DMA_FROM_DEVICE);
1052
1053 dev->stats.rx_packets++;
1054 dev->stats.rx_bytes += pktlen;
1055
1056 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1057 if (!skb) {
1058 skb_free_frag(ring->buf[i].rx_buf);
1059 goto next;
1060 }
1061
1062 skb_reserve(skb, offset);
1063 skb_put(skb, pktlen);
1064
1065 if (ag71xx_has_ar8216(ag))
1066 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1067
1068 if (err) {
1069 dev->stats.rx_dropped++;
1070 kfree_skb(skb);
1071 } else {
1072 skb->dev = dev;
1073 skb->ip_summed = CHECKSUM_NONE;
1074 __skb_queue_tail(&queue, skb);
1075 }
1076
1077 next:
1078 ring->buf[i].rx_buf = NULL;
1079 done++;
1080
1081 ring->curr++;
1082 }
1083
1084 ag71xx_ring_rx_refill(ag);
1085
1086 while ((skb = __skb_dequeue(&queue)) != NULL) {
1087 skb->protocol = eth_type_trans(skb, dev);
1088 netif_receive_skb(skb);
1089 }
1090
1091 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1092 dev->name, ring->curr, ring->dirty, done);
1093
1094 return done;
1095 }
1096
1097 static int ag71xx_poll(struct napi_struct *napi, int limit)
1098 {
1099 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1100 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1101 struct net_device *dev = ag->dev;
1102 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1103 int rx_ring_size = BIT(rx_ring->order);
1104 unsigned long flags;
1105 u32 status;
1106 int tx_done;
1107 int rx_done;
1108
1109 pdata->ddr_flush();
1110 tx_done = ag71xx_tx_packets(ag, false);
1111
1112 DBG("%s: processing RX ring\n", dev->name);
1113 rx_done = ag71xx_rx_packets(ag, limit);
1114
1115 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1116
1117 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1118 goto oom;
1119
1120 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1121 if (unlikely(status & RX_STATUS_OF)) {
1122 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1123 dev->stats.rx_fifo_errors++;
1124
1125 /* restart RX */
1126 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1127 }
1128
1129 if (rx_done < limit) {
1130 if (status & RX_STATUS_PR)
1131 goto more;
1132
1133 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1134 if (status & TX_STATUS_PS)
1135 goto more;
1136
1137 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1138 dev->name, rx_done, tx_done, limit);
1139
1140 napi_complete(napi);
1141
1142 /* enable interrupts */
1143 spin_lock_irqsave(&ag->lock, flags);
1144 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1145 spin_unlock_irqrestore(&ag->lock, flags);
1146 return rx_done;
1147 }
1148
1149 more:
1150 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1151 dev->name, rx_done, tx_done, limit);
1152 return limit;
1153
1154 oom:
1155 if (netif_msg_rx_err(ag))
1156 pr_info("%s: out of memory\n", dev->name);
1157
1158 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1159 napi_complete(napi);
1160 return 0;
1161 }
1162
1163 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1164 {
1165 struct net_device *dev = dev_id;
1166 struct ag71xx *ag = netdev_priv(dev);
1167 u32 status;
1168
1169 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1170 ag71xx_dump_intr(ag, "raw", status);
1171
1172 if (unlikely(!status))
1173 return IRQ_NONE;
1174
1175 if (unlikely(status & AG71XX_INT_ERR)) {
1176 if (status & AG71XX_INT_TX_BE) {
1177 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1178 dev_err(&dev->dev, "TX BUS error\n");
1179 }
1180 if (status & AG71XX_INT_RX_BE) {
1181 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1182 dev_err(&dev->dev, "RX BUS error\n");
1183 }
1184 }
1185
1186 if (likely(status & AG71XX_INT_POLL)) {
1187 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1188 DBG("%s: enable polling mode\n", dev->name);
1189 napi_schedule(&ag->napi);
1190 }
1191
1192 ag71xx_debugfs_update_int_stats(ag, status);
1193
1194 return IRQ_HANDLED;
1195 }
1196
1197 #ifdef CONFIG_NET_POLL_CONTROLLER
1198 /*
1199 * Polling 'interrupt' - used by things like netconsole to send skbs
1200 * without having to re-enable interrupts. It's not called while
1201 * the interrupt routine is executing.
1202 */
1203 static void ag71xx_netpoll(struct net_device *dev)
1204 {
1205 disable_irq(dev->irq);
1206 ag71xx_interrupt(dev->irq, dev);
1207 enable_irq(dev->irq);
1208 }
1209 #endif
1210
1211 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1212 {
1213 struct ag71xx *ag = netdev_priv(dev);
1214 unsigned int max_frame_len;
1215
1216 max_frame_len = ag71xx_max_frame_len(new_mtu);
1217 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1218 return -EINVAL;
1219
1220 if (netif_running(dev))
1221 return -EBUSY;
1222
1223 dev->mtu = new_mtu;
1224 return 0;
1225 }
1226
1227 static const struct net_device_ops ag71xx_netdev_ops = {
1228 .ndo_open = ag71xx_open,
1229 .ndo_stop = ag71xx_stop,
1230 .ndo_start_xmit = ag71xx_hard_start_xmit,
1231 .ndo_do_ioctl = ag71xx_do_ioctl,
1232 .ndo_tx_timeout = ag71xx_tx_timeout,
1233 .ndo_change_mtu = ag71xx_change_mtu,
1234 .ndo_set_mac_address = eth_mac_addr,
1235 .ndo_validate_addr = eth_validate_addr,
1236 #ifdef CONFIG_NET_POLL_CONTROLLER
1237 .ndo_poll_controller = ag71xx_netpoll,
1238 #endif
1239 };
1240
1241 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1242 {
1243 switch (mode) {
1244 case PHY_INTERFACE_MODE_MII:
1245 return "MII";
1246 case PHY_INTERFACE_MODE_GMII:
1247 return "GMII";
1248 case PHY_INTERFACE_MODE_RMII:
1249 return "RMII";
1250 case PHY_INTERFACE_MODE_RGMII:
1251 return "RGMII";
1252 case PHY_INTERFACE_MODE_SGMII:
1253 return "SGMII";
1254 default:
1255 break;
1256 }
1257
1258 return "unknown";
1259 }
1260
1261
1262 static int ag71xx_probe(struct platform_device *pdev)
1263 {
1264 struct net_device *dev;
1265 struct resource *res;
1266 struct ag71xx *ag;
1267 struct ag71xx_platform_data *pdata;
1268 int tx_size, err;
1269
1270 pdata = pdev->dev.platform_data;
1271 if (!pdata) {
1272 dev_err(&pdev->dev, "no platform data specified\n");
1273 err = -ENXIO;
1274 goto err_out;
1275 }
1276
1277 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1278 dev_err(&pdev->dev, "no MII bus device specified\n");
1279 err = -EINVAL;
1280 goto err_out;
1281 }
1282
1283 dev = alloc_etherdev(sizeof(*ag));
1284 if (!dev) {
1285 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1286 err = -ENOMEM;
1287 goto err_out;
1288 }
1289
1290 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1291 return -EINVAL;
1292
1293 SET_NETDEV_DEV(dev, &pdev->dev);
1294
1295 ag = netdev_priv(dev);
1296 ag->pdev = pdev;
1297 ag->dev = dev;
1298 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1299 AG71XX_DEFAULT_MSG_ENABLE);
1300 spin_lock_init(&ag->lock);
1301
1302 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1303 if (!res) {
1304 dev_err(&pdev->dev, "no mac_base resource found\n");
1305 err = -ENXIO;
1306 goto err_out;
1307 }
1308
1309 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1310 if (!ag->mac_base) {
1311 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1312 err = -ENOMEM;
1313 goto err_free_dev;
1314 }
1315
1316 dev->irq = platform_get_irq(pdev, 0);
1317 err = request_irq(dev->irq, ag71xx_interrupt,
1318 0x0,
1319 dev->name, dev);
1320 if (err) {
1321 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1322 goto err_unmap_base;
1323 }
1324
1325 dev->base_addr = (unsigned long)ag->mac_base;
1326 dev->netdev_ops = &ag71xx_netdev_ops;
1327 dev->ethtool_ops = &ag71xx_ethtool_ops;
1328
1329 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1330
1331 init_timer(&ag->oom_timer);
1332 ag->oom_timer.data = (unsigned long) dev;
1333 ag->oom_timer.function = ag71xx_oom_timer_handler;
1334
1335 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1336 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1337
1338 ag->max_frame_len = pdata->max_frame_len;
1339 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1340
1341 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1342 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1343 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1344 }
1345 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1346
1347 ag->stop_desc = dma_alloc_coherent(NULL,
1348 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1349
1350 if (!ag->stop_desc)
1351 goto err_free_irq;
1352
1353 ag->stop_desc->data = 0;
1354 ag->stop_desc->ctrl = 0;
1355 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1356
1357 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1358
1359 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1360
1361 ag71xx_dump_regs(ag);
1362
1363 ag71xx_hw_init(ag);
1364
1365 ag71xx_dump_regs(ag);
1366
1367 err = ag71xx_phy_connect(ag);
1368 if (err)
1369 goto err_free_desc;
1370
1371 err = ag71xx_debugfs_init(ag);
1372 if (err)
1373 goto err_phy_disconnect;
1374
1375 platform_set_drvdata(pdev, dev);
1376
1377 err = register_netdev(dev);
1378 if (err) {
1379 dev_err(&pdev->dev, "unable to register net device\n");
1380 goto err_debugfs_exit;
1381 }
1382
1383 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1384 dev->name, dev->base_addr, dev->irq,
1385 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1386
1387 return 0;
1388
1389 err_debugfs_exit:
1390 ag71xx_debugfs_exit(ag);
1391 err_phy_disconnect:
1392 ag71xx_phy_disconnect(ag);
1393 err_free_desc:
1394 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1395 ag->stop_desc_dma);
1396 err_free_irq:
1397 free_irq(dev->irq, dev);
1398 err_unmap_base:
1399 iounmap(ag->mac_base);
1400 err_free_dev:
1401 kfree(dev);
1402 err_out:
1403 platform_set_drvdata(pdev, NULL);
1404 return err;
1405 }
1406
1407 static int ag71xx_remove(struct platform_device *pdev)
1408 {
1409 struct net_device *dev = platform_get_drvdata(pdev);
1410
1411 if (dev) {
1412 struct ag71xx *ag = netdev_priv(dev);
1413
1414 ag71xx_debugfs_exit(ag);
1415 ag71xx_phy_disconnect(ag);
1416 unregister_netdev(dev);
1417 free_irq(dev->irq, dev);
1418 iounmap(ag->mac_base);
1419 kfree(dev);
1420 platform_set_drvdata(pdev, NULL);
1421 }
1422
1423 return 0;
1424 }
1425
1426 static struct platform_driver ag71xx_driver = {
1427 .probe = ag71xx_probe,
1428 .remove = ag71xx_remove,
1429 .driver = {
1430 .name = AG71XX_DRV_NAME,
1431 }
1432 };
1433
1434 static int __init ag71xx_module_init(void)
1435 {
1436 int ret;
1437
1438 ret = ag71xx_debugfs_root_init();
1439 if (ret)
1440 goto err_out;
1441
1442 ret = ag71xx_mdio_driver_init();
1443 if (ret)
1444 goto err_debugfs_exit;
1445
1446 ret = platform_driver_register(&ag71xx_driver);
1447 if (ret)
1448 goto err_mdio_exit;
1449
1450 return 0;
1451
1452 err_mdio_exit:
1453 ag71xx_mdio_driver_exit();
1454 err_debugfs_exit:
1455 ag71xx_debugfs_root_exit();
1456 err_out:
1457 return ret;
1458 }
1459
1460 static void __exit ag71xx_module_exit(void)
1461 {
1462 platform_driver_unregister(&ag71xx_driver);
1463 ag71xx_mdio_driver_exit();
1464 ag71xx_debugfs_root_exit();
1465 }
1466
1467 module_init(ag71xx_module_init);
1468 module_exit(ag71xx_module_exit);
1469
1470 MODULE_VERSION(AG71XX_DRV_VERSION);
1471 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1472 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1473 MODULE_LICENSE("GPL v2");
1474 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository