projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ar71xx: ag71xx: calculate max frame len register value from the MTU
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
32 {
33 return ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
34 }
35
36 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
37 {
38 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
39 ag->dev->name,
40 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
41 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
42 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
43
44 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
45 ag->dev->name,
46 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
47 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
48 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
49 }
50
51 static void ag71xx_dump_regs(struct ag71xx *ag)
52 {
53 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
54 ag->dev->name,
55 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
56 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
57 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
58 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
59 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
60 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
63 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
65 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
70 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
71 ag->dev->name,
72 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
73 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
75 }
76
77 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
78 {
79 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
80 ag->dev->name, label, intr,
81 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
82 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
83 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
84 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
85 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
86 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
87 }
88
89 static void ag71xx_ring_free(struct ag71xx_ring *ring)
90 {
91 kfree(ring->buf);
92
93 if (ring->descs_cpu)
94 dma_free_coherent(NULL, ring->size * ring->desc_size,
95 ring->descs_cpu, ring->descs_dma);
96 }
97
98 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
99 {
100 int err;
101 int i;
102
103 ring->desc_size = sizeof(struct ag71xx_desc);
104 if (ring->desc_size % cache_line_size()) {
105 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
106 ring, ring->desc_size,
107 roundup(ring->desc_size, cache_line_size()));
108 ring->desc_size = roundup(ring->desc_size, cache_line_size());
109 }
110
111 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
112 &ring->descs_dma, GFP_ATOMIC);
113 if (!ring->descs_cpu) {
114 err = -ENOMEM;
115 goto err;
116 }
117
118
119 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
120 if (!ring->buf) {
121 err = -ENOMEM;
122 goto err;
123 }
124
125 for (i = 0; i < ring->size; i++) {
126 int idx = i * ring->desc_size;
127 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
128 DBG("ag71xx: ring %p, desc %d at %p\n",
129 ring, i, ring->buf[i].desc);
130 }
131
132 return 0;
133
134 err:
135 return err;
136 }
137
138 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
139 {
140 struct ag71xx_ring *ring = &ag->tx_ring;
141 struct net_device *dev = ag->dev;
142 u32 bytes_compl = 0, pkts_compl = 0;
143
144 while (ring->curr != ring->dirty) {
145 u32 i = ring->dirty % ring->size;
146
147 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
148 ring->buf[i].desc->ctrl = 0;
149 dev->stats.tx_errors++;
150 }
151
152 if (ring->buf[i].skb) {
153 bytes_compl += ring->buf[i].len;
154 pkts_compl++;
155 dev_kfree_skb_any(ring->buf[i].skb);
156 }
157 ring->buf[i].skb = NULL;
158 ring->dirty++;
159 }
160
161 /* flush descriptors */
162 wmb();
163
164 netdev_completed_queue(dev, pkts_compl, bytes_compl);
165 }
166
167 static void ag71xx_ring_tx_init(struct ag71xx *ag)
168 {
169 struct ag71xx_ring *ring = &ag->tx_ring;
170 int i;
171
172 for (i = 0; i < ring->size; i++) {
173 ring->buf[i].desc->next = (u32) (ring->descs_dma +
174 ring->desc_size * ((i + 1) % ring->size));
175
176 ring->buf[i].desc->ctrl = DESC_EMPTY;
177 ring->buf[i].skb = NULL;
178 }
179
180 /* flush descriptors */
181 wmb();
182
183 ring->curr = 0;
184 ring->dirty = 0;
185 netdev_reset_queue(ag->dev);
186 }
187
188 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
189 {
190 struct ag71xx_ring *ring = &ag->rx_ring;
191 int i;
192
193 if (!ring->buf)
194 return;
195
196 for (i = 0; i < ring->size; i++)
197 if (ring->buf[i].rx_buf) {
198 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
199 ag->rx_buf_size, DMA_FROM_DEVICE);
200 kfree(ring->buf[i].rx_buf);
201 }
202 }
203
204 static int ag71xx_buffer_offset(struct ag71xx *ag)
205 {
206 int offset = NET_SKB_PAD;
207
208 /*
209 * On AR71xx/AR91xx packets must be 4-byte aligned.
210 *
211 * When using builtin AR8216 support, hardware adds a 2-byte header,
212 * so we don't need any extra alignment in that case.
213 */
214 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
215 return offset;
216
217 return offset + NET_IP_ALIGN;
218 }
219
220 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
221 int offset)
222 {
223 void *data;
224
225 data = kmalloc(ag->rx_buf_size +
226 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
227 GFP_ATOMIC);
228 if (!data)
229 return false;
230
231 buf->rx_buf = data;
232 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
233 DMA_FROM_DEVICE);
234 buf->desc->data = (u32) buf->dma_addr + offset;
235 return true;
236 }
237
238 static int ag71xx_ring_rx_init(struct ag71xx *ag)
239 {
240 struct ag71xx_ring *ring = &ag->rx_ring;
241 unsigned int i;
242 int ret;
243 int offset = ag71xx_buffer_offset(ag);
244
245 ret = 0;
246 for (i = 0; i < ring->size; i++) {
247 ring->buf[i].desc->next = (u32) (ring->descs_dma +
248 ring->desc_size * ((i + 1) % ring->size));
249
250 DBG("ag71xx: RX desc at %p, next is %08x\n",
251 ring->buf[i].desc,
252 ring->buf[i].desc->next);
253 }
254
255 for (i = 0; i < ring->size; i++) {
256 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
257 ret = -ENOMEM;
258 break;
259 }
260
261 ring->buf[i].desc->ctrl = DESC_EMPTY;
262 }
263
264 /* flush descriptors */
265 wmb();
266
267 ring->curr = 0;
268 ring->dirty = 0;
269
270 return ret;
271 }
272
273 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
274 {
275 struct ag71xx_ring *ring = &ag->rx_ring;
276 unsigned int count;
277 int offset = ag71xx_buffer_offset(ag);
278
279 count = 0;
280 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
281 unsigned int i;
282
283 i = ring->dirty % ring->size;
284
285 if (!ring->buf[i].rx_buf &&
286 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
287 break;
288
289 ring->buf[i].desc->ctrl = DESC_EMPTY;
290 count++;
291 }
292
293 /* flush descriptors */
294 wmb();
295
296 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
297
298 return count;
299 }
300
301 static int ag71xx_rings_init(struct ag71xx *ag)
302 {
303 int ret;
304
305 ret = ag71xx_ring_alloc(&ag->tx_ring);
306 if (ret)
307 return ret;
308
309 ag71xx_ring_tx_init(ag);
310
311 ret = ag71xx_ring_alloc(&ag->rx_ring);
312 if (ret)
313 return ret;
314
315 ret = ag71xx_ring_rx_init(ag);
316 return ret;
317 }
318
319 static void ag71xx_rings_cleanup(struct ag71xx *ag)
320 {
321 ag71xx_ring_rx_clean(ag);
322 ag71xx_ring_free(&ag->rx_ring);
323
324 ag71xx_ring_tx_clean(ag);
325 netdev_reset_queue(ag->dev);
326 ag71xx_ring_free(&ag->tx_ring);
327 }
328
329 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
330 {
331 switch (ag->speed) {
332 case SPEED_1000:
333 return "1000";
334 case SPEED_100:
335 return "100";
336 case SPEED_10:
337 return "10";
338 }
339
340 return "?";
341 }
342
343 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
344 {
345 u32 t;
346
347 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
348 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
349
350 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
351
352 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
354 }
355
356 static void ag71xx_dma_reset(struct ag71xx *ag)
357 {
358 u32 val;
359 int i;
360
361 ag71xx_dump_dma_regs(ag);
362
363 /* stop RX and TX */
364 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
365 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
366
367 /*
368 * give the hardware some time to really stop all rx/tx activity
369 * clearing the descriptors too early causes random memory corruption
370 */
371 mdelay(1);
372
373 /* clear descriptor addresses */
374 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
375 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
376
377 /* clear pending RX/TX interrupts */
378 for (i = 0; i < 256; i++) {
379 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
380 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
381 }
382
383 /* clear pending errors */
384 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
385 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
386
387 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
388 if (val)
389 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
390 ag->dev->name, val);
391
392 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
393
394 /* mask out reserved bits */
395 val &= ~0xff000000;
396
397 if (val)
398 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
399 ag->dev->name, val);
400
401 ag71xx_dump_dma_regs(ag);
402 }
403
404 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
405 MAC_CFG1_SRX | MAC_CFG1_STX)
406
407 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
408
409 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
410 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
411 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
412 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
413 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
414 FIFO_CFG4_VT)
415
416 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
417 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
418 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
419 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
420 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
421 FIFO_CFG5_17 | FIFO_CFG5_SF)
422
423 static void ag71xx_hw_stop(struct ag71xx *ag)
424 {
425 /* disable all interrupts and stop the rx/tx engine */
426 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
427 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
428 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
429 }
430
431 static void ag71xx_hw_setup(struct ag71xx *ag)
432 {
433 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
434
435 /* setup MAC configuration registers */
436 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
437
438 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
439 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
440
441 /* setup max frame length to zero */
442 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
443
444 /* setup FIFO configuration registers */
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
446 if (pdata->is_ar724x) {
447 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
448 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
449 } else {
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
452 }
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
455 }
456
457 static void ag71xx_hw_init(struct ag71xx *ag)
458 {
459 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
460 u32 reset_mask = pdata->reset_bit;
461
462 ag71xx_hw_stop(ag);
463
464 if (pdata->is_ar724x) {
465 u32 reset_phy = reset_mask;
466
467 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
468 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
469
470 ath79_device_reset_set(reset_phy);
471 mdelay(50);
472 ath79_device_reset_clear(reset_phy);
473 mdelay(200);
474 }
475
476 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
477 udelay(20);
478
479 ath79_device_reset_set(reset_mask);
480 mdelay(100);
481 ath79_device_reset_clear(reset_mask);
482 mdelay(200);
483
484 ag71xx_hw_setup(ag);
485
486 ag71xx_dma_reset(ag);
487 }
488
489 static void ag71xx_fast_reset(struct ag71xx *ag)
490 {
491 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
492 struct net_device *dev = ag->dev;
493 u32 reset_mask = pdata->reset_bit;
494 u32 rx_ds, tx_ds;
495 u32 mii_reg;
496
497 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
498
499 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
500 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
501 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
502
503 ath79_device_reset_set(reset_mask);
504 udelay(10);
505 ath79_device_reset_clear(reset_mask);
506 udelay(10);
507
508 ag71xx_dma_reset(ag);
509 ag71xx_hw_setup(ag);
510
511 /* setup max frame length */
512 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
513 ag71xx_max_frame_len(ag->dev->mtu));
514
515 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
516 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
517 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
518
519 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
520 }
521
522 static void ag71xx_hw_start(struct ag71xx *ag)
523 {
524 /* start RX engine */
525 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
526
527 /* enable interrupts */
528 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
529 }
530
531 void ag71xx_link_adjust(struct ag71xx *ag)
532 {
533 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
534 u32 cfg2;
535 u32 ifctl;
536 u32 fifo5;
537
538 if (!ag->link) {
539 ag71xx_hw_stop(ag);
540 netif_carrier_off(ag->dev);
541 if (netif_msg_link(ag))
542 pr_info("%s: link down\n", ag->dev->name);
543 return;
544 }
545
546 if (pdata->is_ar724x)
547 ag71xx_fast_reset(ag);
548
549 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
550 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
551 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
552
553 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
554 ifctl &= ~(MAC_IFCTL_SPEED);
555
556 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
557 fifo5 &= ~FIFO_CFG5_BM;
558
559 switch (ag->speed) {
560 case SPEED_1000:
561 cfg2 |= MAC_CFG2_IF_1000;
562 fifo5 |= FIFO_CFG5_BM;
563 break;
564 case SPEED_100:
565 cfg2 |= MAC_CFG2_IF_10_100;
566 ifctl |= MAC_IFCTL_SPEED;
567 break;
568 case SPEED_10:
569 cfg2 |= MAC_CFG2_IF_10_100;
570 break;
571 default:
572 BUG();
573 return;
574 }
575
576 if (pdata->is_ar91xx)
577 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
578 else if (pdata->is_ar724x)
579 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
580 else
581 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
582
583 if (pdata->set_speed)
584 pdata->set_speed(ag->speed);
585
586 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
587 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
588 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
589 ag71xx_hw_start(ag);
590
591 netif_carrier_on(ag->dev);
592 if (netif_msg_link(ag))
593 pr_info("%s: link up (%sMbps/%s duplex)\n",
594 ag->dev->name,
595 ag71xx_speed_str(ag),
596 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
597
598 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
599 ag->dev->name,
600 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
601 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
602 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
603
604 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
605 ag->dev->name,
606 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
607 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
608 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
609
610 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
611 ag->dev->name,
612 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
613 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
614 }
615
616 static int ag71xx_open(struct net_device *dev)
617 {
618 struct ag71xx *ag = netdev_priv(dev);
619 unsigned int max_frame_len;
620 int ret;
621
622 max_frame_len = ag71xx_max_frame_len(dev->mtu);
623 ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
624
625 /* setup max frame length */
626 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
627
628 ret = ag71xx_rings_init(ag);
629 if (ret)
630 goto err;
631
632 napi_enable(&ag->napi);
633
634 netif_carrier_off(dev);
635 ag71xx_phy_start(ag);
636
637 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
638 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
639
640 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
641
642 netif_start_queue(dev);
643
644 return 0;
645
646 err:
647 ag71xx_rings_cleanup(ag);
648 return ret;
649 }
650
651 static int ag71xx_stop(struct net_device *dev)
652 {
653 struct ag71xx *ag = netdev_priv(dev);
654 unsigned long flags;
655
656 netif_carrier_off(dev);
657 ag71xx_phy_stop(ag);
658
659 spin_lock_irqsave(&ag->lock, flags);
660
661 netif_stop_queue(dev);
662
663 ag71xx_hw_stop(ag);
664 ag71xx_dma_reset(ag);
665
666 napi_disable(&ag->napi);
667 del_timer_sync(&ag->oom_timer);
668
669 spin_unlock_irqrestore(&ag->lock, flags);
670
671 ag71xx_rings_cleanup(ag);
672
673 return 0;
674 }
675
676 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
677 struct net_device *dev)
678 {
679 struct ag71xx *ag = netdev_priv(dev);
680 struct ag71xx_ring *ring = &ag->tx_ring;
681 struct ag71xx_desc *desc;
682 dma_addr_t dma_addr;
683 int i;
684
685 i = ring->curr % ring->size;
686 desc = ring->buf[i].desc;
687
688 if (!ag71xx_desc_empty(desc))
689 goto err_drop;
690
691 if (ag71xx_has_ar8216(ag))
692 ag71xx_add_ar8216_header(ag, skb);
693
694 if (skb->len <= 0) {
695 DBG("%s: packet len is too small\n", ag->dev->name);
696 goto err_drop;
697 }
698
699 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
700 DMA_TO_DEVICE);
701
702 netdev_sent_queue(dev, skb->len);
703 ring->buf[i].len = skb->len;
704 ring->buf[i].skb = skb;
705 ring->buf[i].timestamp = jiffies;
706
707 /* setup descriptor fields */
708 desc->data = (u32) dma_addr;
709 desc->ctrl = skb->len & ag->desc_pktlen_mask;
710
711 /* flush descriptor */
712 wmb();
713
714 ring->curr++;
715 if (ring->curr == (ring->dirty + ring->size)) {
716 DBG("%s: tx queue full\n", ag->dev->name);
717 netif_stop_queue(dev);
718 }
719
720 DBG("%s: packet injected into TX queue\n", ag->dev->name);
721
722 /* enable TX engine */
723 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
724
725 return NETDEV_TX_OK;
726
727 err_drop:
728 dev->stats.tx_dropped++;
729
730 dev_kfree_skb(skb);
731 return NETDEV_TX_OK;
732 }
733
734 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
735 {
736 struct ag71xx *ag = netdev_priv(dev);
737 int ret;
738
739 switch (cmd) {
740 case SIOCETHTOOL:
741 if (ag->phy_dev == NULL)
742 break;
743
744 spin_lock_irq(&ag->lock);
745 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
746 spin_unlock_irq(&ag->lock);
747 return ret;
748
749 case SIOCSIFHWADDR:
750 if (copy_from_user
751 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
752 return -EFAULT;
753 return 0;
754
755 case SIOCGIFHWADDR:
756 if (copy_to_user
757 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
758 return -EFAULT;
759 return 0;
760
761 case SIOCGMIIPHY:
762 case SIOCGMIIREG:
763 case SIOCSMIIREG:
764 if (ag->phy_dev == NULL)
765 break;
766
767 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
768
769 default:
770 break;
771 }
772
773 return -EOPNOTSUPP;
774 }
775
776 static void ag71xx_oom_timer_handler(unsigned long data)
777 {
778 struct net_device *dev = (struct net_device *) data;
779 struct ag71xx *ag = netdev_priv(dev);
780
781 napi_schedule(&ag->napi);
782 }
783
784 static void ag71xx_tx_timeout(struct net_device *dev)
785 {
786 struct ag71xx *ag = netdev_priv(dev);
787
788 if (netif_msg_tx_err(ag))
789 pr_info("%s: tx timeout\n", ag->dev->name);
790
791 schedule_work(&ag->restart_work);
792 }
793
794 static void ag71xx_restart_work_func(struct work_struct *work)
795 {
796 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
797
798 if (ag71xx_get_pdata(ag)->is_ar724x) {
799 ag->link = 0;
800 ag71xx_link_adjust(ag);
801 return;
802 }
803
804 ag71xx_stop(ag->dev);
805 ag71xx_open(ag->dev);
806 }
807
808 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
809 {
810 u32 rx_sm, tx_sm, rx_fd;
811
812 if (likely(time_before(jiffies, timestamp + HZ/10)))
813 return false;
814
815 if (!netif_carrier_ok(ag->dev))
816 return false;
817
818 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
819 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
820 return true;
821
822 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
823 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
824 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
825 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
826 return true;
827
828 return false;
829 }
830
831 static int ag71xx_tx_packets(struct ag71xx *ag)
832 {
833 struct ag71xx_ring *ring = &ag->tx_ring;
834 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
835 int sent = 0;
836 int bytes_compl = 0;
837
838 DBG("%s: processing TX ring\n", ag->dev->name);
839
840 while (ring->dirty != ring->curr) {
841 unsigned int i = ring->dirty % ring->size;
842 struct ag71xx_desc *desc = ring->buf[i].desc;
843 struct sk_buff *skb = ring->buf[i].skb;
844 int len = ring->buf[i].len;
845
846 if (!ag71xx_desc_empty(desc)) {
847 if (pdata->is_ar7240 &&
848 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
849 schedule_work(&ag->restart_work);
850 break;
851 }
852
853 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
854
855 bytes_compl += len;
856 ag->dev->stats.tx_bytes += len;
857 ag->dev->stats.tx_packets++;
858
859 dev_kfree_skb_any(skb);
860 ring->buf[i].skb = NULL;
861
862 ring->dirty++;
863 sent++;
864 }
865
866 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
867
868 if (!sent)
869 return 0;
870
871 netdev_completed_queue(ag->dev, sent, bytes_compl);
872 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
873 netif_wake_queue(ag->dev);
874
875 return sent;
876 }
877
878 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
879 {
880 struct net_device *dev = ag->dev;
881 struct ag71xx_ring *ring = &ag->rx_ring;
882 int offset = ag71xx_buffer_offset(ag);
883 unsigned int pktlen_mask = ag->desc_pktlen_mask;
884 int done = 0;
885
886 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
887 dev->name, limit, ring->curr, ring->dirty);
888
889 while (done < limit) {
890 unsigned int i = ring->curr % ring->size;
891 struct ag71xx_desc *desc = ring->buf[i].desc;
892 struct sk_buff *skb;
893 int pktlen;
894 int err = 0;
895
896 if (ag71xx_desc_empty(desc))
897 break;
898
899 if ((ring->dirty + ring->size) == ring->curr) {
900 ag71xx_assert(0);
901 break;
902 }
903
904 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
905
906 pktlen = desc->ctrl & pktlen_mask;
907 pktlen -= ETH_FCS_LEN;
908
909 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
910 ag->rx_buf_size, DMA_FROM_DEVICE);
911
912 dev->stats.rx_packets++;
913 dev->stats.rx_bytes += pktlen;
914
915 skb = build_skb(ring->buf[i].rx_buf, 0);
916 if (!skb) {
917 kfree(ring->buf[i].rx_buf);
918 goto next;
919 }
920
921 skb_reserve(skb, offset);
922 skb_put(skb, pktlen);
923
924 if (ag71xx_has_ar8216(ag))
925 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
926
927 if (err) {
928 dev->stats.rx_dropped++;
929 kfree_skb(skb);
930 } else {
931 skb->dev = dev;
932 skb->ip_summed = CHECKSUM_NONE;
933 skb->protocol = eth_type_trans(skb, dev);
934 netif_receive_skb(skb);
935 }
936
937 next:
938 ring->buf[i].rx_buf = NULL;
939 done++;
940
941 ring->curr++;
942 }
943
944 ag71xx_ring_rx_refill(ag);
945
946 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
947 dev->name, ring->curr, ring->dirty, done);
948
949 return done;
950 }
951
952 static int ag71xx_poll(struct napi_struct *napi, int limit)
953 {
954 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
955 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
956 struct net_device *dev = ag->dev;
957 struct ag71xx_ring *rx_ring;
958 unsigned long flags;
959 u32 status;
960 int tx_done;
961 int rx_done;
962
963 pdata->ddr_flush();
964 tx_done = ag71xx_tx_packets(ag);
965
966 DBG("%s: processing RX ring\n", dev->name);
967 rx_done = ag71xx_rx_packets(ag, limit);
968
969 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
970
971 rx_ring = &ag->rx_ring;
972 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
973 goto oom;
974
975 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
976 if (unlikely(status & RX_STATUS_OF)) {
977 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
978 dev->stats.rx_fifo_errors++;
979
980 /* restart RX */
981 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
982 }
983
984 if (rx_done < limit) {
985 if (status & RX_STATUS_PR)
986 goto more;
987
988 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
989 if (status & TX_STATUS_PS)
990 goto more;
991
992 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
993 dev->name, rx_done, tx_done, limit);
994
995 napi_complete(napi);
996
997 /* enable interrupts */
998 spin_lock_irqsave(&ag->lock, flags);
999 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1000 spin_unlock_irqrestore(&ag->lock, flags);
1001 return rx_done;
1002 }
1003
1004 more:
1005 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1006 dev->name, rx_done, tx_done, limit);
1007 return rx_done;
1008
1009 oom:
1010 if (netif_msg_rx_err(ag))
1011 pr_info("%s: out of memory\n", dev->name);
1012
1013 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1014 napi_complete(napi);
1015 return 0;
1016 }
1017
1018 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1019 {
1020 struct net_device *dev = dev_id;
1021 struct ag71xx *ag = netdev_priv(dev);
1022 u32 status;
1023
1024 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1025 ag71xx_dump_intr(ag, "raw", status);
1026
1027 if (unlikely(!status))
1028 return IRQ_NONE;
1029
1030 if (unlikely(status & AG71XX_INT_ERR)) {
1031 if (status & AG71XX_INT_TX_BE) {
1032 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1033 dev_err(&dev->dev, "TX BUS error\n");
1034 }
1035 if (status & AG71XX_INT_RX_BE) {
1036 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1037 dev_err(&dev->dev, "RX BUS error\n");
1038 }
1039 }
1040
1041 if (likely(status & AG71XX_INT_POLL)) {
1042 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1043 DBG("%s: enable polling mode\n", dev->name);
1044 napi_schedule(&ag->napi);
1045 }
1046
1047 ag71xx_debugfs_update_int_stats(ag, status);
1048
1049 return IRQ_HANDLED;
1050 }
1051
1052 #ifdef CONFIG_NET_POLL_CONTROLLER
1053 /*
1054 * Polling 'interrupt' - used by things like netconsole to send skbs
1055 * without having to re-enable interrupts. It's not called while
1056 * the interrupt routine is executing.
1057 */
1058 static void ag71xx_netpoll(struct net_device *dev)
1059 {
1060 disable_irq(dev->irq);
1061 ag71xx_interrupt(dev->irq, dev);
1062 enable_irq(dev->irq);
1063 }
1064 #endif
1065
1066 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1067 {
1068 struct ag71xx *ag = netdev_priv(dev);
1069 unsigned int max_frame_len;
1070
1071 max_frame_len = ag71xx_max_frame_len(new_mtu);
1072 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1073 return -EINVAL;
1074
1075 if (netif_running(dev))
1076 return -EBUSY;
1077
1078 dev->mtu = new_mtu;
1079 return 0;
1080 }
1081
1082 static const struct net_device_ops ag71xx_netdev_ops = {
1083 .ndo_open = ag71xx_open,
1084 .ndo_stop = ag71xx_stop,
1085 .ndo_start_xmit = ag71xx_hard_start_xmit,
1086 .ndo_do_ioctl = ag71xx_do_ioctl,
1087 .ndo_tx_timeout = ag71xx_tx_timeout,
1088 .ndo_change_mtu = ag71xx_change_mtu,
1089 .ndo_set_mac_address = eth_mac_addr,
1090 .ndo_validate_addr = eth_validate_addr,
1091 #ifdef CONFIG_NET_POLL_CONTROLLER
1092 .ndo_poll_controller = ag71xx_netpoll,
1093 #endif
1094 };
1095
1096 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1097 {
1098 switch (mode) {
1099 case PHY_INTERFACE_MODE_MII:
1100 return "MII";
1101 case PHY_INTERFACE_MODE_GMII:
1102 return "GMII";
1103 case PHY_INTERFACE_MODE_RMII:
1104 return "RMII";
1105 case PHY_INTERFACE_MODE_RGMII:
1106 return "RGMII";
1107 case PHY_INTERFACE_MODE_SGMII:
1108 return "SGMII";
1109 default:
1110 break;
1111 }
1112
1113 return "unknown";
1114 }
1115
1116
1117 static int ag71xx_probe(struct platform_device *pdev)
1118 {
1119 struct net_device *dev;
1120 struct resource *res;
1121 struct ag71xx *ag;
1122 struct ag71xx_platform_data *pdata;
1123 int err;
1124
1125 pdata = pdev->dev.platform_data;
1126 if (!pdata) {
1127 dev_err(&pdev->dev, "no platform data specified\n");
1128 err = -ENXIO;
1129 goto err_out;
1130 }
1131
1132 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1133 dev_err(&pdev->dev, "no MII bus device specified\n");
1134 err = -EINVAL;
1135 goto err_out;
1136 }
1137
1138 dev = alloc_etherdev(sizeof(*ag));
1139 if (!dev) {
1140 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1141 err = -ENOMEM;
1142 goto err_out;
1143 }
1144
1145 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1146 return -EINVAL;
1147
1148 SET_NETDEV_DEV(dev, &pdev->dev);
1149
1150 ag = netdev_priv(dev);
1151 ag->pdev = pdev;
1152 ag->dev = dev;
1153 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1154 AG71XX_DEFAULT_MSG_ENABLE);
1155 spin_lock_init(&ag->lock);
1156
1157 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1158 if (!res) {
1159 dev_err(&pdev->dev, "no mac_base resource found\n");
1160 err = -ENXIO;
1161 goto err_out;
1162 }
1163
1164 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1165 if (!ag->mac_base) {
1166 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1167 err = -ENOMEM;
1168 goto err_free_dev;
1169 }
1170
1171 dev->irq = platform_get_irq(pdev, 0);
1172 err = request_irq(dev->irq, ag71xx_interrupt,
1173 IRQF_DISABLED,
1174 dev->name, dev);
1175 if (err) {
1176 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1177 goto err_unmap_base;
1178 }
1179
1180 dev->base_addr = (unsigned long)ag->mac_base;
1181 dev->netdev_ops = &ag71xx_netdev_ops;
1182 dev->ethtool_ops = &ag71xx_ethtool_ops;
1183
1184 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1185
1186 init_timer(&ag->oom_timer);
1187 ag->oom_timer.data = (unsigned long) dev;
1188 ag->oom_timer.function = ag71xx_oom_timer_handler;
1189
1190 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1191 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1192
1193 ag->max_frame_len = pdata->max_frame_len;
1194 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1195
1196 ag->stop_desc = dma_alloc_coherent(NULL,
1197 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1198
1199 if (!ag->stop_desc)
1200 goto err_free_irq;
1201
1202 ag->stop_desc->data = 0;
1203 ag->stop_desc->ctrl = 0;
1204 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1205
1206 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1207
1208 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1209
1210 ag71xx_dump_regs(ag);
1211
1212 ag71xx_hw_init(ag);
1213
1214 ag71xx_dump_regs(ag);
1215
1216 err = ag71xx_phy_connect(ag);
1217 if (err)
1218 goto err_free_desc;
1219
1220 err = ag71xx_debugfs_init(ag);
1221 if (err)
1222 goto err_phy_disconnect;
1223
1224 platform_set_drvdata(pdev, dev);
1225
1226 err = register_netdev(dev);
1227 if (err) {
1228 dev_err(&pdev->dev, "unable to register net device\n");
1229 goto err_debugfs_exit;
1230 }
1231
1232 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1233 dev->name, dev->base_addr, dev->irq,
1234 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1235
1236 return 0;
1237
1238 err_debugfs_exit:
1239 ag71xx_debugfs_exit(ag);
1240 err_phy_disconnect:
1241 ag71xx_phy_disconnect(ag);
1242 err_free_desc:
1243 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1244 ag->stop_desc_dma);
1245 err_free_irq:
1246 free_irq(dev->irq, dev);
1247 err_unmap_base:
1248 iounmap(ag->mac_base);
1249 err_free_dev:
1250 kfree(dev);
1251 err_out:
1252 platform_set_drvdata(pdev, NULL);
1253 return err;
1254 }
1255
1256 static int ag71xx_remove(struct platform_device *pdev)
1257 {
1258 struct net_device *dev = platform_get_drvdata(pdev);
1259
1260 if (dev) {
1261 struct ag71xx *ag = netdev_priv(dev);
1262
1263 ag71xx_debugfs_exit(ag);
1264 ag71xx_phy_disconnect(ag);
1265 unregister_netdev(dev);
1266 free_irq(dev->irq, dev);
1267 iounmap(ag->mac_base);
1268 kfree(dev);
1269 platform_set_drvdata(pdev, NULL);
1270 }
1271
1272 return 0;
1273 }
1274
1275 static struct platform_driver ag71xx_driver = {
1276 .probe = ag71xx_probe,
1277 .remove = ag71xx_remove,
1278 .driver = {
1279 .name = AG71XX_DRV_NAME,
1280 }
1281 };
1282
1283 static int __init ag71xx_module_init(void)
1284 {
1285 int ret;
1286
1287 ret = ag71xx_debugfs_root_init();
1288 if (ret)
1289 goto err_out;
1290
1291 ret = ag71xx_mdio_driver_init();
1292 if (ret)
1293 goto err_debugfs_exit;
1294
1295 ret = platform_driver_register(&ag71xx_driver);
1296 if (ret)
1297 goto err_mdio_exit;
1298
1299 return 0;
1300
1301 err_mdio_exit:
1302 ag71xx_mdio_driver_exit();
1303 err_debugfs_exit:
1304 ag71xx_debugfs_root_exit();
1305 err_out:
1306 return ret;
1307 }
1308
1309 static void __exit ag71xx_module_exit(void)
1310 {
1311 platform_driver_unregister(&ag71xx_driver);
1312 ag71xx_mdio_driver_exit();
1313 ag71xx_debugfs_root_exit();
1314 }
1315
1316 module_init(ag71xx_module_init);
1317 module_exit(ag71xx_module_exit);
1318
1319 MODULE_VERSION(AG71XX_DRV_VERSION);
1320 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1321 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1322 MODULE_LICENSE("GPL v2");
1323 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository