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ar71xx: ag71xx: add BQL support
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137 u32 bytes_compl = 0, pkts_compl = 0;
138
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % ring->size;
141
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
145 }
146
147 if (ring->buf[i].skb) {
148 bytes_compl += ring->buf[i].skb->len;
149 pkts_compl++;
150 dev_kfree_skb_any(ring->buf[i].skb);
151 }
152 ring->buf[i].skb = NULL;
153 ring->dirty++;
154 }
155
156 /* flush descriptors */
157 wmb();
158
159 netdev_completed_queue(dev, pkts_compl, bytes_compl);
160 }
161
162 static void ag71xx_ring_tx_init(struct ag71xx *ag)
163 {
164 struct ag71xx_ring *ring = &ag->tx_ring;
165 int i;
166
167 for (i = 0; i < ring->size; i++) {
168 ring->buf[i].desc->next = (u32) (ring->descs_dma +
169 ring->desc_size * ((i + 1) % ring->size));
170
171 ring->buf[i].desc->ctrl = DESC_EMPTY;
172 ring->buf[i].skb = NULL;
173 }
174
175 /* flush descriptors */
176 wmb();
177
178 ring->curr = 0;
179 ring->dirty = 0;
180 netdev_reset_queue(ag->dev);
181 }
182
183 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
184 {
185 struct ag71xx_ring *ring = &ag->rx_ring;
186 int i;
187
188 if (!ring->buf)
189 return;
190
191 for (i = 0; i < ring->size; i++)
192 if (ring->buf[i].skb) {
193 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
194 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
195 kfree_skb(ring->buf[i].skb);
196 }
197 }
198
199 static int ag71xx_rx_reserve(struct ag71xx *ag)
200 {
201 int reserve = 0;
202
203 if (ag71xx_get_pdata(ag)->is_ar724x) {
204 if (!ag71xx_has_ar8216(ag))
205 reserve = 2;
206
207 if (ag->phy_dev)
208 reserve += 4 - (ag->phy_dev->pkt_align % 4);
209
210 reserve %= 4;
211 }
212
213 return reserve + AG71XX_RX_PKT_RESERVE;
214 }
215
216
217 static int ag71xx_ring_rx_init(struct ag71xx *ag)
218 {
219 struct ag71xx_ring *ring = &ag->rx_ring;
220 unsigned int reserve = ag71xx_rx_reserve(ag);
221 unsigned int i;
222 int ret;
223
224 ret = 0;
225 for (i = 0; i < ring->size; i++) {
226 ring->buf[i].desc->next = (u32) (ring->descs_dma +
227 ring->desc_size * ((i + 1) % ring->size));
228
229 DBG("ag71xx: RX desc at %p, next is %08x\n",
230 ring->buf[i].desc,
231 ring->buf[i].desc->next);
232 }
233
234 for (i = 0; i < ring->size; i++) {
235 struct sk_buff *skb;
236 dma_addr_t dma_addr;
237
238 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
239 if (!skb) {
240 ret = -ENOMEM;
241 break;
242 }
243
244 skb->dev = ag->dev;
245 skb_reserve(skb, reserve);
246
247 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
248 AG71XX_RX_PKT_SIZE,
249 DMA_FROM_DEVICE);
250 ring->buf[i].skb = skb;
251 ring->buf[i].dma_addr = dma_addr;
252 ring->buf[i].desc->data = (u32) dma_addr;
253 ring->buf[i].desc->ctrl = DESC_EMPTY;
254 }
255
256 /* flush descriptors */
257 wmb();
258
259 ring->curr = 0;
260 ring->dirty = 0;
261
262 return ret;
263 }
264
265 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
266 {
267 struct ag71xx_ring *ring = &ag->rx_ring;
268 unsigned int reserve = ag71xx_rx_reserve(ag);
269 unsigned int count;
270
271 count = 0;
272 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
273 unsigned int i;
274
275 i = ring->dirty % ring->size;
276
277 if (ring->buf[i].skb == NULL) {
278 dma_addr_t dma_addr;
279 struct sk_buff *skb;
280
281 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
282 if (skb == NULL)
283 break;
284
285 skb_reserve(skb, reserve);
286 skb->dev = ag->dev;
287
288 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
289 AG71XX_RX_PKT_SIZE,
290 DMA_FROM_DEVICE);
291
292 ring->buf[i].skb = skb;
293 ring->buf[i].dma_addr = dma_addr;
294 ring->buf[i].desc->data = (u32) dma_addr;
295 }
296
297 ring->buf[i].desc->ctrl = DESC_EMPTY;
298 count++;
299 }
300
301 /* flush descriptors */
302 wmb();
303
304 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
305
306 return count;
307 }
308
309 static int ag71xx_rings_init(struct ag71xx *ag)
310 {
311 int ret;
312
313 ret = ag71xx_ring_alloc(&ag->tx_ring);
314 if (ret)
315 return ret;
316
317 ag71xx_ring_tx_init(ag);
318
319 ret = ag71xx_ring_alloc(&ag->rx_ring);
320 if (ret)
321 return ret;
322
323 ret = ag71xx_ring_rx_init(ag);
324 return ret;
325 }
326
327 static void ag71xx_rings_cleanup(struct ag71xx *ag)
328 {
329 ag71xx_ring_rx_clean(ag);
330 ag71xx_ring_free(&ag->rx_ring);
331
332 ag71xx_ring_tx_clean(ag);
333 netdev_reset_queue(ag->dev);
334 ag71xx_ring_free(&ag->tx_ring);
335 }
336
337 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
338 {
339 switch (ag->speed) {
340 case SPEED_1000:
341 return "1000";
342 case SPEED_100:
343 return "100";
344 case SPEED_10:
345 return "10";
346 }
347
348 return "?";
349 }
350
351 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
352 {
353 u32 t;
354
355 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
356 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
357
358 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
359
360 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
361 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
362 }
363
364 static void ag71xx_dma_reset(struct ag71xx *ag)
365 {
366 u32 val;
367 int i;
368
369 ag71xx_dump_dma_regs(ag);
370
371 /* stop RX and TX */
372 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
373 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
374
375 /*
376 * give the hardware some time to really stop all rx/tx activity
377 * clearing the descriptors too early causes random memory corruption
378 */
379 mdelay(1);
380
381 /* clear descriptor addresses */
382 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
383 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
384
385 /* clear pending RX/TX interrupts */
386 for (i = 0; i < 256; i++) {
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
389 }
390
391 /* clear pending errors */
392 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
393 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
394
395 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
396 if (val)
397 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
398 ag->dev->name, val);
399
400 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
401
402 /* mask out reserved bits */
403 val &= ~0xff000000;
404
405 if (val)
406 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
407 ag->dev->name, val);
408
409 ag71xx_dump_dma_regs(ag);
410 }
411
412 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
413 MAC_CFG1_SRX | MAC_CFG1_STX)
414
415 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
416
417 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
418 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
419 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
420 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
421 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
422 FIFO_CFG4_VT)
423
424 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
425 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
426 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
427 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
428 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
429 FIFO_CFG5_17 | FIFO_CFG5_SF)
430
431 static void ag71xx_hw_stop(struct ag71xx *ag)
432 {
433 /* disable all interrupts and stop the rx/tx engine */
434 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
435 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
436 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
437 }
438
439 static void ag71xx_hw_setup(struct ag71xx *ag)
440 {
441 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
442
443 /* setup MAC configuration registers */
444 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
445
446 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
447 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
448
449 /* setup max frame length */
450 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
451
452 /* setup FIFO configuration registers */
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
454 if (pdata->is_ar724x) {
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
457 } else {
458 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
459 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
460 }
461 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
462 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
463 }
464
465 static void ag71xx_hw_init(struct ag71xx *ag)
466 {
467 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
468 u32 reset_mask = pdata->reset_bit;
469
470 ag71xx_hw_stop(ag);
471
472 if (pdata->is_ar724x) {
473 u32 reset_phy = reset_mask;
474
475 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
476 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
477
478 ath79_device_reset_set(reset_phy);
479 mdelay(50);
480 ath79_device_reset_clear(reset_phy);
481 mdelay(200);
482 }
483
484 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
485 udelay(20);
486
487 ath79_device_reset_set(reset_mask);
488 mdelay(100);
489 ath79_device_reset_clear(reset_mask);
490 mdelay(200);
491
492 ag71xx_hw_setup(ag);
493
494 ag71xx_dma_reset(ag);
495 }
496
497 static void ag71xx_fast_reset(struct ag71xx *ag)
498 {
499 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
500 struct net_device *dev = ag->dev;
501 u32 reset_mask = pdata->reset_bit;
502 u32 rx_ds, tx_ds;
503 u32 mii_reg;
504
505 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
506
507 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
508 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
509 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
510
511 ath79_device_reset_set(reset_mask);
512 udelay(10);
513 ath79_device_reset_clear(reset_mask);
514 udelay(10);
515
516 ag71xx_dma_reset(ag);
517 ag71xx_hw_setup(ag);
518
519 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
520 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
521 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
522
523 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
524 }
525
526 static void ag71xx_hw_start(struct ag71xx *ag)
527 {
528 /* start RX engine */
529 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
530
531 /* enable interrupts */
532 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
533 }
534
535 void ag71xx_link_adjust(struct ag71xx *ag)
536 {
537 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
538 u32 cfg2;
539 u32 ifctl;
540 u32 fifo5;
541
542 if (!ag->link) {
543 ag71xx_hw_stop(ag);
544 netif_carrier_off(ag->dev);
545 if (netif_msg_link(ag))
546 pr_info("%s: link down\n", ag->dev->name);
547 return;
548 }
549
550 if (pdata->is_ar724x)
551 ag71xx_fast_reset(ag);
552
553 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
554 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
555 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
556
557 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
558 ifctl &= ~(MAC_IFCTL_SPEED);
559
560 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
561 fifo5 &= ~FIFO_CFG5_BM;
562
563 switch (ag->speed) {
564 case SPEED_1000:
565 cfg2 |= MAC_CFG2_IF_1000;
566 fifo5 |= FIFO_CFG5_BM;
567 break;
568 case SPEED_100:
569 cfg2 |= MAC_CFG2_IF_10_100;
570 ifctl |= MAC_IFCTL_SPEED;
571 break;
572 case SPEED_10:
573 cfg2 |= MAC_CFG2_IF_10_100;
574 break;
575 default:
576 BUG();
577 return;
578 }
579
580 if (pdata->is_ar91xx)
581 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
582 else if (pdata->is_ar724x)
583 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
584 else
585 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
586
587 if (pdata->set_speed)
588 pdata->set_speed(ag->speed);
589
590 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
591 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
592 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
593 ag71xx_hw_start(ag);
594
595 netif_carrier_on(ag->dev);
596 if (netif_msg_link(ag))
597 pr_info("%s: link up (%sMbps/%s duplex)\n",
598 ag->dev->name,
599 ag71xx_speed_str(ag),
600 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
601
602 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
603 ag->dev->name,
604 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
605 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
606 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
607
608 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
609 ag->dev->name,
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
611 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
612 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
613
614 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
615 ag->dev->name,
616 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
617 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
618 }
619
620 static int ag71xx_open(struct net_device *dev)
621 {
622 struct ag71xx *ag = netdev_priv(dev);
623 int ret;
624
625 ret = ag71xx_rings_init(ag);
626 if (ret)
627 goto err;
628
629 napi_enable(&ag->napi);
630
631 netif_carrier_off(dev);
632 ag71xx_phy_start(ag);
633
634 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
635 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
636
637 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
638
639 netif_start_queue(dev);
640
641 return 0;
642
643 err:
644 ag71xx_rings_cleanup(ag);
645 return ret;
646 }
647
648 static int ag71xx_stop(struct net_device *dev)
649 {
650 struct ag71xx *ag = netdev_priv(dev);
651 unsigned long flags;
652
653 netif_carrier_off(dev);
654 ag71xx_phy_stop(ag);
655
656 spin_lock_irqsave(&ag->lock, flags);
657
658 netif_stop_queue(dev);
659
660 ag71xx_hw_stop(ag);
661 ag71xx_dma_reset(ag);
662
663 napi_disable(&ag->napi);
664 del_timer_sync(&ag->oom_timer);
665
666 spin_unlock_irqrestore(&ag->lock, flags);
667
668 ag71xx_rings_cleanup(ag);
669
670 return 0;
671 }
672
673 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
674 struct net_device *dev)
675 {
676 struct ag71xx *ag = netdev_priv(dev);
677 struct ag71xx_ring *ring = &ag->tx_ring;
678 struct ag71xx_desc *desc;
679 dma_addr_t dma_addr;
680 int i;
681
682 i = ring->curr % ring->size;
683 desc = ring->buf[i].desc;
684
685 if (!ag71xx_desc_empty(desc))
686 goto err_drop;
687
688 if (ag71xx_has_ar8216(ag))
689 ag71xx_add_ar8216_header(ag, skb);
690
691 if (skb->len <= 0) {
692 DBG("%s: packet len is too small\n", ag->dev->name);
693 goto err_drop;
694 }
695
696 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
697 DMA_TO_DEVICE);
698
699 netdev_sent_queue(dev, skb->len);
700 ring->buf[i].skb = skb;
701 ring->buf[i].timestamp = jiffies;
702
703 /* setup descriptor fields */
704 desc->data = (u32) dma_addr;
705 desc->ctrl = (skb->len & DESC_PKTLEN_M);
706
707 /* flush descriptor */
708 wmb();
709
710 ring->curr++;
711 if (ring->curr == (ring->dirty + ring->size)) {
712 DBG("%s: tx queue full\n", ag->dev->name);
713 netif_stop_queue(dev);
714 }
715
716 DBG("%s: packet injected into TX queue\n", ag->dev->name);
717
718 /* enable TX engine */
719 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
720
721 return NETDEV_TX_OK;
722
723 err_drop:
724 dev->stats.tx_dropped++;
725
726 dev_kfree_skb(skb);
727 return NETDEV_TX_OK;
728 }
729
730 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
731 {
732 struct ag71xx *ag = netdev_priv(dev);
733 int ret;
734
735 switch (cmd) {
736 case SIOCETHTOOL:
737 if (ag->phy_dev == NULL)
738 break;
739
740 spin_lock_irq(&ag->lock);
741 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
742 spin_unlock_irq(&ag->lock);
743 return ret;
744
745 case SIOCSIFHWADDR:
746 if (copy_from_user
747 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
748 return -EFAULT;
749 return 0;
750
751 case SIOCGIFHWADDR:
752 if (copy_to_user
753 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
754 return -EFAULT;
755 return 0;
756
757 case SIOCGMIIPHY:
758 case SIOCGMIIREG:
759 case SIOCSMIIREG:
760 if (ag->phy_dev == NULL)
761 break;
762
763 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
764
765 default:
766 break;
767 }
768
769 return -EOPNOTSUPP;
770 }
771
772 static void ag71xx_oom_timer_handler(unsigned long data)
773 {
774 struct net_device *dev = (struct net_device *) data;
775 struct ag71xx *ag = netdev_priv(dev);
776
777 napi_schedule(&ag->napi);
778 }
779
780 static void ag71xx_tx_timeout(struct net_device *dev)
781 {
782 struct ag71xx *ag = netdev_priv(dev);
783
784 if (netif_msg_tx_err(ag))
785 pr_info("%s: tx timeout\n", ag->dev->name);
786
787 schedule_work(&ag->restart_work);
788 }
789
790 static void ag71xx_restart_work_func(struct work_struct *work)
791 {
792 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
793
794 if (ag71xx_get_pdata(ag)->is_ar724x) {
795 ag->link = 0;
796 ag71xx_link_adjust(ag);
797 return;
798 }
799
800 ag71xx_stop(ag->dev);
801 ag71xx_open(ag->dev);
802 }
803
804 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
805 {
806 u32 rx_sm, tx_sm, rx_fd;
807
808 if (likely(time_before(jiffies, timestamp + HZ/10)))
809 return false;
810
811 if (!netif_carrier_ok(ag->dev))
812 return false;
813
814 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
815 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
816 return true;
817
818 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
819 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
820 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
821 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
822 return true;
823
824 return false;
825 }
826
827 static int ag71xx_tx_packets(struct ag71xx *ag)
828 {
829 struct ag71xx_ring *ring = &ag->tx_ring;
830 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
831 int sent = 0;
832 int bytes_compl = 0;
833
834 DBG("%s: processing TX ring\n", ag->dev->name);
835
836 while (ring->dirty != ring->curr) {
837 unsigned int i = ring->dirty % ring->size;
838 struct ag71xx_desc *desc = ring->buf[i].desc;
839 struct sk_buff *skb = ring->buf[i].skb;
840
841 if (!ag71xx_desc_empty(desc)) {
842 if (pdata->is_ar7240 &&
843 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
844 schedule_work(&ag->restart_work);
845 break;
846 }
847
848 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
849
850 bytes_compl += skb->len;
851 ag->dev->stats.tx_bytes += skb->len;
852 ag->dev->stats.tx_packets++;
853
854 dev_kfree_skb_any(skb);
855 ring->buf[i].skb = NULL;
856
857 ring->dirty++;
858 sent++;
859 }
860
861 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
862
863 netdev_completed_queue(ag->dev, sent, bytes_compl);
864 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
865 netif_wake_queue(ag->dev);
866
867 return sent;
868 }
869
870 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
871 {
872 struct net_device *dev = ag->dev;
873 struct ag71xx_ring *ring = &ag->rx_ring;
874 int done = 0;
875
876 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
877 dev->name, limit, ring->curr, ring->dirty);
878
879 while (done < limit) {
880 unsigned int i = ring->curr % ring->size;
881 struct ag71xx_desc *desc = ring->buf[i].desc;
882 struct sk_buff *skb;
883 int pktlen;
884 int err = 0;
885
886 if (ag71xx_desc_empty(desc))
887 break;
888
889 if ((ring->dirty + ring->size) == ring->curr) {
890 ag71xx_assert(0);
891 break;
892 }
893
894 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
895
896 skb = ring->buf[i].skb;
897 pktlen = ag71xx_desc_pktlen(desc);
898 pktlen -= ETH_FCS_LEN;
899
900 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
901 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
902
903 dev->last_rx = jiffies;
904 dev->stats.rx_packets++;
905 dev->stats.rx_bytes += pktlen;
906
907 skb_put(skb, pktlen);
908 if (ag71xx_has_ar8216(ag))
909 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
910
911 if (err) {
912 dev->stats.rx_dropped++;
913 kfree_skb(skb);
914 } else {
915 skb->dev = dev;
916 skb->ip_summed = CHECKSUM_NONE;
917 if (ag->phy_dev) {
918 ag->phy_dev->netif_receive_skb(skb);
919 } else {
920 skb->protocol = eth_type_trans(skb, dev);
921 netif_receive_skb(skb);
922 }
923 }
924
925 ring->buf[i].skb = NULL;
926 done++;
927
928 ring->curr++;
929 }
930
931 ag71xx_ring_rx_refill(ag);
932
933 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
934 dev->name, ring->curr, ring->dirty, done);
935
936 return done;
937 }
938
939 static int ag71xx_poll(struct napi_struct *napi, int limit)
940 {
941 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
942 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
943 struct net_device *dev = ag->dev;
944 struct ag71xx_ring *rx_ring;
945 unsigned long flags;
946 u32 status;
947 int tx_done;
948 int rx_done;
949
950 pdata->ddr_flush();
951 tx_done = ag71xx_tx_packets(ag);
952
953 DBG("%s: processing RX ring\n", dev->name);
954 rx_done = ag71xx_rx_packets(ag, limit);
955
956 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
957
958 rx_ring = &ag->rx_ring;
959 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
960 goto oom;
961
962 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
963 if (unlikely(status & RX_STATUS_OF)) {
964 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
965 dev->stats.rx_fifo_errors++;
966
967 /* restart RX */
968 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
969 }
970
971 if (rx_done < limit) {
972 if (status & RX_STATUS_PR)
973 goto more;
974
975 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
976 if (status & TX_STATUS_PS)
977 goto more;
978
979 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
980 dev->name, rx_done, tx_done, limit);
981
982 napi_complete(napi);
983
984 /* enable interrupts */
985 spin_lock_irqsave(&ag->lock, flags);
986 ag71xx_int_enable(ag, AG71XX_INT_POLL);
987 spin_unlock_irqrestore(&ag->lock, flags);
988 return rx_done;
989 }
990
991 more:
992 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
993 dev->name, rx_done, tx_done, limit);
994 return rx_done;
995
996 oom:
997 if (netif_msg_rx_err(ag))
998 pr_info("%s: out of memory\n", dev->name);
999
1000 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1001 napi_complete(napi);
1002 return 0;
1003 }
1004
1005 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1006 {
1007 struct net_device *dev = dev_id;
1008 struct ag71xx *ag = netdev_priv(dev);
1009 u32 status;
1010
1011 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1012 ag71xx_dump_intr(ag, "raw", status);
1013
1014 if (unlikely(!status))
1015 return IRQ_NONE;
1016
1017 if (unlikely(status & AG71XX_INT_ERR)) {
1018 if (status & AG71XX_INT_TX_BE) {
1019 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1020 dev_err(&dev->dev, "TX BUS error\n");
1021 }
1022 if (status & AG71XX_INT_RX_BE) {
1023 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1024 dev_err(&dev->dev, "RX BUS error\n");
1025 }
1026 }
1027
1028 if (likely(status & AG71XX_INT_POLL)) {
1029 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1030 DBG("%s: enable polling mode\n", dev->name);
1031 napi_schedule(&ag->napi);
1032 }
1033
1034 ag71xx_debugfs_update_int_stats(ag, status);
1035
1036 return IRQ_HANDLED;
1037 }
1038
1039 #ifdef CONFIG_NET_POLL_CONTROLLER
1040 /*
1041 * Polling 'interrupt' - used by things like netconsole to send skbs
1042 * without having to re-enable interrupts. It's not called while
1043 * the interrupt routine is executing.
1044 */
1045 static void ag71xx_netpoll(struct net_device *dev)
1046 {
1047 disable_irq(dev->irq);
1048 ag71xx_interrupt(dev->irq, dev);
1049 enable_irq(dev->irq);
1050 }
1051 #endif
1052
1053 static const struct net_device_ops ag71xx_netdev_ops = {
1054 .ndo_open = ag71xx_open,
1055 .ndo_stop = ag71xx_stop,
1056 .ndo_start_xmit = ag71xx_hard_start_xmit,
1057 .ndo_do_ioctl = ag71xx_do_ioctl,
1058 .ndo_tx_timeout = ag71xx_tx_timeout,
1059 .ndo_change_mtu = eth_change_mtu,
1060 .ndo_set_mac_address = eth_mac_addr,
1061 .ndo_validate_addr = eth_validate_addr,
1062 #ifdef CONFIG_NET_POLL_CONTROLLER
1063 .ndo_poll_controller = ag71xx_netpoll,
1064 #endif
1065 };
1066
1067 static int __devinit ag71xx_probe(struct platform_device *pdev)
1068 {
1069 struct net_device *dev;
1070 struct resource *res;
1071 struct ag71xx *ag;
1072 struct ag71xx_platform_data *pdata;
1073 int err;
1074
1075 pdata = pdev->dev.platform_data;
1076 if (!pdata) {
1077 dev_err(&pdev->dev, "no platform data specified\n");
1078 err = -ENXIO;
1079 goto err_out;
1080 }
1081
1082 if (pdata->mii_bus_dev == NULL) {
1083 dev_err(&pdev->dev, "no MII bus device specified\n");
1084 err = -EINVAL;
1085 goto err_out;
1086 }
1087
1088 dev = alloc_etherdev(sizeof(*ag));
1089 if (!dev) {
1090 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1091 err = -ENOMEM;
1092 goto err_out;
1093 }
1094
1095 SET_NETDEV_DEV(dev, &pdev->dev);
1096
1097 ag = netdev_priv(dev);
1098 ag->pdev = pdev;
1099 ag->dev = dev;
1100 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1101 AG71XX_DEFAULT_MSG_ENABLE);
1102 spin_lock_init(&ag->lock);
1103
1104 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1105 if (!res) {
1106 dev_err(&pdev->dev, "no mac_base resource found\n");
1107 err = -ENXIO;
1108 goto err_out;
1109 }
1110
1111 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1112 if (!ag->mac_base) {
1113 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1114 err = -ENOMEM;
1115 goto err_free_dev;
1116 }
1117
1118 dev->irq = platform_get_irq(pdev, 0);
1119 err = request_irq(dev->irq, ag71xx_interrupt,
1120 IRQF_DISABLED,
1121 dev->name, dev);
1122 if (err) {
1123 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1124 goto err_unmap_base;
1125 }
1126
1127 dev->base_addr = (unsigned long)ag->mac_base;
1128 dev->netdev_ops = &ag71xx_netdev_ops;
1129 dev->ethtool_ops = &ag71xx_ethtool_ops;
1130
1131 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1132
1133 init_timer(&ag->oom_timer);
1134 ag->oom_timer.data = (unsigned long) dev;
1135 ag->oom_timer.function = ag71xx_oom_timer_handler;
1136
1137 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1138 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1139
1140 ag->stop_desc = dma_alloc_coherent(NULL,
1141 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1142
1143 if (!ag->stop_desc)
1144 goto err_free_irq;
1145
1146 ag->stop_desc->data = 0;
1147 ag->stop_desc->ctrl = 0;
1148 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1149
1150 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1151
1152 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1153
1154 err = register_netdev(dev);
1155 if (err) {
1156 dev_err(&pdev->dev, "unable to register net device\n");
1157 goto err_free_desc;
1158 }
1159
1160 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1161 dev->name, dev->base_addr, dev->irq);
1162
1163 ag71xx_dump_regs(ag);
1164
1165 ag71xx_hw_init(ag);
1166
1167 ag71xx_dump_regs(ag);
1168
1169 err = ag71xx_phy_connect(ag);
1170 if (err)
1171 goto err_unregister_netdev;
1172
1173 err = ag71xx_debugfs_init(ag);
1174 if (err)
1175 goto err_phy_disconnect;
1176
1177 platform_set_drvdata(pdev, dev);
1178
1179 return 0;
1180
1181 err_phy_disconnect:
1182 ag71xx_phy_disconnect(ag);
1183 err_unregister_netdev:
1184 unregister_netdev(dev);
1185 err_free_desc:
1186 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1187 ag->stop_desc_dma);
1188 err_free_irq:
1189 free_irq(dev->irq, dev);
1190 err_unmap_base:
1191 iounmap(ag->mac_base);
1192 err_free_dev:
1193 kfree(dev);
1194 err_out:
1195 platform_set_drvdata(pdev, NULL);
1196 return err;
1197 }
1198
1199 static int __devexit ag71xx_remove(struct platform_device *pdev)
1200 {
1201 struct net_device *dev = platform_get_drvdata(pdev);
1202
1203 if (dev) {
1204 struct ag71xx *ag = netdev_priv(dev);
1205
1206 ag71xx_debugfs_exit(ag);
1207 ag71xx_phy_disconnect(ag);
1208 unregister_netdev(dev);
1209 free_irq(dev->irq, dev);
1210 iounmap(ag->mac_base);
1211 kfree(dev);
1212 platform_set_drvdata(pdev, NULL);
1213 }
1214
1215 return 0;
1216 }
1217
1218 static struct platform_driver ag71xx_driver = {
1219 .probe = ag71xx_probe,
1220 .remove = __exit_p(ag71xx_remove),
1221 .driver = {
1222 .name = AG71XX_DRV_NAME,
1223 }
1224 };
1225
1226 static int __init ag71xx_module_init(void)
1227 {
1228 int ret;
1229
1230 ret = ag71xx_debugfs_root_init();
1231 if (ret)
1232 goto err_out;
1233
1234 ret = ag71xx_mdio_driver_init();
1235 if (ret)
1236 goto err_debugfs_exit;
1237
1238 ret = platform_driver_register(&ag71xx_driver);
1239 if (ret)
1240 goto err_mdio_exit;
1241
1242 return 0;
1243
1244 err_mdio_exit:
1245 ag71xx_mdio_driver_exit();
1246 err_debugfs_exit:
1247 ag71xx_debugfs_root_exit();
1248 err_out:
1249 return ret;
1250 }
1251
1252 static void __exit ag71xx_module_exit(void)
1253 {
1254 platform_driver_unregister(&ag71xx_driver);
1255 ag71xx_mdio_driver_exit();
1256 ag71xx_debugfs_root_exit();
1257 }
1258
1259 module_init(ag71xx_module_init);
1260 module_exit(ag71xx_module_exit);
1261
1262 MODULE_VERSION(AG71XX_DRV_VERSION);
1263 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1264 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1265 MODULE_LICENSE("GPL v2");
1266 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository