projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
rtl8366_smi: add Kconfig option for the debugfs stuff
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
29 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
30 #define RTL8366_SMI_DRIVER_VER "0.1.1"
31
32 #define RTL8366S_PHY_NO_MAX 4
33 #define RTL8366S_PHY_PAGE_MAX 7
34 #define RTL8366S_PHY_ADDR_MAX 31
35
36 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
37 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
38
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0105
46 #define RTL8366S_CHIP_ID_8366 0x8366
47
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
51
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
54
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60
61 #define RTL8366_SMI_ACK_RETRY_COUNT 5
62 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
63
64 /* LED control registers */
65 #define RTL8366_LED_BLINKRATE_REG 0x0420
66 #define RTL8366_LED_BLINKRATE_BIT 0
67 #define RTL8366_LED_BLINKRATE_MASK 0x0007
68
69 #define RTL8366_LED_CTRL_REG 0x0421
70 #define RTL8366_LED_0_1_CTRL_REG 0x0422
71 #define RTL8366_LED_2_3_CTRL_REG 0x0423
72
73 #define RTL8366S_MIB_COUNT 33
74 #define RTL8366S_GLOBAL_MIB_COUNT 1
75 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
76 #define RTL8366S_MIB_COUNTER_BASE 0x1000
77 #define RTL8366S_MIB_CTRL_REG 0x11F0
78 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
79 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
80 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
81
82 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
83 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
84 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
85
86
87 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
88 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
89 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
90
91 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
92
93 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
94 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
95 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
96
97 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
98
99
100 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
101 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
102 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
103 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
104 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
105 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
106 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
107
108
109 #define RTL8366_PORT_NUM_CPU 5
110 #define RTL8366_NUM_PORTS 6
111 #define RTL8366_NUM_VLANS 16
112 #define RTL8366_NUM_LEDGROUPS 4
113 #define RTL8366_NUM_VIDS 4096
114 #define RTL8366S_PRIORITYMAX 7
115 #define RTL8366S_FIDMAX 7
116
117
118 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
119 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
120 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
121 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
122
123 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
124 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
125
126 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
127 RTL8366_PORT_2 | \
128 RTL8366_PORT_3 | \
129 RTL8366_PORT_4 | \
130 RTL8366_PORT_UNKNOWN | \
131 RTL8366_PORT_CPU)
132
133 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
134 RTL8366_PORT_2 | \
135 RTL8366_PORT_3 | \
136 RTL8366_PORT_4 | \
137 RTL8366_PORT_UNKNOWN)
138
139 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
140 RTL8366_PORT_2 | \
141 RTL8366_PORT_3 | \
142 RTL8366_PORT_4)
143
144 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
145 RTL8366_PORT_CPU)
146
147 struct rtl8366s_vlanconfig {
148 u16 reserved2:1;
149 u16 priority:3;
150 u16 vid:12;
151
152 u16 reserved1:1;
153 u16 fid:3;
154 u16 untag:6;
155 u16 member:6;
156 };
157
158 struct rtl8366s_vlan4kentry {
159 u16 reserved1:4;
160 u16 vid:12;
161
162 u16 reserved2:1;
163 u16 fid:3;
164 u16 untag:6;
165 u16 member:6;
166 };
167
168 static const char *MIBCOUNTERS[] = { "IfInOctets ",
169 "EtherStatsOctets ",
170 "EtherStatsUnderSizePkts ",
171 "EtherFregament ",
172 "EtherStatsPkts64Octets ",
173 "EtherStatsPkts65to127Octets ",
174 "EtherStatsPkts128to255Octets ",
175 "EtherStatsPkts256to511Octets ",
176 "EtherStatsPkts512to1023Octets ",
177 "EtherStatsPkts1024to1518Octets ",
178 "EtherOversizeStats ",
179 "EtherStatsJabbers ",
180 "IfInUcastPkts ",
181 "EtherStatsMulticastPkts ",
182 "EtherStatsBroadcastPkts ",
183 "EtherStatsDropEvents ",
184 "Dot3StatsFCSErrors ",
185 "Dot3StatsSymbolErrors ",
186 "Dot3InPauseFrames ",
187 "Dot3ControlInUnknownOpcodes ",
188 "IfOutOctets ",
189 "Dot3StatsSingleCollisionFrames ",
190 "Dot3StatMultipleCollisionFrames ",
191 "Dot3sDeferredTransmissions ",
192 "Dot3StatsLateCollisions ",
193 "EtherStatsCollisions ",
194 "Dot3StatsExcessiveCollisions ",
195 "Dot3OutPauseFrames ",
196 "Dot1dBasePortDelayExceededDiscards",
197 "Dot1dTpPortInDiscards ",
198 "IfOutUcastPkts ",
199 "IfOutMulticastPkts ",
200 "IfOutBroadcastPkts ",
201 NULL };
202
203 struct rtl8366_smi {
204 struct platform_device *pdev;
205 struct rtl8366_smi_platform_data *pdata;
206 spinlock_t lock;
207 struct mii_bus *mii_bus;
208 struct switch_dev dev;
209 int mii_irq[PHY_MAX_ADDR];
210 char buf[4096];
211 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
212 struct dentry *debugfs_root;
213 #endif
214 };
215
216 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
217 u16 g_dbg_reg;
218 #endif
219
220 static inline struct rtl8366_smi *sw_to_rtl8366(struct switch_dev *sw)
221 {
222 return container_of(sw, struct rtl8366_smi, dev);
223 }
224
225 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
226 {
227 ndelay(RTL8366_SMI_CLK_DELAY);
228 }
229
230 static void rtl8366_smi_start(struct rtl8366_smi *smi)
231 {
232 unsigned int sda = smi->pdata->gpio_sda;
233 unsigned int sck = smi->pdata->gpio_sck;
234
235 /*
236 * Set GPIO pins to output mode, with initial state:
237 * SCK = 0, SDA = 1
238 */
239 gpio_direction_output(sck, 0);
240 gpio_direction_output(sda, 1);
241 rtl8366_smi_clk_delay(smi);
242
243 /* CLK 1: 0 -> 1, 1 -> 0 */
244 gpio_set_value(sck, 1);
245 rtl8366_smi_clk_delay(smi);
246 gpio_set_value(sck, 0);
247 rtl8366_smi_clk_delay(smi);
248
249 /* CLK 2: */
250 gpio_set_value(sck, 1);
251 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sda, 0);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sck, 0);
255 rtl8366_smi_clk_delay(smi);
256 gpio_set_value(sda, 1);
257 }
258
259 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
260 {
261 unsigned int sda = smi->pdata->gpio_sda;
262 unsigned int sck = smi->pdata->gpio_sck;
263
264 rtl8366_smi_clk_delay(smi);
265 gpio_set_value(sda, 0);
266 gpio_set_value(sck, 1);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sda, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sck, 1);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 0);
273 rtl8366_smi_clk_delay(smi);
274 gpio_set_value(sck, 1);
275
276 /* add a click */
277 rtl8366_smi_clk_delay(smi);
278 gpio_set_value(sck, 0);
279 rtl8366_smi_clk_delay(smi);
280 gpio_set_value(sck, 1);
281
282 /* set GPIO pins to input mode */
283 gpio_direction_input(sda);
284 gpio_direction_input(sck);
285 }
286
287 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
288 {
289 unsigned int sda = smi->pdata->gpio_sda;
290 unsigned int sck = smi->pdata->gpio_sck;
291
292 for (; len > 0; len--) {
293 rtl8366_smi_clk_delay(smi);
294
295 /* prepare data */
296 if ( data & ( 1 << (len - 1)) )
297 gpio_set_value(sda, 1);
298 else
299 gpio_set_value(sda, 0);
300 rtl8366_smi_clk_delay(smi);
301
302 /* clocking */
303 gpio_set_value(sck, 1);
304 rtl8366_smi_clk_delay(smi);
305 gpio_set_value(sck, 0);
306 }
307 }
308
309 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
310 {
311 unsigned int sda = smi->pdata->gpio_sda;
312 unsigned int sck = smi->pdata->gpio_sck;
313
314 gpio_direction_input(sda);
315
316 for (*data = 0; len > 0; len--) {
317 u32 u;
318
319 rtl8366_smi_clk_delay(smi);
320
321 /* clocking */
322 gpio_set_value(sck, 1);
323 rtl8366_smi_clk_delay(smi);
324 u = gpio_get_value(sda);
325 gpio_set_value(sck, 0);
326
327 *data |= (u << (len - 1));
328 }
329
330 gpio_direction_output(sda, 0);
331 }
332
333 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
334 {
335 int retry_cnt;
336
337 retry_cnt = 0;
338 do {
339 u32 ack;
340
341 rtl8366_smi_read_bits(smi, 1, &ack);
342 if (ack == 0)
343 break;
344
345 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
346 return -EIO;
347 } while (1);
348
349 return 0;
350 }
351
352 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
353 {
354 rtl8366_smi_write_bits(smi, data, 8);
355 return rtl8366_smi_wait_for_ack(smi);
356 }
357
358 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
359 {
360 u32 t;
361
362 /* read data */
363 rtl8366_smi_read_bits(smi, 8, &t);
364 *data = (t & 0xff);
365
366 /* send an ACK */
367 rtl8366_smi_write_bits(smi, 0x00, 1);
368
369 return 0;
370 }
371
372 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
373 {
374 u32 t;
375
376 /* read data */
377 rtl8366_smi_read_bits(smi, 8, &t);
378 *data = (t & 0xff);
379
380 /* send an ACK */
381 rtl8366_smi_write_bits(smi, 0x01, 1);
382
383 return 0;
384 }
385
386 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
387 {
388 unsigned long flags;
389 u8 lo = 0;
390 u8 hi = 0;
391 int ret;
392
393 spin_lock_irqsave(&smi->lock, flags);
394
395 rtl8366_smi_start(smi);
396
397 /* send READ command */
398 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
399 if (ret)
400 goto out;
401
402 /* set ADDR[7:0] */
403 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
404 if (ret)
405 goto out;
406
407 /* set ADDR[15:8] */
408 ret = rtl8366_smi_write_byte(smi, addr >> 8);
409 if (ret)
410 goto out;
411
412 /* read DATA[7:0] */
413 rtl8366_smi_read_byte0(smi, &lo);
414 /* read DATA[15:8] */
415 rtl8366_smi_read_byte1(smi, &hi);
416
417 *data = ((u32) lo) | (((u32) hi) << 8);
418
419 ret = 0;
420
421 out:
422 rtl8366_smi_stop(smi);
423 spin_unlock_irqrestore(&smi->lock, flags);
424
425 return ret;
426 }
427
428 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
429 {
430 unsigned long flags;
431 int ret;
432
433 spin_lock_irqsave(&smi->lock, flags);
434
435 rtl8366_smi_start(smi);
436
437 /* send WRITE command */
438 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
439 if (ret)
440 goto out;
441
442 /* set ADDR[7:0] */
443 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
444 if (ret)
445 goto out;
446
447 /* set ADDR[15:8] */
448 ret = rtl8366_smi_write_byte(smi, addr >> 8);
449 if (ret)
450 goto out;
451
452 /* write DATA[7:0] */
453 ret = rtl8366_smi_write_byte(smi, data & 0xff);
454 if (ret)
455 goto out;
456
457 /* write DATA[15:8] */
458 ret = rtl8366_smi_write_byte(smi, data >> 8);
459 if (ret)
460 goto out;
461
462 ret = 0;
463
464 out:
465 rtl8366_smi_stop(smi);
466 spin_unlock_irqrestore(&smi->lock, flags);
467
468 return ret;
469 }
470
471 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
472 u32 phy_no, u32 page, u32 addr, u32 *data)
473 {
474 u32 reg;
475 int ret;
476
477 if (phy_no > RTL8366S_PHY_NO_MAX)
478 return -EINVAL;
479
480 if (page > RTL8366S_PHY_PAGE_MAX)
481 return -EINVAL;
482
483 if (addr > RTL8366S_PHY_ADDR_MAX)
484 return -EINVAL;
485
486 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
487 RTL8366S_PHY_CTRL_READ);
488 if (ret)
489 return ret;
490
491 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
492 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
493 (addr & RTL8366S_PHY_REG_MASK);
494
495 ret = rtl8366_smi_write_reg(smi, reg, 0);
496 if (ret)
497 return ret;
498
499 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
500 if (ret)
501 return ret;
502
503 return 0;
504 }
505
506 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
507 u32 phy_no, u32 page, u32 addr, u32 data)
508 {
509 u32 reg;
510 int ret;
511
512 if (phy_no > RTL8366S_PHY_NO_MAX)
513 return -EINVAL;
514
515 if (page > RTL8366S_PHY_PAGE_MAX)
516 return -EINVAL;
517
518 if (addr > RTL8366S_PHY_ADDR_MAX)
519 return -EINVAL;
520
521 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
522 RTL8366S_PHY_CTRL_WRITE);
523 if (ret)
524 return ret;
525
526 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
527 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
528 (addr & RTL8366S_PHY_REG_MASK);
529
530 ret = rtl8366_smi_write_reg(smi, reg, data);
531 if (ret)
532 return ret;
533
534 return 0;
535 }
536
537 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
538 int port, unsigned long long *val)
539 {
540 int i;
541 int err;
542 u32 addr, data, regoffset;
543 u64 mibvalue;
544
545 /* address offset to MIBs counter */
546 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
547 2, 2, 2, 2, 2, 2, 2, 2, 2,
548 2, 2, 4, 2, 2, 2, 2, 2, 2,
549 2, 2, 2, 2, 2, 2};
550
551 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
552 return -EINVAL;
553
554 i = 0;
555 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
556
557 while (i < counter) {
558 regoffset += mibLength[i];
559 i++;
560 }
561
562 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
563
564
565 /* writing access counter address first */
566 /* then ASIC will prepare 64bits counter wait for being retrived */
567 data = 0;/* writing data will be discard by ASIC */
568 err = rtl8366_smi_write_reg(smi, addr, data);
569 if (err)
570 return err;
571
572 /* read MIB control register */
573 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
574 if (err)
575 return err;
576
577 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
578 return -EBUSY;
579
580 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
581 return -EIO;
582
583 mibvalue = 0;
584 addr = addr + mibLength[counter] - 1;
585 i = mibLength[counter];
586
587 while (i) {
588 err = rtl8366_smi_read_reg(smi, addr, &data);
589 if (err)
590 return err;
591
592 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
593
594 addr--;
595 i--;
596 }
597
598 *val = mibvalue;
599 return 0;
600 }
601
602 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
603 struct rtl8366s_vlan4kentry *vlan4k)
604 {
605 int err;
606 u32 data;
607 u16 *tableaddr;
608
609 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
610 vlan4k->vid = vid;
611
612 if (vid >= RTL8366_NUM_VIDS)
613 return -EINVAL;
614
615 tableaddr = (u16 *)vlan4k;
616
617 /* write VID */
618 data = *tableaddr;
619 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
620 if (err)
621 return err;
622
623 /* write table access control word */
624 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
625 RTL8366S_TABLE_VLAN_READ_CTRL);
626 if (err)
627 return err;
628
629 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
630 if (err)
631 return err;
632
633 *tableaddr = data;
634 tableaddr++;
635
636 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
637 &data);
638 if (err)
639 return err;
640
641 *tableaddr = data;
642 vlan4k->vid = vid;
643
644 return 0;
645 }
646
647 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
648 const struct rtl8366s_vlan4kentry *vlan4k)
649 {
650 int err;
651 u32 data;
652 u16 *tableaddr;
653
654 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
655 vlan4k->member > RTL8366_PORT_ALL ||
656 vlan4k->untag > RTL8366_PORT_ALL ||
657 vlan4k->fid > RTL8366S_FIDMAX)
658 return -EINVAL;
659
660 tableaddr = (u16 *)vlan4k;
661
662 data = *tableaddr;
663
664 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
665 if (err)
666 return err;
667
668 tableaddr++;
669
670 data = *tableaddr;
671
672 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
673 data);
674 if (err)
675 return err;
676
677 /* write table access control word */
678 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
679 RTL8366S_TABLE_VLAN_WRITE_CTRL);
680
681 return err;
682 }
683
684 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
685 struct rtl8366s_vlanconfig *vlanmc)
686 {
687 int err;
688 u32 addr;
689 u32 data;
690 u16 *tableaddr;
691
692 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
693
694 if (index >= RTL8366_NUM_VLANS)
695 return -EINVAL;
696
697 tableaddr = (u16 *)vlanmc;
698
699 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
700
701 err = rtl8366_smi_read_reg(smi, addr, &data);
702 if (err)
703 return err;
704
705 *tableaddr = data;
706 tableaddr++;
707
708 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
709
710 err = rtl8366_smi_read_reg(smi, addr, &data);
711 if (err)
712 return err;
713
714 *tableaddr = data;
715
716 return 0;
717 }
718
719 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
720 const struct rtl8366s_vlanconfig
721 *vlanmc)
722 {
723 int err;
724 u32 addr;
725 u32 data;
726 u16 *tableaddr;
727
728 if (index >= RTL8366_NUM_VLANS ||
729 vlanmc->vid >= RTL8366_NUM_VIDS ||
730 vlanmc->priority > RTL8366S_PRIORITYMAX ||
731 vlanmc->member > RTL8366_PORT_ALL ||
732 vlanmc->untag > RTL8366_PORT_ALL ||
733 vlanmc->fid > RTL8366S_FIDMAX)
734 return -EINVAL;
735
736 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
737
738
739 tableaddr = (u16 *)vlanmc;
740 data = *tableaddr;
741
742 err = rtl8366_smi_write_reg(smi, addr, data);
743 if (err)
744 return err;
745
746 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
747
748 tableaddr++;
749 data = *tableaddr;
750
751 err = rtl8366_smi_write_reg(smi, addr, data);
752 if (err)
753 return err;
754
755 return 0;
756 }
757
758 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
759 int *val)
760 {
761 int err;
762 u32 addr;
763 u32 data;
764
765 /* bits mapping to port vlan control register of port n */
766 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
767 0xF000, 0x000F, 0x00F0 };
768 /* bits offset to port vlan control register of port n */
769 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
770 /* address offset to port vlan control register of port n */
771 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
772
773 if (port >= RTL8366_NUM_PORTS)
774 return -EINVAL;
775
776 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
777
778 err = rtl8366_smi_read_reg(smi, addr, &data);
779 if (err)
780 return err;
781
782 *val = (data & bits[port]) >> bitoffset[port];
783
784 return 0;
785
786 }
787
788 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
789 int *val)
790 {
791 int err;
792 int index;
793 struct rtl8366s_vlanconfig vlanmc;
794
795 err = rtl8366_get_port_vlan_index(smi, port, &index);
796 if (err)
797 return err;
798
799 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
800 if (err)
801 return err;
802
803 *val = vlanmc.vid;
804 return 0;
805 }
806
807 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
808 int index)
809 {
810 int err;
811 u32 addr;
812 u32 data;
813 u32 vlan_data;
814 u32 bits;
815
816 /* bits mapping to port vlan control register of port n */
817 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
818 0xF000, 0x000F, 0x00F0 };
819 /* bits offset to port vlan control register of port n */
820 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
821 /* address offset to port vlan control register of port n */
822 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
823
824 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
825 return -EINVAL;
826
827 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
828
829 bits = bitmasks[port];
830
831 data = (index << bitOff[port]) & bits;
832
833 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
834 if (err)
835 return err;
836
837 vlan_data &= ~(vlan_data & bits);
838 vlan_data |= data;
839
840 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
841 if (err)
842 return err;
843
844 return 0;
845 }
846
847 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
848 int val)
849 {
850 int i;
851 struct rtl8366s_vlanconfig vlanmc;
852 struct rtl8366s_vlan4kentry vlan4k;
853
854 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
855 return -EINVAL;
856
857
858
859 /* Updating the 4K entry; lookup it and change the port member set */
860 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
861 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
862 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
863 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
864
865 /* For the 16 entries more work needs to be done. First see if such
866 VID is already there and change it */
867 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
868 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
869
870 /* Try to find an existing vid and update port member set */
871 if (val == vlanmc.vid) {
872 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
873 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
874
875 /* Now update PVID register settings */
876 rtl8366_set_port_vlan_index(smi, port, i);
877
878 return 0;
879 }
880 }
881
882 /* PVID could not be found from vlan table. Replace unused (one that
883 has no member ports) with new one */
884 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
885 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
886
887 /* See if this vlan member configuration is unused. It is
888 unused if member set contains no ports or CPU port only */
889 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
890 vlanmc.vid = val;
891 vlanmc.priority = 0;
892 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
893 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
894 vlanmc.fid = 0;
895
896 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
897
898 /* Now update PVID register settings */
899 rtl8366_set_port_vlan_index(smi, port, i);
900
901 return 0;
902 }
903 }
904
905 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
906 "use\n");
907 return -EINVAL;
908 }
909
910
911 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
912 {
913 u32 data = 0;
914 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
915
916 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
917 if (enable)
918 data |= RTL8366_CHIP_CTRL_VLAN;
919
920 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
921 }
922
923 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
924 {
925 u32 data = 0;
926 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
927
928 data &= ~(data & 1);
929 if (enable)
930 data |= 1;
931
932 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
933 }
934
935 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
936 {
937 struct rtl8366s_vlan4kentry vlan4k;
938 struct rtl8366s_vlanconfig vlanmc;
939 int err;
940 int i;
941
942 /* clear 16 VLAN member configuration */
943 vlanmc.vid = 0;
944 vlanmc.priority = 0;
945 vlanmc.member = 0;
946 vlanmc.untag = 0;
947 vlanmc.fid = 0;
948 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
949 err = rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
950 if (err)
951 return err;
952 }
953
954 /* Set a default VLAN with vid 1 to 4K table for all ports */
955 vlan4k.vid = 1;
956 vlan4k.member = RTL8366_PORT_ALL;
957 vlan4k.untag = RTL8366_PORT_ALL;
958 vlan4k.fid = 0;
959 err = rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
960 if (err)
961 return err;
962
963 /* Set all ports PVID to default VLAN */
964 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
965 err = rtl8366_set_vlan_port_pvid(smi, i, 0);
966 if (err)
967 return err;
968 }
969
970 return 0;
971 }
972
973 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
974 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
975 {
976 file->private_data = inode->i_private;
977 return 0;
978 }
979
980 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
981 char __user *user_buf,
982 size_t count, loff_t *ppos)
983 {
984 int i, j, len = 0;
985 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
986 char *buf = smi->buf;
987
988 len += snprintf(buf + len, sizeof(smi->buf) - len, "MIB Counters:\n");
989 len += snprintf(buf + len, sizeof(smi->buf) - len, "Counter"
990 " "
991 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
992 "Port 4\n");
993
994 for (i = 0; i < 33; ++i) {
995
996 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d:%s ",
997 i, MIBCOUNTERS[i]);
998 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
999 unsigned long long counter = 0;
1000
1001 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
1002 len += snprintf(buf + len, sizeof(smi->buf) - len,
1003 "[%llu]", counter);
1004 else
1005 len += snprintf(buf + len, sizeof(smi->buf) - len,
1006 "[error]");
1007
1008 if (j != RTL8366_NUM_PORTS - 1) {
1009 if (counter < 100000)
1010 len += snprintf(buf + len,
1011 sizeof(smi->buf) - len,
1012 "\t");
1013
1014 len += snprintf(buf + len, sizeof(smi->buf) - len,
1015 "\t");
1016 }
1017 }
1018 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1019 }
1020
1021 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1022
1023 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1024 }
1025
1026 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1027 char __user *user_buf,
1028 size_t count, loff_t *ppos)
1029 {
1030 int i, j, len = 0;
1031 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1032 char *buf = smi->buf;
1033
1034 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN Member Config:\n");
1035 len += snprintf(buf + len, sizeof(smi->buf) - len,
1036 "\t id \t vid \t prio \t member \t untag \t fid "
1037 "\tports\n");
1038
1039 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1040 struct rtl8366s_vlanconfig vlanmc;
1041
1042 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1043
1044 len += snprintf(buf + len, sizeof(smi->buf) - len,
1045 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1046 "\t", i, vlanmc.vid, vlanmc.priority,
1047 vlanmc.member, vlanmc.untag, vlanmc.fid);
1048
1049 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1050 int index = 0;
1051 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1052 if (index == i)
1053 len += snprintf(buf + len,
1054 sizeof(smi->buf) - len,
1055 "%d", j);
1056 }
1057 }
1058 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1059 }
1060
1061 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1062 }
1063
1064 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1065 char __user *user_buf,
1066 size_t count, loff_t *ppos)
1067 {
1068 u32 t, reg = g_dbg_reg;
1069 int err, len = 0;
1070 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1071 char *buf = smi->buf;
1072
1073 memset(buf, '\0', sizeof(smi->buf));
1074
1075 err = rtl8366_smi_read_reg(smi, reg, &t);
1076 if (err) {
1077 len += snprintf(buf, sizeof(smi->buf),
1078 "Read failed (reg: 0x%04x)\n", reg);
1079 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1080 }
1081
1082 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
1083 reg, t);
1084
1085 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1086 }
1087
1088 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1089 const char __user *user_buf,
1090 size_t count, loff_t *ppos)
1091 {
1092 unsigned long data;
1093 u32 reg = g_dbg_reg;
1094 int err;
1095 size_t len;
1096 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1097 char *buf = smi->buf;
1098
1099 len = min(count, sizeof(smi->buf) - 1);
1100 if (copy_from_user(buf, user_buf, len)) {
1101 dev_err(&smi->pdev->dev, "copy from user failed\n");
1102 return -EFAULT;
1103 }
1104
1105 buf[len] = '\0';
1106 if (len > 0 && buf[len - 1] == '\n')
1107 buf[len - 1] = '\0';
1108
1109
1110 if (strict_strtoul(buf, 16, &data)) {
1111 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1112 } else {
1113 err = rtl8366_smi_write_reg(smi, reg, data);
1114 if (err) {
1115 dev_err(&smi->pdev->dev,
1116 "writing reg 0x%04x val 0x%04lx failed\n",
1117 reg, data);
1118 }
1119 }
1120
1121 return count;
1122 }
1123
1124 static const struct file_operations fops_rtl8366_regs = {
1125 .read = rtl8366_read_debugfs_reg,
1126 .write = rtl8366_write_debugfs_reg,
1127 .open = rtl8366_debugfs_open,
1128 .owner = THIS_MODULE
1129 };
1130
1131 static const struct file_operations fops_rtl8366_vlan = {
1132 .read = rtl8366_read_debugfs_vlan,
1133 .open = rtl8366_debugfs_open,
1134 .owner = THIS_MODULE
1135 };
1136
1137 static const struct file_operations fops_rtl8366_mibs = {
1138 .read = rtl8366_read_debugfs_mibs,
1139 .open = rtl8366_debugfs_open,
1140 .owner = THIS_MODULE
1141 };
1142
1143 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1144 {
1145 struct dentry *node;
1146 struct dentry *root;
1147
1148 if (!smi->debugfs_root)
1149 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1150
1151 if (!smi->debugfs_root) {
1152 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1153 return;
1154 }
1155 root = smi->debugfs_root;
1156
1157 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1158 if (!node) {
1159 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1160 return;
1161 }
1162
1163 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1164 &fops_rtl8366_regs);
1165 if (!node) {
1166 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1167 return;
1168 }
1169
1170 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1171 &fops_rtl8366_vlan);
1172 if (!node) {
1173 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1174 "failed\n");
1175 return;
1176 }
1177
1178 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1179 &fops_rtl8366_mibs);
1180 if (!node) {
1181 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1182 "xfailed\n");
1183 return;
1184 }
1185 }
1186
1187 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1188 {
1189 if (smi->debugfs_root) {
1190 debugfs_remove_recursive(smi->debugfs_root);
1191 smi->debugfs_root = NULL;
1192 }
1193 }
1194
1195 #else
1196 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1197 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1198 #endif /* CONFIG_RTL8366_SMI_DEBUG_FS */
1199
1200 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1201 const struct switch_attr *attr,
1202 struct switch_val *val)
1203 {
1204 u32 data = 0;
1205 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1206
1207 if (val->value.i == 1) {
1208 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1209 data |= (1 << 2);
1210 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1211 }
1212
1213 return 0;
1214 }
1215
1216 static int rtl8366_get_vlan(struct switch_dev *dev,
1217 const struct switch_attr *attr,
1218 struct switch_val *val)
1219 {
1220 u32 data;
1221 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1222
1223 if (attr->ofs == 1) {
1224 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1225
1226 if (data & RTL8366_CHIP_CTRL_VLAN)
1227 val->value.i = 1;
1228 else
1229 val->value.i = 0;
1230 } else if (attr->ofs == 2) {
1231 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1232
1233 if (data & 0x0001)
1234 val->value.i = 1;
1235 else
1236 val->value.i = 0;
1237 }
1238
1239 return 0;
1240 }
1241
1242 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1243 const struct switch_attr *attr,
1244 struct switch_val *val)
1245 {
1246 u32 data;
1247 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1248 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1249
1250 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1251
1252 return 0;
1253 }
1254
1255 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1256 const struct switch_attr *attr,
1257 struct switch_val *val)
1258 {
1259 u32 data;
1260 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1261
1262 if (val->value.i >= 6)
1263 return -EINVAL;
1264
1265 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1266
1267 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1268 data |= val->value.i;
1269
1270 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1271
1272 return 0;
1273 }
1274
1275 static int rtl8366_set_vlan(struct switch_dev *dev,
1276 const struct switch_attr *attr,
1277 struct switch_val *val)
1278 {
1279 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1280
1281 if (attr->ofs == 1)
1282 return rtl8366_vlan_set_vlan(smi, val->value.i);
1283 else
1284 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1285 }
1286
1287 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1288 const struct switch_attr *attr,
1289 struct switch_val *val)
1290 {
1291 u32 len = 0, data = 0;
1292 int speed, duplex, link, txpause, rxpause, nway;
1293 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1294 char *buf = smi->buf;
1295
1296 if (val->port_vlan >= RTL8366_NUM_PORTS)
1297 return -EINVAL;
1298
1299 memset(buf, '\0', sizeof(smi->buf));
1300 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1301 (val->port_vlan >> 1),
1302 &data);
1303
1304 if (val->port_vlan & 0x1)
1305 data = data >> 8;
1306
1307 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1308 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1309 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1310 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1311 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1312 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1313
1314 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d: ",
1315 val->port_vlan);
1316
1317 if (link)
1318 len += snprintf(buf + len, sizeof(smi->buf) - len,
1319 "Link UP, Speed: ");
1320 else
1321 len += snprintf(buf + len, sizeof(smi->buf) - len,
1322 "Link DOWN, Speed: ");
1323
1324 if (speed == 0)
1325 len += snprintf(buf + len, sizeof(smi->buf) - len, "10Base-TX ");
1326 else if (speed == 1)
1327 len += snprintf(buf + len, sizeof(smi->buf) - len, "100Base-TX ");
1328 else if (speed == 2)
1329 len += snprintf(buf + len, sizeof(smi->buf) - len, "1000Base-TX ");
1330
1331 if (duplex)
1332 len += snprintf(buf + len, sizeof(smi->buf) - len, "Full-Duplex, ");
1333 else
1334 len += snprintf(buf + len, sizeof(smi->buf) - len, "Half-Duplex, ");
1335
1336 if (txpause)
1337 len += snprintf(buf + len, sizeof(smi->buf) - len, "TX-Pause ");
1338 if (rxpause)
1339 len += snprintf(buf + len, sizeof(smi->buf) - len, "RX-Pause ");
1340 if (nway)
1341 len += snprintf(buf + len, sizeof(smi->buf) - len, "nway ");
1342
1343 val->value.s = buf;
1344 val->len = len;
1345
1346 return 0;
1347 }
1348
1349 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1350 const struct switch_attr *attr,
1351 struct switch_val *val)
1352 {
1353 int i;
1354 u32 len = 0;
1355 struct rtl8366s_vlanconfig vlanmc;
1356 struct rtl8366s_vlan4kentry vlan4k;
1357 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1358 char *buf = smi->buf;
1359
1360 if (val->port_vlan >= RTL8366_NUM_VLANS)
1361 return -EINVAL;
1362
1363 memset(buf, '\0', sizeof(smi->buf));
1364
1365 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1366 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1367
1368 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN %d: Ports: ",
1369 val->port_vlan);
1370
1371 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1372 int index = 0;
1373 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1374 index == val->port_vlan)
1375 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d", i);
1376 }
1377 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1378
1379 len += snprintf(buf + len, sizeof(smi->buf) - len,
1380 "\t\t vid \t prio \t member \t untag \t fid\n");
1381 len += snprintf(buf + len, sizeof(smi->buf) - len, "\tMC:\t");
1382 len += snprintf(buf + len, sizeof(smi->buf) - len,
1383 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1384 vlanmc.vid, vlanmc.priority, vlanmc.member,
1385 vlanmc.untag, vlanmc.fid);
1386 len += snprintf(buf + len, sizeof(smi->buf) - len, "\t4K:\t");
1387 len += snprintf(buf + len, sizeof(smi->buf) - len,
1388 "%d \t \t 0x%04x \t 0x%04x \t %d",
1389 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1390
1391 val->value.s = buf;
1392 val->len = len;
1393
1394 return 0;
1395 }
1396
1397 static int rtl8366_set_port_led(struct switch_dev *dev,
1398 const struct switch_attr *attr,
1399 struct switch_val *val)
1400 {
1401 u32 data = 0;
1402 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1403 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1404 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1405 return -EINVAL;
1406
1407 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1408 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1409 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1410 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1411 } else {
1412 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1413 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1414 (val->value.i << (val->port_vlan * 4));
1415 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1416 }
1417
1418 return 0;
1419 }
1420
1421 static int rtl8366_get_port_led(struct switch_dev *dev,
1422 const struct switch_attr *attr,
1423 struct switch_val *val)
1424 {
1425 u32 data = 0;
1426 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1427 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1428 return -EINVAL;
1429
1430 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1431 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1432
1433 return 0;
1434 }
1435
1436 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1437 const struct switch_attr *attr,
1438 struct switch_val *val)
1439 {
1440 u32 data = 0;
1441 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1442 if (val->port_vlan >= RTL8366_NUM_PORTS)
1443 return -EINVAL;
1444
1445 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1446 data |= (1 << (val->port_vlan + 3));
1447 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1448
1449 return 0;
1450 }
1451
1452 static int rtl8366_get_port_mib(struct switch_dev *dev,
1453 const struct switch_attr *attr,
1454 struct switch_val *val)
1455 {
1456 int i, len = 0;
1457 unsigned long long counter = 0;
1458 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1459 char *buf = smi->buf;
1460
1461 if (val->port_vlan >= RTL8366_NUM_PORTS)
1462 return -EINVAL;
1463
1464 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d MIB counters\n",
1465 val->port_vlan);
1466 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1467
1468 len += snprintf(buf + len, sizeof(smi->buf) - len,
1469 "%d:%s\t", i, MIBCOUNTERS[i]);
1470 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1471 len += snprintf(buf + len, sizeof(smi->buf) - len,
1472 "[%llu]\n", counter);
1473 else
1474 len += snprintf(buf + len, sizeof(smi->buf) - len,
1475 "[error]\n");
1476 }
1477
1478 val->value.s = buf;
1479 val->len = len;
1480 return 0;
1481 }
1482
1483 static int rtl8366_get_ports(struct switch_dev *dev,
1484 struct switch_val *val)
1485 {
1486 struct rtl8366s_vlanconfig vlanmc;
1487 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1488 struct switch_port *port;
1489 int i;
1490
1491 if (val->port_vlan >= RTL8366_NUM_VLANS)
1492 return -EINVAL;
1493
1494 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1495
1496 port = &val->value.ports[0];
1497 val->len = 0;
1498 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1499 if (!(vlanmc.member & BIT(i)))
1500 continue;
1501
1502 port->id = i;
1503 port->flags = (vlanmc.untag & BIT(i)) ?
1504 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1505 val->len++;
1506 port++;
1507 }
1508 return 0;
1509 }
1510
1511 static int rtl8366_set_ports(struct switch_dev *dev,
1512 struct switch_val *val)
1513 {
1514 struct rtl8366s_vlanconfig vlanmc;
1515 struct rtl8366s_vlan4kentry vlan4k;
1516 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1517 struct switch_port *port;
1518 int i;
1519
1520 if (val->port_vlan >= RTL8366_NUM_VLANS)
1521 return -EINVAL;
1522
1523 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1524 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1525
1526 vlanmc.untag = 0;
1527 vlanmc.member = 0;
1528
1529 port = &val->value.ports[0];
1530 for (i = 0; i < val->len; i++, port++) {
1531 vlanmc.member |= BIT(port->id);
1532
1533 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1534 vlanmc.untag |= BIT(port->id);
1535 }
1536
1537 vlan4k.member = vlanmc.member;
1538 vlan4k.untag = vlanmc.untag;
1539
1540 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1541 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1542 return 0;
1543 }
1544
1545 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1546 {
1547 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1548 return rtl8366_get_vlan_port_pvid(smi, port, val);
1549 }
1550
1551 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1552 {
1553 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1554 return rtl8366_set_vlan_port_pvid(smi, port, val);
1555 }
1556
1557 static int rtl8366_reset_switch(struct switch_dev *dev)
1558 {
1559 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1560 int timeout = 10;
1561 u32 data;
1562
1563 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1564 RTL8366_CHIP_CTRL_RESET_HW);
1565 do {
1566 msleep(1);
1567 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1568 return -EIO;
1569
1570 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1571 break;
1572 } while (--timeout);
1573
1574 if (!timeout) {
1575 printk("Timeout waiting for the switch to reset\n");
1576 return -EIO;
1577 }
1578
1579 return rtl8366s_reset_vlan(smi);
1580 }
1581
1582 static struct switch_attr rtl8366_globals[] = {
1583 {
1584 .type = SWITCH_TYPE_INT,
1585 .name = "enable_vlan",
1586 .description = "Enable VLAN mode",
1587 .set = rtl8366_set_vlan,
1588 .get = rtl8366_get_vlan,
1589 .max = 1,
1590 .ofs = 1
1591 },
1592 {
1593 .type = SWITCH_TYPE_INT,
1594 .name = "enable_vlan4k",
1595 .description = "Enable VLAN 4K mode",
1596 .set = rtl8366_set_vlan,
1597 .get = rtl8366_get_vlan,
1598 .max = 1,
1599 .ofs = 2
1600 },
1601 {
1602 .type = SWITCH_TYPE_INT,
1603 .name = "reset_mibs",
1604 .description = "Reset all MIB counters",
1605 .set = rtl8366_global_reset_mibs,
1606 .get = NULL,
1607 .max = 1
1608 },
1609 {
1610 .type = SWITCH_TYPE_INT,
1611 .name = "blinkrate",
1612 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1613 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1614 .set = rtl8366_global_set_blinkrate,
1615 .get = rtl8366_global_get_blinkrate,
1616 .max = 5
1617 },
1618 };
1619
1620 static struct switch_attr rtl8366_port[] = {
1621 {
1622 .type = SWITCH_TYPE_STRING,
1623 .name = "link",
1624 .description = "Get port link information",
1625 .max = 1,
1626 .set = NULL,
1627 .get = rtl8366_attr_get_port_link
1628 },
1629 {
1630 .type = SWITCH_TYPE_INT,
1631 .name = "reset_mib",
1632 .description = "Reset single port MIB counters",
1633 .max = 1,
1634 .set = rtl8366_reset_port_mibs,
1635 .get = NULL
1636 },
1637 {
1638 .type = SWITCH_TYPE_STRING,
1639 .name = "mib",
1640 .description = "Get MIB counters for port",
1641 .max = 33,
1642 .set = NULL,
1643 .get = rtl8366_get_port_mib
1644 },
1645 {
1646 .type = SWITCH_TYPE_INT,
1647 .name = "led",
1648 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1649 .max = 15,
1650 .set = rtl8366_set_port_led,
1651 .get = rtl8366_get_port_led
1652 },
1653 };
1654
1655 static struct switch_attr rtl8366_vlan[] = {
1656 {
1657 .type = SWITCH_TYPE_STRING,
1658 .name = "info",
1659 .description = "Get vlan information",
1660 .max = 1,
1661 .set = NULL,
1662 .get = rtl8366_attr_get_vlan_info
1663 },
1664 };
1665
1666
1667 /* template */
1668 static struct switch_dev rtldev = {
1669 .name = "RTL8366S",
1670 .cpu_port = RTL8366_PORT_NUM_CPU,
1671 .ports = RTL8366_NUM_PORTS,
1672 .vlans = RTL8366_NUM_VLANS,
1673 .attr_global = {
1674 .attr = rtl8366_globals,
1675 .n_attr = ARRAY_SIZE(rtl8366_globals),
1676 },
1677 .attr_port = {
1678 .attr = rtl8366_port,
1679 .n_attr = ARRAY_SIZE(rtl8366_port),
1680 },
1681 .attr_vlan = {
1682 .attr = rtl8366_vlan,
1683 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1684 },
1685
1686 .get_vlan_ports = rtl8366_get_ports,
1687 .set_vlan_ports = rtl8366_set_ports,
1688 .get_port_pvid = rtl8366_get_port_pvid,
1689 .set_port_pvid = rtl8366_set_port_pvid,
1690 .reset_switch = rtl8366_reset_switch,
1691 };
1692
1693 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1694 {
1695 struct switch_dev *dev = &smi->dev;
1696 int err;
1697
1698 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1699 dev->priv = smi;
1700 dev->devname = dev_name(&smi->pdev->dev);
1701
1702 err = register_switch(dev, NULL);
1703 if (err)
1704 dev_err(&smi->pdev->dev, "switch registration failed\n");
1705
1706 return err;
1707 }
1708
1709 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1710 {
1711 unregister_switch(&smi->dev);
1712 }
1713
1714 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1715 {
1716 struct rtl8366_smi *smi = bus->priv;
1717 u32 val = 0;
1718 int err;
1719
1720 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1721 if (err)
1722 return 0xffff;
1723
1724 return val;
1725 }
1726
1727 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1728 u16 val)
1729 {
1730 struct rtl8366_smi *smi = bus->priv;
1731 u32 t;
1732 int err;
1733
1734 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1735 /* flush write */
1736 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1737
1738 return err;
1739 }
1740
1741 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1742 {
1743 int ret;
1744 int i;
1745
1746 smi->mii_bus = mdiobus_alloc();
1747 if (smi->mii_bus == NULL) {
1748 ret = -ENOMEM;
1749 goto err;
1750 }
1751
1752 spin_lock_init(&smi->lock);
1753 smi->mii_bus->priv = (void *) smi;
1754 smi->mii_bus->name = "rtl8366-smi";
1755 smi->mii_bus->read = rtl8366_smi_mii_read;
1756 smi->mii_bus->write = rtl8366_smi_mii_write;
1757 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1758 dev_name(&smi->pdev->dev));
1759 smi->mii_bus->parent = &smi->pdev->dev;
1760 smi->mii_bus->phy_mask = ~(0x1f);
1761 smi->mii_bus->irq = smi->mii_irq;
1762 for (i = 0; i < PHY_MAX_ADDR; i++)
1763 smi->mii_irq[i] = PHY_POLL;
1764
1765 ret = mdiobus_register(smi->mii_bus);
1766 if (ret)
1767 goto err_free;
1768
1769 return 0;
1770
1771 err_free:
1772 mdiobus_free(smi->mii_bus);
1773 err:
1774 return ret;
1775 }
1776
1777 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1778 {
1779 mdiobus_unregister(smi->mii_bus);
1780 mdiobus_free(smi->mii_bus);
1781 }
1782
1783 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1784 {
1785 return (bus->read == rtl8366_smi_mii_read &&
1786 bus->write == rtl8366_smi_mii_write);
1787 }
1788
1789 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1790 {
1791 u32 chip_id = 0;
1792 u32 chip_ver = 0;
1793 int ret;
1794
1795 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1796 if (ret) {
1797 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1798 return ret;
1799 }
1800
1801 switch (chip_id) {
1802 case RTL8366S_CHIP_ID_8366:
1803 break;
1804 default:
1805 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1806 return -ENODEV;
1807 }
1808
1809 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1810 &chip_ver);
1811 if (ret) {
1812 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1813 return ret;
1814 }
1815
1816 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1817 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1818
1819 rtl8366_debugfs_init(smi);
1820
1821 return 0;
1822 }
1823
1824 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1825 {
1826 static int rtl8366_smi_version_printed;
1827 struct rtl8366_smi_platform_data *pdata;
1828 struct rtl8366_smi *smi;
1829 int err;
1830
1831 if (!rtl8366_smi_version_printed++)
1832 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1833 " version " RTL8366_SMI_DRIVER_VER"\n");
1834
1835 pdata = pdev->dev.platform_data;
1836 if (!pdata) {
1837 dev_err(&pdev->dev, "no platform data specified\n");
1838 err = -EINVAL;
1839 goto err_out;
1840 }
1841
1842 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1843 if (!smi) {
1844 dev_err(&pdev->dev, "no memory for private data\n");
1845 err = -ENOMEM;
1846 goto err_out;
1847 }
1848
1849 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1850 if (err) {
1851 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1852 pdata->gpio_sda, err);
1853 goto err_free_smi;
1854 }
1855
1856 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1857 if (err) {
1858 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1859 pdata->gpio_sck, err);
1860 goto err_free_sda;
1861 }
1862
1863 smi->pdev = pdev;
1864 smi->pdata = pdata;
1865 spin_lock_init(&smi->lock);
1866
1867 platform_set_drvdata(pdev, smi);
1868
1869 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1870 pdata->gpio_sda, pdata->gpio_sck);
1871
1872 err = rtl8366_smi_setup(smi);
1873 if (err)
1874 goto err_clear_drvdata;
1875
1876 err = rtl8366_smi_mii_init(smi);
1877 if (err)
1878 goto err_clear_drvdata;
1879
1880 err = rtl8366_smi_switch_init(smi);
1881 if (err)
1882 goto err_mii_cleanup;
1883
1884 return 0;
1885
1886 err_mii_cleanup:
1887 rtl8366_smi_mii_cleanup(smi);
1888 err_clear_drvdata:
1889 platform_set_drvdata(pdev, NULL);
1890 gpio_free(pdata->gpio_sck);
1891 err_free_sda:
1892 gpio_free(pdata->gpio_sda);
1893 err_free_smi:
1894 kfree(smi);
1895 err_out:
1896 return err;
1897 }
1898
1899 int rtl8366_phy_config_init(struct phy_device *phydev)
1900 {
1901 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1902 return -EINVAL;
1903
1904 return 0;
1905 }
1906
1907 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1908 {
1909 return 0;
1910 }
1911
1912 static struct phy_driver rtl8366_smi_phy_driver = {
1913 .phy_id = 0x001cc960,
1914 .name = "Realtek RTL8366",
1915 .phy_id_mask = 0x1ffffff0,
1916 .features = PHY_GBIT_FEATURES,
1917 .config_aneg = rtl8366_phy_config_aneg,
1918 .config_init = rtl8366_phy_config_init,
1919 .read_status = genphy_read_status,
1920 .driver = {
1921 .owner = THIS_MODULE,
1922 },
1923 };
1924
1925 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1926 {
1927 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1928
1929 if (smi) {
1930 struct rtl8366_smi_platform_data *pdata;
1931
1932 pdata = pdev->dev.platform_data;
1933
1934 rtl8366_smi_switch_cleanup(smi);
1935 rtl8366_debugfs_remove(smi);
1936 rtl8366_smi_mii_cleanup(smi);
1937 platform_set_drvdata(pdev, NULL);
1938 gpio_free(pdata->gpio_sck);
1939 gpio_free(pdata->gpio_sda);
1940 kfree(smi);
1941 }
1942
1943 return 0;
1944 }
1945
1946 static struct platform_driver rtl8366_smi_driver = {
1947 .driver = {
1948 .name = RTL8366_SMI_DRIVER_NAME,
1949 .owner = THIS_MODULE,
1950 },
1951 .probe = rtl8366_smi_probe,
1952 .remove = __devexit_p(rtl8366_smi_remove),
1953 };
1954
1955 static int __init rtl8366_smi_init(void)
1956 {
1957 int ret;
1958 ret = platform_driver_register(&rtl8366_smi_driver);
1959 if (ret)
1960 return ret;
1961
1962 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1963 if (ret)
1964 goto err_platform_unregister;
1965
1966 return 0;
1967
1968 err_platform_unregister:
1969 platform_driver_unregister(&rtl8366_smi_driver);
1970 return ret;
1971 }
1972 module_init(rtl8366_smi_init);
1973
1974 static void __exit rtl8366_smi_exit(void)
1975 {
1976 phy_driver_unregister(&rtl8366_smi_phy_driver);
1977 platform_driver_unregister(&rtl8366_smi_driver);
1978 }
1979 module_exit(rtl8366_smi_exit);
1980
1981 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1982 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1983 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1984 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1985 MODULE_LICENSE("GPL v2");
1986 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
OpenWrt Source Repository