target/linux/ar71xx/patches-3.8/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch

   1 From 5e079d9b7ac5dda3be9f215f8440333597f57b26 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sun, 3 Feb 2013 14:52:47 +0000
   4 Subject: [PATCH] MIPS: pci-ar724x: setup command register of the PCI
   5  controller
   6
   7 commit 12401fc28d40aa5bf8bda6991a96b6d7a3dae3ac upstream.
   8
   9 The command register of the PCI controller is
  10 not initialized correctly by the bootloader on
  11 some boards and this leads to non working PCI
  12 bus.
  13
  14 Add code to initialize the command register
  15 from the Linux code to avoid this.
  16
  17 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  18 Patchwork: http://patchwork.linux-mips.org/patch/4916/
  19 Signed-off-by: John Crispin <blogic@openwrt.org>
  20 ---
  21  arch/mips/ath79/pci.c                          |   10 +++-
  22  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 +
  23  arch/mips/pci/pci-ar724x.c                     |   63 ++++++++++++++++++++++++
  24  3 files changed, 74 insertions(+), 1 deletion(-)
  25
  26 --- a/arch/mips/ath79/pci.c
  27 +++ b/arch/mips/ath79/pci.c
  28 @@ -139,13 +139,14 @@ static struct platform_device *
  29  ath79_register_pci_ar724x(int id,
  30                           unsigned long cfg_base,
  31                           unsigned long ctrl_base,
  32 +                         unsigned long crp_base,
  33                           unsigned long mem_base,
  34                           unsigned long mem_size,
  35                           unsigned long io_base,
  36                           int irq)
  37  {
  38         struct platform_device *pdev;
  39 -       struct resource res[5];
  40 +       struct resource res[6];
  41
  42         memset(res, 0, sizeof(res));
  43
  44 @@ -173,6 +174,11 @@ ath79_register_pci_ar724x(int id,
  45         res[4].start = io_base;
  46         res[4].end = io_base;
  47
  48 +       res[5].name = "crp_base";
  49 +       res[5].flags = IORESOURCE_MEM;
  50 +       res[5].start = crp_base;
  51 +       res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
  52 +
  53         pdev = platform_device_register_simple("ar724x-pci", id,
  54                                                res, ARRAY_SIZE(res));
  55         return pdev;
  56 @@ -188,6 +194,7 @@ int __init ath79_register_pci(void)
  57                 pdev = ath79_register_pci_ar724x(-1,
  58                                                  AR724X_PCI_CFG_BASE,
  59                                                  AR724X_PCI_CTRL_BASE,
  60 +                                                AR724X_PCI_CRP_BASE,
  61                                                  AR724X_PCI_MEM_BASE,
  62                                                  AR724X_PCI_MEM_SIZE,
  63                                                  0,
  64 @@ -203,6 +210,7 @@ int __init ath79_register_pci(void)
  65                 pdev = ath79_register_pci_ar724x(-1,
  66                                                  AR724X_PCI_CFG_BASE,
  67                                                  AR724X_PCI_CTRL_BASE,
  68 +                                                AR724X_PCI_CRP_BASE,
  69                                                  AR724X_PCI_MEM_BASE,
  70                                                  AR724X_PCI_MEM_SIZE,
  71                                                  0,
  72 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  73 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  74 @@ -67,6 +67,8 @@
  75
  76  #define AR724X_PCI_CFG_BASE    0x14000000
  77  #define AR724X_PCI_CFG_SIZE    0x1000
  78 +#define AR724X_PCI_CRP_BASE    (AR71XX_APB_BASE + 0x000c0000)
  79 +#define AR724X_PCI_CRP_SIZE    0x1000
  80  #define AR724X_PCI_CTRL_BASE   (AR71XX_APB_BASE + 0x000f0000)
  81  #define AR724X_PCI_CTRL_SIZE   0x100
  82
  83 --- a/arch/mips/pci/pci-ar724x.c
  84 +++ b/arch/mips/pci/pci-ar724x.c
  85 @@ -29,9 +29,17 @@
  86
  87  #define AR7240_BAR0_WAR_VALUE  0xffff
  88
  89 +#define AR724X_PCI_CMD_INIT    (PCI_COMMAND_MEMORY |           \
  90 +                                PCI_COMMAND_MASTER |           \
  91 +                                PCI_COMMAND_INVALIDATE |       \
  92 +                                PCI_COMMAND_PARITY |           \
  93 +                                PCI_COMMAND_SERR |             \
  94 +                                PCI_COMMAND_FAST_BACK)
  95 +
  96  struct ar724x_pci_controller {
  97         void __iomem *devcfg_base;
  98         void __iomem *ctrl_base;
  99 +       void __iomem *crp_base;
 100
 101         int irq;
 102         int irq_base;
 103 @@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
 104         return container_of(hose, struct ar724x_pci_controller, pci_controller);
 105  }
 106
 107 +static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
 108 +                                 int where, int size, u32 value)
 109 +{
 110 +       unsigned long flags;
 111 +       void __iomem *base;
 112 +       u32 data;
 113 +       int s;
 114 +
 115 +       WARN_ON(where & (size - 1));
 116 +
 117 +       if (!apc->link_up)
 118 +               return PCIBIOS_DEVICE_NOT_FOUND;
 119 +
 120 +       base = apc->crp_base;
 121 +
 122 +       spin_lock_irqsave(&apc->lock, flags);
 123 +       data = __raw_readl(base + (where & ~3));
 124 +
 125 +       switch (size) {
 126 +       case 1:
 127 +               s = ((where & 3) * 8);
 128 +               data &= ~(0xff << s);
 129 +               data |= ((value & 0xff) << s);
 130 +               break;
 131 +       case 2:
 132 +               s = ((where & 2) * 8);
 133 +               data &= ~(0xffff << s);
 134 +               data |= ((value & 0xffff) << s);
 135 +               break;
 136 +       case 4:
 137 +               data = value;
 138 +               break;
 139 +       default:
 140 +               spin_unlock_irqrestore(&apc->lock, flags);
 141 +               return PCIBIOS_BAD_REGISTER_NUMBER;
 142 +       }
 143 +
 144 +       __raw_writel(data, base + (where & ~3));
 145 +       /* flush write */
 146 +       __raw_readl(base + (where & ~3));
 147 +       spin_unlock_irqrestore(&apc->lock, flags);
 148 +
 149 +       return PCIBIOS_SUCCESSFUL;
 150 +}
 151 +
 152  static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 153                             int size, uint32_t *value)
 154  {
 155 @@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
 156         if (!apc->devcfg_base)
 157                 return -EBUSY;
 158
 159 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
 160 +       if (!res)
 161 +               return -EINVAL;
 162 +
 163 +       apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
 164 +       if (apc->crp_base == NULL)
 165 +               return -EBUSY;
 166 +
 167         apc->irq = platform_get_irq(pdev, 0);
 168         if (apc->irq < 0)
 169                 return -EINVAL;
 170 @@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
 171
 172         ar724x_pci_irq_init(apc, id);
 173
 174 +       ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
 175 +
 176         register_pci_controller(&apc->pci_controller);
 177
 178         return 0;