target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch

   1 From 64d8592fd1f7265de8b31dbf294928eaf9983db5 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Fri, 15 Feb 2013 13:38:17 +0000
   4 Subject: [PATCH] MIPS: ath79: add clock setup code for the QCA955X SoCs
   5
   6 commit 41583c05c15cd3adb848f9ee8316bf8084c961cb upstream.
   7
   8 The patch adds code to get various clock frequencies
   9 from the PLLs used in the QCA955x SoCs.
  10
  11 Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
  12 Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
  13 Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
  14 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  15 Patchwork: http://patchwork.linux-mips.org/patch/4945/
  16 Signed-off-by: John Crispin <blogic@openwrt.org>
  17 ---
  18  arch/mips/ath79/clock.c                        |   78 ++++++++++++++++++++++++
  19  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   39 ++++++++++++
  20  2 files changed, 117 insertions(+)
  21
  22 --- a/arch/mips/ath79/clock.c
  23 +++ b/arch/mips/ath79/clock.c
  24 @@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
  25         iounmap(dpll_base);
  26  }
  27
  28 +static void __init qca955x_clocks_init(void)
  29 +{
  30 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  31 +       u32 cpu_pll, ddr_pll;
  32 +       u32 bootstrap;
  33 +
  34 +       bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
  35 +       if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
  36 +               ath79_ref_clk.rate = 40 * 1000 * 1000;
  37 +       else
  38 +               ath79_ref_clk.rate = 25 * 1000 * 1000;
  39 +
  40 +       pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
  41 +       out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  42 +                 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
  43 +       ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  44 +                 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
  45 +       nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
  46 +              QCA955X_PLL_CPU_CONFIG_NINT_MASK;
  47 +       frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  48 +              QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
  49 +
  50 +       cpu_pll = nint * ath79_ref_clk.rate / ref_div;
  51 +       cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
  52 +       cpu_pll /= (1 << out_div);
  53 +
  54 +       pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
  55 +       out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  56 +                 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
  57 +       ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  58 +                 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
  59 +       nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
  60 +              QCA955X_PLL_DDR_CONFIG_NINT_MASK;
  61 +       frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  62 +              QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
  63 +
  64 +       ddr_pll = nint * ath79_ref_clk.rate / ref_div;
  65 +       ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
  66 +       ddr_pll /= (1 << out_div);
  67 +
  68 +       clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
  69 +
  70 +       postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  71 +                 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  72 +
  73 +       if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  74 +               ath79_cpu_clk.rate = ath79_ref_clk.rate;
  75 +       else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  76 +               ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
  77 +       else
  78 +               ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
  79 +
  80 +       postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  81 +                 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  82 +
  83 +       if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  84 +               ath79_ddr_clk.rate = ath79_ref_clk.rate;
  85 +       else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  86 +               ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
  87 +       else
  88 +               ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
  89 +
  90 +       postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  91 +                 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  92 +
  93 +       if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  94 +               ath79_ahb_clk.rate = ath79_ref_clk.rate;
  95 +       else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  96 +               ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
  97 +       else
  98 +               ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
  99 +
 100 +       ath79_wdt_clk.rate = ath79_ref_clk.rate;
 101 +       ath79_uart_clk.rate = ath79_ref_clk.rate;
 102 +}
 103 +
 104  void __init ath79_clocks_init(void)
 105  {
 106         if (soc_is_ar71xx())
 107 @@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
 108                 ar933x_clocks_init();
 109         else if (soc_is_ar934x())
 110                 ar934x_clocks_init();
 111 +       else if (soc_is_qca955x())
 112 +               qca955x_clocks_init();
 113         else
 114                 BUG();
 115
 116 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 117 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 118 @@ -225,6 +225,41 @@
 119  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
 120  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
 121
 122 +#define QCA955X_PLL_CPU_CONFIG_REG             0x00
 123 +#define QCA955X_PLL_DDR_CONFIG_REG             0x04
 124 +#define QCA955X_PLL_CLK_CTRL_REG               0x08
 125 +
 126 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 127 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 128 +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT      6
 129 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 130 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 131 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 132 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 133 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK     0x3
 134 +
 135 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 136 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 137 +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT      10
 138 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 139 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 140 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 141 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 142 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 143 +
 144 +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 145 +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 146 +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 147 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 148 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 149 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 150 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 151 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 152 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 153 +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 154 +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 155 +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 156 +
 157  /*
 158   * USB_CONFIG block
 159   */
 160 @@ -264,6 +299,8 @@
 161  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 162  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 163
 164 +#define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 165 +
 166  #define MISC_INT_ETHSW                 BIT(12)
 167  #define MISC_INT_TIMER4                        BIT(10)
 168  #define MISC_INT_TIMER3                        BIT(9)
 169 @@ -341,6 +378,8 @@
 170  #define AR934X_BOOTSTRAP_SDRAM_DISABLED        BIT(1)
 171  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 172
 173 +#define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 174 +
 175  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 176  #define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
 177  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)