target/linux/ar71xx/patches-4.14/606-MIPS-ath79-pb44-fixes.patch

   1 --- a/arch/mips/ath79/mach-pb44.c
   2 +++ b/arch/mips/ath79/mach-pb44.c
   3 @@ -8,23 +8,47 @@
   4   *  by the Free Software Foundation.
   5   */
   6
   7 +#include <linux/delay.h>
   8  #include <linux/init.h>
   9  #include <linux/platform_device.h>
  10  #include <linux/i2c.h>
  11  #include <linux/i2c-gpio.h>
  12  #include <linux/platform_data/pcf857x.h>
  13 +#include <linux/spi/flash.h>
  14 +#include <linux/spi/vsc7385.h>
  15
  16  #include "machtypes.h"
  17 +#include <asm/mach-ath79/ar71xx_regs.h>
  18 +#include <asm/mach-ath79/ath79.h>
  19 +#include "dev-eth.h"
  20  #include "dev-gpio-buttons.h"
  21  #include "dev-leds-gpio.h"
  22  #include "dev-spi.h"
  23  #include "dev-usb.h"
  24 +#include "machtypes.h"
  25  #include "pci.h"
  26
  27  #define PB44_GPIO_I2C_SCL      0
  28  #define PB44_GPIO_I2C_SDA      1
  29
  30 +#define PB44_PCF8757_VSC7395_CS        0
  31 +#define PB44_PCF8757_STEREO_CS 1
  32 +#define PB44_PCF8757_SLIC_CS0  2
  33 +#define PB44_PCF8757_SLIC_TEST 3
  34 +#define PB44_PCF8757_SLIC_INT0 4
  35 +#define PB44_PCF8757_SLIC_INT1 5
  36 +#define PB44_PCF8757_SW_RESET  6
  37 +#define PB44_PCF8757_SW_JUMP   8
  38 +#define PB44_PCF8757_LED_JUMP1 9
  39 +#define PB44_PCF8757_LED_JUMP2 10
  40 +#define PB44_PCF8757_TP24      11
  41 +#define PB44_PCF8757_TP25      12
  42 +#define PB44_PCF8757_TP26      13
  43 +#define PB44_PCF8757_TP27      14
  44 +#define PB44_PCF8757_TP28      15
  45 +
  46  #define PB44_GPIO_EXP_BASE     16
  47 +#define PB44_GPIO_VSC7395_CS   (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
  48  #define PB44_GPIO_SW_RESET     (PB44_GPIO_EXP_BASE + 6)
  49  #define PB44_GPIO_SW_JUMP      (PB44_GPIO_EXP_BASE + 8)
  50  #define PB44_GPIO_LED_JUMP1    (PB44_GPIO_EXP_BASE + 9)
  51 @@ -87,20 +111,59 @@ static struct gpio_keys_button pb44_gpio
  52         }
  53  };
  54
  55 +static void pb44_vsc7395_reset(void)
  56 +{
  57 +       ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  58 +       udelay(10);
  59 +       ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  60 +       mdelay(50);
  61 +}
  62 +
  63 +static struct vsc7385_platform_data pb44_vsc7395_data = {
  64 +       .reset          = pb44_vsc7395_reset,
  65 +       .ucode_name     = "vsc7395_ucode_pb44.bin",
  66 +       .mac_cfg = {
  67 +               .tx_ipg         = 6,
  68 +               .bit2           = 1,
  69 +               .clk_sel        = 0,
  70 +       },
  71 +};
  72 +
  73 +static const char *pb44_part_probes[] = {
  74 +       "RedBoot",
  75 +       NULL,
  76 +};
  77 +
  78 +static struct flash_platform_data pb44_flash_data = {
  79 +       .part_probes    = pb44_part_probes,
  80 +};
  81 +
  82  static struct spi_board_info pb44_spi_info[] = {
  83         {
  84                 .bus_num        = 0,
  85                 .chip_select    = 0,
  86                 .max_speed_hz   = 25000000,
  87                 .modalias       = "m25p64",
  88 +               .platform_data  = &pb44_flash_data,
  89         },
  90 +       {
  91 +               .bus_num        = 0,
  92 +               .chip_select    = 1,
  93 +               .max_speed_hz   = 25000000,
  94 +               .modalias       = "spi-vsc7385",
  95 +               .platform_data  = &pb44_vsc7395_data,
  96 +       }
  97  };
  98
  99  static struct ath79_spi_platform_data pb44_spi_data = {
 100         .bus_num                = 0,
 101 -       .num_chipselect         = 1,
 102 +       .num_chipselect         = 2,
 103  };
 104
 105 +#define PB44_WAN_PHYMASK       BIT(0)
 106 +#define PB44_LAN_PHYMASK       0
 107 +#define PB44_MDIO_PHYMASK      (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
 108 +
 109  static void __init pb44_init(void)
 110  {
 111         i2c_register_board_info(0, pb44_i2c_board_info,
 112 @@ -116,6 +179,22 @@ static void __init pb44_init(void)
 113                            ARRAY_SIZE(pb44_spi_info));
 114         ath79_register_usb();
 115         ath79_register_pci();
 116 +
 117 +       ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
 118 +
 119 +       ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 120 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 121 +       ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
 122 +
 123 +       ath79_register_eth(0);
 124 +
 125 +       ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 126 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 127 +       ath79_eth1_data.speed = SPEED_1000;
 128 +       ath79_eth1_data.duplex = DUPLEX_FULL;
 129 +       ath79_eth1_pll_data.pll_1000 = 0x110000;
 130 +
 131 +       ath79_register_eth(1);
 132  }
 133
 134  MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
 135 --- a/arch/mips/ath79/Kconfig
 136 +++ b/arch/mips/ath79/Kconfig
 137 @@ -58,6 +58,7 @@ config ATH79_MACH_DB120
 138  config ATH79_MACH_PB44
 139         bool "Atheros PB44 reference board"
 140         select SOC_AR71XX
 141 +       select ATH79_DEV_ETH
 142         select ATH79_DEV_GPIO_BUTTONS
 143         select ATH79_DEV_LEDS_GPIO
 144         select ATH79_DEV_SPI