target/linux/ar71xx/patches-4.4/606-MIPS-ath79-pb44-fixes.patch

   1 --- a/arch/mips/ath79/mach-pb44.c
   2 +++ b/arch/mips/ath79/mach-pb44.c
   3 @@ -8,23 +8,48 @@
   4   *  by the Free Software Foundation.
   5   */
   6
   7 +#include <linux/delay.h>
   8  #include <linux/init.h>
   9  #include <linux/platform_device.h>
  10  #include <linux/i2c.h>
  11  #include <linux/i2c-gpio.h>
  12  #include <linux/i2c/pcf857x.h>
  13 +#include <linux/i2c/pcf857x.h>
  14 +#include <linux/spi/flash.h>
  15 +#include <linux/spi/vsc7385.h>
  16
  17 -#include "machtypes.h"
  18 +#include <asm/mach-ath79/ar71xx_regs.h>
  19 +#include <asm/mach-ath79/ath79.h>
  20 +
  21 +#include "dev-eth.h"
  22  #include "dev-gpio-buttons.h"
  23  #include "dev-leds-gpio.h"
  24  #include "dev-spi.h"
  25  #include "dev-usb.h"
  26 +#include "machtypes.h"
  27  #include "pci.h"
  28
  29  #define PB44_GPIO_I2C_SCL      0
  30  #define PB44_GPIO_I2C_SDA      1
  31
  32 +#define PB44_PCF8757_VSC7395_CS        0
  33 +#define PB44_PCF8757_STEREO_CS 1
  34 +#define PB44_PCF8757_SLIC_CS0  2
  35 +#define PB44_PCF8757_SLIC_TEST 3
  36 +#define PB44_PCF8757_SLIC_INT0 4
  37 +#define PB44_PCF8757_SLIC_INT1 5
  38 +#define PB44_PCF8757_SW_RESET  6
  39 +#define PB44_PCF8757_SW_JUMP   8
  40 +#define PB44_PCF8757_LED_JUMP1 9
  41 +#define PB44_PCF8757_LED_JUMP2 10
  42 +#define PB44_PCF8757_TP24      11
  43 +#define PB44_PCF8757_TP25      12
  44 +#define PB44_PCF8757_TP26      13
  45 +#define PB44_PCF8757_TP27      14
  46 +#define PB44_PCF8757_TP28      15
  47 +
  48  #define PB44_GPIO_EXP_BASE     16
  49 +#define PB44_GPIO_VSC7395_CS   (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
  50  #define PB44_GPIO_SW_RESET     (PB44_GPIO_EXP_BASE + 6)
  51  #define PB44_GPIO_SW_JUMP      (PB44_GPIO_EXP_BASE + 8)
  52  #define PB44_GPIO_LED_JUMP1    (PB44_GPIO_EXP_BASE + 9)
  53 @@ -87,20 +112,59 @@ static struct gpio_keys_button pb44_gpio
  54         }
  55  };
  56
  57 +static void pb44_vsc7395_reset(void)
  58 +{
  59 +       ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  60 +       udelay(10);
  61 +       ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  62 +       mdelay(50);
  63 +}
  64 +
  65 +static struct vsc7385_platform_data pb44_vsc7395_data = {
  66 +       .reset          = pb44_vsc7395_reset,
  67 +       .ucode_name     = "vsc7395_ucode_pb44.bin",
  68 +       .mac_cfg = {
  69 +               .tx_ipg         = 6,
  70 +               .bit2           = 1,
  71 +               .clk_sel        = 0,
  72 +       },
  73 +};
  74 +
  75 +static const char *pb44_part_probes[] = {
  76 +       "RedBoot",
  77 +       NULL,
  78 +};
  79 +
  80 +static struct flash_platform_data pb44_flash_data = {
  81 +       .part_probes    = pb44_part_probes,
  82 +};
  83 +
  84  static struct spi_board_info pb44_spi_info[] = {
  85         {
  86                 .bus_num        = 0,
  87                 .chip_select    = 0,
  88                 .max_speed_hz   = 25000000,
  89                 .modalias       = "m25p64",
  90 +               .platform_data  = &pb44_flash_data,
  91         },
  92 +       {
  93 +               .bus_num        = 0,
  94 +               .chip_select    = 1,
  95 +               .max_speed_hz   = 25000000,
  96 +               .modalias       = "spi-vsc7385",
  97 +               .platform_data  = &pb44_vsc7395_data,
  98 +       }
  99  };
 100
 101  static struct ath79_spi_platform_data pb44_spi_data = {
 102         .bus_num                = 0,
 103 -       .num_chipselect         = 1,
 104 +       .num_chipselect         = 2,
 105  };
 106
 107 +#define PB44_WAN_PHYMASK       BIT(0)
 108 +#define PB44_LAN_PHYMASK       0
 109 +#define PB44_MDIO_PHYMASK      (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
 110 +
 111  static void __init pb44_init(void)
 112  {
 113         i2c_register_board_info(0, pb44_i2c_board_info,
 114 @@ -116,6 +180,22 @@ static void __init pb44_init(void)
 115                            ARRAY_SIZE(pb44_spi_info));
 116         ath79_register_usb();
 117         ath79_register_pci();
 118 +
 119 +       ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
 120 +
 121 +       ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 122 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 123 +       ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
 124 +
 125 +       ath79_register_eth(0);
 126 +
 127 +       ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 128 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 129 +       ath79_eth1_data.speed = SPEED_1000;
 130 +       ath79_eth1_data.duplex = DUPLEX_FULL;
 131 +       ath79_eth1_pll_data.pll_1000 = 0x110000;
 132 +
 133 +       ath79_register_eth(1);
 134  }
 135
 136  MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
 137 --- a/arch/mips/ath79/Kconfig
 138 +++ b/arch/mips/ath79/Kconfig
 139 @@ -58,6 +58,7 @@ config ATH79_MACH_DB120
 140  config ATH79_MACH_PB44
 141         bool "Atheros PB44 reference board"
 142         select SOC_AR71XX
 143 +       select ATH79_DEV_ETH
 144         select ATH79_DEV_GPIO_BUTTONS
 145         select ATH79_DEV_LEDS_GPIO
 146         select ATH79_DEV_SPI