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[openwrt/openwrt.git] / target / linux / ath25 / patches-4.9 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -5,7 +5,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on PCI
15 + depends on (PCI || ATH25)
16 ---help---
17 If you have a network (Ethernet) card belonging to this class, say Y.
18
19 @@ -78,4 +78,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATH25
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1198 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/netdevice.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/interrupt.h>
64 +#include <linux/skbuff.h>
65 +#include <linux/init.h>
66 +#include <linux/delay.h>
67 +#include <linux/mm.h>
68 +#include <linux/mii.h>
69 +#include <linux/phy.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/io.h>
72 +
73 +#define AR2313_MTU 1692
74 +#define AR2313_PRIOS 1
75 +#define AR2313_QUEUES (2*AR2313_PRIOS)
76 +#define AR2313_DESCR_ENTRIES 64
77 +
78 +#ifndef min
79 +#define min(a, b) (((a) < (b)) ? (a) : (b))
80 +#endif
81 +
82 +#ifndef SMP_CACHE_BYTES
83 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
84 +#endif
85 +
86 +#define AR2313_MBOX_SET_BIT 0x8
87 +
88 +#include "ar231x.h"
89 +
90 +/**
91 + * New interrupt handler strategy:
92 + *
93 + * An old interrupt handler worked using the traditional method of
94 + * replacing an skbuff with a new one when a packet arrives. However
95 + * the rx rings do not need to contain a static number of buffer
96 + * descriptors, thus it makes sense to move the memory allocation out
97 + * of the main interrupt handler and do it in a bottom half handler
98 + * and only allocate new buffers when the number of buffers in the
99 + * ring is below a certain threshold. In order to avoid starving the
100 + * NIC under heavy load it is however necessary to force allocation
101 + * when hitting a minimum threshold. The strategy for alloction is as
102 + * follows:
103 + *
104 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
105 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
106 + * the buffers in the interrupt handler
107 + * RX_RING_THRES - maximum number of buffers in the rx ring
108 + *
109 + * One advantagous side effect of this allocation approach is that the
110 + * entire rx processing can be done without holding any spin lock
111 + * since the rx rings and registers are totally independent of the tx
112 + * ring and its registers. This of course includes the kmalloc's of
113 + * new skb's. Thus start_xmit can run in parallel with rx processing
114 + * and the memory allocation on SMP systems.
115 + *
116 + * Note that running the skb reallocation in a bottom half opens up
117 + * another can of races which needs to be handled properly. In
118 + * particular it can happen that the interrupt handler tries to run
119 + * the reallocation while the bottom half is either running on another
120 + * CPU or was interrupted on the same CPU. To get around this the
121 + * driver uses bitops to prevent the reallocation routines from being
122 + * reentered.
123 + *
124 + * TX handling can also be done without holding any spin lock, wheee
125 + * this is fun! since tx_csm is only written to by the interrupt
126 + * handler.
127 + */
128 +
129 +/**
130 + * Threshold values for RX buffer allocation - the low water marks for
131 + * when to start refilling the rings are set to 75% of the ring
132 + * sizes. It seems to make sense to refill the rings entirely from the
133 + * intrrupt handler once it gets below the panic threshold, that way
134 + * we don't risk that the refilling is moved to another CPU when the
135 + * one running the interrupt handler just got the slab code hot in its
136 + * cache.
137 + */
138 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
139 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
140 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
141 +#define CRC_LEN 4
142 +#define RX_OFFSET 2
143 +
144 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
145 +#define VLAN_HDR 4
146 +#else
147 +#define VLAN_HDR 0
148 +#endif
149 +
150 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
151 + RX_OFFSET)
152 +
153 +#ifdef MODULE
154 +MODULE_LICENSE("GPL");
155 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@nbd.name>");
156 +MODULE_DESCRIPTION("AR231x Ethernet driver");
157 +#endif
158 +
159 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
160 +
161 +/* prototypes */
162 +static void ar231x_halt(struct net_device *dev);
163 +static void rx_tasklet_func(unsigned long data);
164 +static void rx_tasklet_cleanup(struct net_device *dev);
165 +static void ar231x_multicast_list(struct net_device *dev);
166 +static void ar231x_tx_timeout(struct net_device *dev);
167 +
168 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
169 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
170 + u16 value);
171 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
172 +static int ar231x_mdiobus_probe(struct net_device *dev);
173 +static void ar231x_adjust_link(struct net_device *dev);
174 +
175 +#ifndef ERR
176 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
177 +#endif
178 +
179 +#ifdef CONFIG_NET_POLL_CONTROLLER
180 +static void
181 +ar231x_netpoll(struct net_device *dev)
182 +{
183 + unsigned long flags;
184 +
185 + local_irq_save(flags);
186 + ar231x_interrupt(dev->irq, dev);
187 + local_irq_restore(flags);
188 +}
189 +#endif
190 +
191 +static const struct net_device_ops ar231x_ops = {
192 + .ndo_open = ar231x_open,
193 + .ndo_stop = ar231x_close,
194 + .ndo_start_xmit = ar231x_start_xmit,
195 + .ndo_set_rx_mode = ar231x_multicast_list,
196 + .ndo_do_ioctl = ar231x_ioctl,
197 + .ndo_change_mtu = eth_change_mtu,
198 + .ndo_validate_addr = eth_validate_addr,
199 + .ndo_set_mac_address = eth_mac_addr,
200 + .ndo_tx_timeout = ar231x_tx_timeout,
201 +#ifdef CONFIG_NET_POLL_CONTROLLER
202 + .ndo_poll_controller = ar231x_netpoll,
203 +#endif
204 +};
205 +
206 +static int ar231x_probe(struct platform_device *pdev)
207 +{
208 + struct net_device *dev;
209 + struct ar231x_private *sp;
210 + struct resource *res;
211 + unsigned long ar_eth_base;
212 + char buf[64];
213 +
214 + dev = alloc_etherdev(sizeof(struct ar231x_private));
215 +
216 + if (dev == NULL) {
217 + printk(KERN_ERR
218 + "ar231x: Unable to allocate net_device structure!\n");
219 + return -ENOMEM;
220 + }
221 +
222 + platform_set_drvdata(pdev, dev);
223 +
224 + SET_NETDEV_DEV(dev, &pdev->dev);
225 +
226 + sp = netdev_priv(dev);
227 + sp->dev = dev;
228 + sp->cfg = pdev->dev.platform_data;
229 +
230 + sprintf(buf, "eth%d_membase", pdev->id);
231 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
232 + if (!res)
233 + return -ENODEV;
234 +
235 + sp->link = 0;
236 + ar_eth_base = res->start;
237 +
238 + sprintf(buf, "eth%d_irq", pdev->id);
239 + dev->irq = platform_get_irq_byname(pdev, buf);
240 +
241 + spin_lock_init(&sp->lock);
242 +
243 + dev->features |= NETIF_F_HIGHDMA;
244 + dev->netdev_ops = &ar231x_ops;
245 +
246 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev);
247 + tasklet_disable(&sp->rx_tasklet);
248 +
249 + sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
250 + if (!sp->eth_regs) {
251 + printk("Can't remap eth registers\n");
252 + return -ENXIO;
253 + }
254 +
255 + /**
256 + * When there's only one MAC, PHY regs are typically on ENET0,
257 + * even though the MAC might be on ENET1.
258 + * So remap PHY regs separately.
259 + */
260 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
261 + if (!res) {
262 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
263 + "eth1_mii");
264 + if (!res)
265 + return -ENODEV;
266 + }
267 + sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
268 + if (!sp->phy_regs) {
269 + printk("Can't remap phy registers\n");
270 + return -ENXIO;
271 + }
272 +
273 + sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
274 + sizeof(*sp->dma_regs));
275 + if (!sp->dma_regs) {
276 + printk("Can't remap DMA registers\n");
277 + return -ENXIO;
278 + }
279 + dev->base_addr = ar_eth_base + 0x1000;
280 +
281 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
282 + sp->name[sizeof(sp->name) - 1] = '\0';
283 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
284 +
285 + if (ar231x_init(dev)) {
286 + /* ar231x_init() calls ar231x_init_cleanup() on error */
287 + kfree(dev);
288 + return -ENODEV;
289 + }
290 +
291 + if (register_netdev(dev)) {
292 + printk("%s: register_netdev failed\n", __func__);
293 + return -1;
294 + }
295 +
296 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
297 + dev->irq);
298 +
299 + sp->mii_bus = mdiobus_alloc();
300 + if (sp->mii_bus == NULL)
301 + return -1;
302 +
303 + sp->mii_bus->priv = dev;
304 + sp->mii_bus->read = ar231x_mdiobus_read;
305 + sp->mii_bus->write = ar231x_mdiobus_write;
306 + sp->mii_bus->reset = ar231x_mdiobus_reset;
307 + sp->mii_bus->name = "ar231x_eth_mii";
308 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
309 +
310 + mdiobus_register(sp->mii_bus);
311 +
312 + if (ar231x_mdiobus_probe(dev) != 0) {
313 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
314 + rx_tasklet_cleanup(dev);
315 + ar231x_init_cleanup(dev);
316 + unregister_netdev(dev);
317 + kfree(dev);
318 + return -ENODEV;
319 + }
320 +
321 + /* start link poll timer */
322 + ar231x_setup_timer(dev);
323 +
324 + return 0;
325 +}
326 +
327 +static void ar231x_multicast_list(struct net_device *dev)
328 +{
329 + struct ar231x_private *sp = netdev_priv(dev);
330 + unsigned int filter;
331 +
332 + filter = sp->eth_regs->mac_control;
333 +
334 + if (dev->flags & IFF_PROMISC)
335 + filter |= MAC_CONTROL_PR;
336 + else
337 + filter &= ~MAC_CONTROL_PR;
338 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
339 + filter |= MAC_CONTROL_PM;
340 + else
341 + filter &= ~MAC_CONTROL_PM;
342 +
343 + sp->eth_regs->mac_control = filter;
344 +}
345 +
346 +static void rx_tasklet_cleanup(struct net_device *dev)
347 +{
348 + struct ar231x_private *sp = netdev_priv(dev);
349 +
350 + /**
351 + * Tasklet may be scheduled. Need to get it removed from the list
352 + * since we're about to free the struct.
353 + */
354 +
355 + sp->unloading = 1;
356 + tasklet_enable(&sp->rx_tasklet);
357 + tasklet_kill(&sp->rx_tasklet);
358 +}
359 +
360 +static int ar231x_remove(struct platform_device *pdev)
361 +{
362 + struct net_device *dev = platform_get_drvdata(pdev);
363 + struct ar231x_private *sp = netdev_priv(dev);
364 +
365 + rx_tasklet_cleanup(dev);
366 + ar231x_init_cleanup(dev);
367 + unregister_netdev(dev);
368 + mdiobus_unregister(sp->mii_bus);
369 + mdiobus_free(sp->mii_bus);
370 + kfree(dev);
371 + return 0;
372 +}
373 +
374 +/**
375 + * Restart the AR2313 ethernet controller.
376 + */
377 +static int ar231x_restart(struct net_device *dev)
378 +{
379 + /* disable interrupts */
380 + disable_irq(dev->irq);
381 +
382 + /* stop mac */
383 + ar231x_halt(dev);
384 +
385 + /* initialize */
386 + ar231x_init(dev);
387 +
388 + /* enable interrupts */
389 + enable_irq(dev->irq);
390 +
391 + return 0;
392 +}
393 +
394 +static struct platform_driver ar231x_driver = {
395 + .driver.name = "ar231x-eth",
396 + .probe = ar231x_probe,
397 + .remove = ar231x_remove,
398 +};
399 +
400 +module_platform_driver(ar231x_driver);
401 +
402 +static void ar231x_free_descriptors(struct net_device *dev)
403 +{
404 + struct ar231x_private *sp = netdev_priv(dev);
405 +
406 + if (sp->rx_ring != NULL) {
407 + kfree((void *)KSEG0ADDR(sp->rx_ring));
408 + sp->rx_ring = NULL;
409 + sp->tx_ring = NULL;
410 + }
411 +}
412 +
413 +static int ar231x_allocate_descriptors(struct net_device *dev)
414 +{
415 + struct ar231x_private *sp = netdev_priv(dev);
416 + int size;
417 + int j;
418 + ar231x_descr_t *space;
419 +
420 + if (sp->rx_ring != NULL) {
421 + printk("%s: already done.\n", __func__);
422 + return 0;
423 + }
424 +
425 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
426 + space = kmalloc(size, GFP_KERNEL);
427 + if (space == NULL)
428 + return 1;
429 +
430 + /* invalidate caches */
431 + dma_cache_inv((unsigned int)space, size);
432 +
433 + /* now convert pointer to KSEG1 */
434 + space = (ar231x_descr_t *)KSEG1ADDR(space);
435 +
436 + memset((void *)space, 0, size);
437 +
438 + sp->rx_ring = space;
439 + space += AR2313_DESCR_ENTRIES;
440 +
441 + sp->tx_ring = space;
442 + space += AR2313_DESCR_ENTRIES;
443 +
444 + /* Initialize the transmit Descriptors */
445 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
446 + ar231x_descr_t *td = &sp->tx_ring[j];
447 +
448 + td->status = 0;
449 + td->devcs = DMA_TX1_CHAINED;
450 + td->addr = 0;
451 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
452 + }
453 +
454 + return 0;
455 +}
456 +
457 +/**
458 + * Generic cleanup handling data allocated during init. Used when the
459 + * module is unloaded or if an error occurs during initialization
460 + */
461 +static void ar231x_init_cleanup(struct net_device *dev)
462 +{
463 + struct ar231x_private *sp = netdev_priv(dev);
464 + struct sk_buff *skb;
465 + int j;
466 +
467 + ar231x_free_descriptors(dev);
468 +
469 + if (sp->eth_regs)
470 + iounmap((void *)sp->eth_regs);
471 + if (sp->dma_regs)
472 + iounmap((void *)sp->dma_regs);
473 + if (sp->phy_regs)
474 + iounmap((void *)sp->phy_regs);
475 +
476 + if (sp->rx_skb) {
477 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
478 + skb = sp->rx_skb[j];
479 + if (skb) {
480 + sp->rx_skb[j] = NULL;
481 + dev_kfree_skb(skb);
482 + }
483 + }
484 + kfree(sp->rx_skb);
485 + sp->rx_skb = NULL;
486 + }
487 +
488 + if (sp->tx_skb) {
489 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
490 + skb = sp->tx_skb[j];
491 + if (skb) {
492 + sp->tx_skb[j] = NULL;
493 + dev_kfree_skb(skb);
494 + }
495 + }
496 + kfree(sp->tx_skb);
497 + sp->tx_skb = NULL;
498 + }
499 +}
500 +
501 +static int ar231x_setup_timer(struct net_device *dev)
502 +{
503 + struct ar231x_private *sp = netdev_priv(dev);
504 +
505 + init_timer(&sp->link_timer);
506 +
507 + sp->link_timer.function = ar231x_link_timer_fn;
508 + sp->link_timer.data = (int)dev;
509 + sp->link_timer.expires = jiffies + HZ;
510 +
511 + add_timer(&sp->link_timer);
512 + return 0;
513 +}
514 +
515 +static void ar231x_link_timer_fn(unsigned long data)
516 +{
517 + struct net_device *dev = (struct net_device *)data;
518 + struct ar231x_private *sp = netdev_priv(dev);
519 +
520 + /**
521 + * See if the link status changed.
522 + * This was needed to make sure we set the PHY to the
523 + * autonegotiated value of half or full duplex.
524 + */
525 + ar231x_check_link(dev);
526 +
527 + /**
528 + * Loop faster when we don't have link.
529 + * This was needed to speed up the AP bootstrap time.
530 + */
531 + if (sp->link == 0)
532 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
533 + else
534 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
535 +}
536 +
537 +static void ar231x_check_link(struct net_device *dev)
538 +{
539 + struct ar231x_private *sp = netdev_priv(dev);
540 + u16 phy_data;
541 +
542 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
543 + if (sp->phy_data != phy_data) {
544 + if (phy_data & BMSR_LSTATUS) {
545 + /**
546 + * Link is present, ready link partner ability to
547 + * deterine duplexity.
548 + */
549 + int duplex = 0;
550 + u16 reg;
551 +
552 + sp->link = 1;
553 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
554 + MII_BMCR);
555 + if (reg & BMCR_ANENABLE) {
556 + /* auto neg enabled */
557 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
558 + MII_LPA);
559 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
560 + 1 : 0;
561 + } else {
562 + /* no auto neg, just read duplex config */
563 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
564 + }
565 +
566 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
567 + dev->name, (duplex) ? "full" : "half");
568 +
569 + if (duplex) {
570 + /* full duplex */
571 + sp->eth_regs->mac_control =
572 + (sp->eth_regs->mac_control |
573 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
574 + } else {
575 + /* half duplex */
576 + sp->eth_regs->mac_control =
577 + (sp->eth_regs->mac_control |
578 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
579 + }
580 + } else {
581 + /* no link */
582 + sp->link = 0;
583 + }
584 + sp->phy_data = phy_data;
585 + }
586 +}
587 +
588 +static int ar231x_reset_reg(struct net_device *dev)
589 +{
590 + struct ar231x_private *sp = netdev_priv(dev);
591 + unsigned int ethsal, ethsah;
592 + unsigned int flags;
593 +
594 + sp->cfg->reset_set(sp->cfg->reset_mac);
595 + mdelay(10);
596 + sp->cfg->reset_clear(sp->cfg->reset_mac);
597 + mdelay(10);
598 + sp->cfg->reset_set(sp->cfg->reset_phy);
599 + mdelay(10);
600 + sp->cfg->reset_clear(sp->cfg->reset_phy);
601 + mdelay(10);
602 +
603 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
604 + mdelay(10);
605 + sp->dma_regs->bus_mode =
606 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
607 +
608 + /* enable interrupts */
609 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
610 + DMA_STATUS_RI | DMA_STATUS_TI |
611 + DMA_STATUS_FBE;
612 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
613 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
614 + sp->dma_regs->control =
615 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
616 +
617 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
618 + sp->eth_regs->vlan_tag = (0x8100);
619 +
620 + /* Enable Ethernet Interface */
621 + flags = (MAC_CONTROL_TE | /* transmit enable */
622 + MAC_CONTROL_PM | /* pass mcast */
623 + MAC_CONTROL_F | /* full duplex */
624 + MAC_CONTROL_HBD); /* heart beat disabled */
625 +
626 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
627 + flags |= MAC_CONTROL_PR;
628 + }
629 + sp->eth_regs->mac_control = flags;
630 +
631 + /* Set all Ethernet station address registers to their initial values */
632 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
633 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
634 +
635 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
636 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
637 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
638 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
639 +
640 + sp->eth_regs->mac_addr[0] = ethsah;
641 + sp->eth_regs->mac_addr[1] = ethsal;
642 +
643 + mdelay(10);
644 +
645 + return 0;
646 +}
647 +
648 +static int ar231x_init(struct net_device *dev)
649 +{
650 + struct ar231x_private *sp = netdev_priv(dev);
651 + int ecode = 0;
652 +
653 + /* Allocate descriptors */
654 + if (ar231x_allocate_descriptors(dev)) {
655 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
656 + dev->name, __func__);
657 + ecode = -EAGAIN;
658 + goto init_error;
659 + }
660 +
661 + /* Get the memory for the skb rings */
662 + if (sp->rx_skb == NULL) {
663 + sp->rx_skb =
664 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
665 + GFP_KERNEL);
666 + if (!(sp->rx_skb)) {
667 + printk("%s: %s: rx_skb kmalloc failed\n",
668 + dev->name, __func__);
669 + ecode = -EAGAIN;
670 + goto init_error;
671 + }
672 + }
673 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
674 +
675 + if (sp->tx_skb == NULL) {
676 + sp->tx_skb =
677 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
678 + GFP_KERNEL);
679 + if (!(sp->tx_skb)) {
680 + printk("%s: %s: tx_skb kmalloc failed\n",
681 + dev->name, __func__);
682 + ecode = -EAGAIN;
683 + goto init_error;
684 + }
685 + }
686 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
687 +
688 + /**
689 + * Set tx_csm before we start receiving interrupts, otherwise
690 + * the interrupt handler might think it is supposed to process
691 + * tx ints before we are up and running, which may cause a null
692 + * pointer access in the int handler.
693 + */
694 + sp->rx_skbprd = 0;
695 + sp->cur_rx = 0;
696 + sp->tx_prd = 0;
697 + sp->tx_csm = 0;
698 +
699 + /* Zero the stats before starting the interface */
700 + memset(&dev->stats, 0, sizeof(dev->stats));
701 +
702 + /**
703 + * We load the ring here as there seem to be no way to tell the
704 + * firmware to wipe the ring without re-initializing it.
705 + */
706 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
707 +
708 + /* Init hardware */
709 + ar231x_reset_reg(dev);
710 +
711 + /* Get the IRQ */
712 + ecode = request_irq(dev->irq, &ar231x_interrupt, 0,
713 + dev->name, dev);
714 + if (ecode) {
715 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
716 + dev->name, __func__, dev->irq);
717 + goto init_error;
718 + }
719 +
720 + tasklet_enable(&sp->rx_tasklet);
721 +
722 + return 0;
723 +
724 +init_error:
725 + ar231x_init_cleanup(dev);
726 + return ecode;
727 +}
728 +
729 +/**
730 + * Load the rx ring.
731 + *
732 + * Loading rings is safe without holding the spin lock since this is
733 + * done only before the device is enabled, thus no interrupts are
734 + * generated and by the interrupt handler/tasklet handler.
735 + */
736 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
737 +{
738 + struct ar231x_private *sp = netdev_priv(dev);
739 + short i, idx;
740 +
741 + idx = sp->rx_skbprd;
742 +
743 + for (i = 0; i < nr_bufs; i++) {
744 + struct sk_buff *skb;
745 + ar231x_descr_t *rd;
746 +
747 + if (sp->rx_skb[idx])
748 + break;
749 +
750 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
751 + if (!skb) {
752 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
753 + __func__);
754 + break;
755 + }
756 +
757 + /* Make sure IP header starts on a fresh cache line */
758 + skb->dev = dev;
759 + sp->rx_skb[idx] = skb;
760 +
761 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
762 +
763 + /* initialize dma descriptor */
764 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
765 + DMA_RX1_CHAINED);
766 + rd->addr = virt_to_phys(skb->data);
767 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
768 + rd->status = DMA_RX_OWN;
769 +
770 + idx = DSC_NEXT(idx);
771 + }
772 +
773 + if (i)
774 + sp->rx_skbprd = idx;
775 +}
776 +
777 +#define AR2313_MAX_PKTS_PER_CALL 64
778 +
779 +static int ar231x_rx_int(struct net_device *dev)
780 +{
781 + struct ar231x_private *sp = netdev_priv(dev);
782 + struct sk_buff *skb, *skb_new;
783 + ar231x_descr_t *rxdesc;
784 + unsigned int status;
785 + u32 idx;
786 + int pkts = 0;
787 + int rval;
788 +
789 + idx = sp->cur_rx;
790 +
791 + /* process at most the entire ring and then wait for another int */
792 + while (1) {
793 + rxdesc = &sp->rx_ring[idx];
794 + status = rxdesc->status;
795 +
796 + if (status & DMA_RX_OWN) {
797 + /* SiByte owns descriptor or descr not yet filled in */
798 + rval = 0;
799 + break;
800 + }
801 +
802 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
803 + rval = 1;
804 + break;
805 + }
806 +
807 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
808 + dev->stats.rx_errors++;
809 + dev->stats.rx_dropped++;
810 +
811 + /* add statistics counters */
812 + if (status & DMA_RX_ERR_CRC)
813 + dev->stats.rx_crc_errors++;
814 + if (status & DMA_RX_ERR_COL)
815 + dev->stats.rx_over_errors++;
816 + if (status & DMA_RX_ERR_LENGTH)
817 + dev->stats.rx_length_errors++;
818 + if (status & DMA_RX_ERR_RUNT)
819 + dev->stats.rx_over_errors++;
820 + if (status & DMA_RX_ERR_DESC)
821 + dev->stats.rx_over_errors++;
822 +
823 + } else {
824 + /* alloc new buffer. */
825 + skb_new = netdev_alloc_skb_ip_align(dev,
826 + AR2313_BUFSIZE);
827 + if (skb_new != NULL) {
828 + skb = sp->rx_skb[idx];
829 + /* set skb */
830 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
831 + 0x3fff) - CRC_LEN);
832 +
833 + dev->stats.rx_bytes += skb->len;
834 + skb->protocol = eth_type_trans(skb, dev);
835 + /* pass the packet to upper layers */
836 + netif_rx(skb);
837 +
838 + skb_new->dev = dev;
839 + /* reset descriptor's curr_addr */
840 + rxdesc->addr = virt_to_phys(skb_new->data);
841 +
842 + dev->stats.rx_packets++;
843 + sp->rx_skb[idx] = skb_new;
844 + } else {
845 + dev->stats.rx_dropped++;
846 + }
847 + }
848 +
849 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
850 + DMA_RX1_CHAINED);
851 + rxdesc->status = DMA_RX_OWN;
852 +
853 + idx = DSC_NEXT(idx);
854 + }
855 +
856 + sp->cur_rx = idx;
857 +
858 + return rval;
859 +}
860 +
861 +static void ar231x_tx_int(struct net_device *dev)
862 +{
863 + struct ar231x_private *sp = netdev_priv(dev);
864 + u32 idx;
865 + struct sk_buff *skb;
866 + ar231x_descr_t *txdesc;
867 + unsigned int status = 0;
868 +
869 + idx = sp->tx_csm;
870 +
871 + while (idx != sp->tx_prd) {
872 + txdesc = &sp->tx_ring[idx];
873 + status = txdesc->status;
874 +
875 + if (status & DMA_TX_OWN) {
876 + /* ar231x dma still owns descr */
877 + break;
878 + }
879 + /* done with this descriptor */
880 + dma_unmap_single(NULL, txdesc->addr,
881 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
882 + DMA_TO_DEVICE);
883 + txdesc->status = 0;
884 +
885 + if (status & DMA_TX_ERROR) {
886 + dev->stats.tx_errors++;
887 + dev->stats.tx_dropped++;
888 + if (status & DMA_TX_ERR_UNDER)
889 + dev->stats.tx_fifo_errors++;
890 + if (status & DMA_TX_ERR_HB)
891 + dev->stats.tx_heartbeat_errors++;
892 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
893 + dev->stats.tx_carrier_errors++;
894 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
895 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
896 + dev->stats.tx_aborted_errors++;
897 + } else {
898 + /* transmit OK */
899 + dev->stats.tx_packets++;
900 + }
901 +
902 + skb = sp->tx_skb[idx];
903 + sp->tx_skb[idx] = NULL;
904 + idx = DSC_NEXT(idx);
905 + dev->stats.tx_bytes += skb->len;
906 + dev_kfree_skb_irq(skb);
907 + }
908 +
909 + sp->tx_csm = idx;
910 +}
911 +
912 +static void rx_tasklet_func(unsigned long data)
913 +{
914 + struct net_device *dev = (struct net_device *)data;
915 + struct ar231x_private *sp = netdev_priv(dev);
916 +
917 + if (sp->unloading)
918 + return;
919 +
920 + if (ar231x_rx_int(dev)) {
921 + tasklet_hi_schedule(&sp->rx_tasklet);
922 + } else {
923 + unsigned long flags;
924 +
925 + spin_lock_irqsave(&sp->lock, flags);
926 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
927 + spin_unlock_irqrestore(&sp->lock, flags);
928 + }
929 +}
930 +
931 +static void rx_schedule(struct net_device *dev)
932 +{
933 + struct ar231x_private *sp = netdev_priv(dev);
934 +
935 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
936 +
937 + tasklet_hi_schedule(&sp->rx_tasklet);
938 +}
939 +
940 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
941 +{
942 + struct net_device *dev = (struct net_device *)dev_id;
943 + struct ar231x_private *sp = netdev_priv(dev);
944 + unsigned int status, enabled;
945 +
946 + /* clear interrupt */
947 + /* Don't clear RI bit if currently disabled */
948 + status = sp->dma_regs->status;
949 + enabled = sp->dma_regs->intr_ena;
950 + sp->dma_regs->status = status & enabled;
951 +
952 + if (status & DMA_STATUS_NIS) {
953 + /* normal status */
954 + /**
955 + * Don't schedule rx processing if interrupt
956 + * is already disabled.
957 + */
958 + if (status & enabled & DMA_STATUS_RI) {
959 + /* receive interrupt */
960 + rx_schedule(dev);
961 + }
962 + if (status & DMA_STATUS_TI) {
963 + /* transmit interrupt */
964 + ar231x_tx_int(dev);
965 + }
966 + }
967 +
968 + /* abnormal status */
969 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
970 + ar231x_restart(dev);
971 +
972 + return IRQ_HANDLED;
973 +}
974 +
975 +static int ar231x_open(struct net_device *dev)
976 +{
977 + struct ar231x_private *sp = netdev_priv(dev);
978 + unsigned int ethsal, ethsah;
979 +
980 + /* reset the hardware, in case the MAC address changed */
981 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
982 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
983 +
984 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
985 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
986 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
987 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
988 +
989 + sp->eth_regs->mac_addr[0] = ethsah;
990 + sp->eth_regs->mac_addr[1] = ethsal;
991 +
992 + mdelay(10);
993 +
994 + dev->mtu = 1500;
995 + netif_start_queue(dev);
996 +
997 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
998 +
999 + return 0;
1000 +}
1001 +
1002 +static void ar231x_tx_timeout(struct net_device *dev)
1003 +{
1004 + struct ar231x_private *sp = netdev_priv(dev);
1005 + unsigned long flags;
1006 +
1007 + spin_lock_irqsave(&sp->lock, flags);
1008 + ar231x_restart(dev);
1009 + spin_unlock_irqrestore(&sp->lock, flags);
1010 +}
1011 +
1012 +static void ar231x_halt(struct net_device *dev)
1013 +{
1014 + struct ar231x_private *sp = netdev_priv(dev);
1015 + int j;
1016 +
1017 + tasklet_disable(&sp->rx_tasklet);
1018 +
1019 + /* kill the MAC */
1020 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1021 + MAC_CONTROL_TE); /* disable Transmits */
1022 + /* stop dma */
1023 + sp->dma_regs->control = 0;
1024 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1025 +
1026 + /* place phy and MAC in reset */
1027 + sp->cfg->reset_set(sp->cfg->reset_mac);
1028 + sp->cfg->reset_set(sp->cfg->reset_phy);
1029 +
1030 + /* free buffers on tx ring */
1031 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1032 + struct sk_buff *skb;
1033 + ar231x_descr_t *txdesc;
1034 +
1035 + txdesc = &sp->tx_ring[j];
1036 + txdesc->descr = 0;
1037 +
1038 + skb = sp->tx_skb[j];
1039 + if (skb) {
1040 + dev_kfree_skb(skb);
1041 + sp->tx_skb[j] = NULL;
1042 + }
1043 + }
1044 +}
1045 +
1046 +/**
1047 + * close should do nothing. Here's why. It's called when
1048 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1049 + * the irq is gone forever ! When bond0 is made 'up' again,
1050 + * the ar231x_open () does not call request_irq (). Worse,
1051 + * the call to ar231x_halt() generates a WDOG reset due to
1052 + * the write to reset register and the box reboots.
1053 + * Commenting this out is good since it allows the
1054 + * system to resume when bond0 is made up again.
1055 + */
1056 +static int ar231x_close(struct net_device *dev)
1057 +{
1058 +#if 0
1059 + /* Disable interrupts */
1060 + disable_irq(dev->irq);
1061 +
1062 + /**
1063 + * Without (or before) releasing irq and stopping hardware, this
1064 + * is an absolute non-sense, by the way. It will be reset instantly
1065 + * by the first irq.
1066 + */
1067 + netif_stop_queue(dev);
1068 +
1069 + /* stop the MAC and DMA engines */
1070 + ar231x_halt(dev);
1071 +
1072 + /* release the interrupt */
1073 + free_irq(dev->irq, dev);
1074 +
1075 +#endif
1076 + return 0;
1077 +}
1078 +
1079 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1080 +{
1081 + struct ar231x_private *sp = netdev_priv(dev);
1082 + ar231x_descr_t *td;
1083 + u32 idx;
1084 +
1085 + idx = sp->tx_prd;
1086 + td = &sp->tx_ring[idx];
1087 +
1088 + if (td->status & DMA_TX_OWN) {
1089 + /* free skbuf and lie to the caller that we sent it out */
1090 + dev->stats.tx_dropped++;
1091 + dev_kfree_skb(skb);
1092 +
1093 + /* restart transmitter in case locked */
1094 + sp->dma_regs->xmt_poll = 0;
1095 + return 0;
1096 + }
1097 +
1098 + /* Setup the transmit descriptor. */
1099 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1100 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1101 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1102 + td->status = DMA_TX_OWN;
1103 +
1104 + /* kick transmitter last */
1105 + sp->dma_regs->xmt_poll = 0;
1106 +
1107 + sp->tx_skb[idx] = skb;
1108 + idx = DSC_NEXT(idx);
1109 + sp->tx_prd = idx;
1110 +
1111 + return 0;
1112 +}
1113 +
1114 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1115 +{
1116 + struct ar231x_private *sp = netdev_priv(dev);
1117 +
1118 + switch (cmd) {
1119 + case SIOCGMIIPHY:
1120 + case SIOCGMIIREG:
1121 + case SIOCSMIIREG:
1122 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1123 +
1124 + default:
1125 + break;
1126 + }
1127 +
1128 + return -EOPNOTSUPP;
1129 +}
1130 +
1131 +static void ar231x_adjust_link(struct net_device *dev)
1132 +{
1133 + struct ar231x_private *sp = netdev_priv(dev);
1134 + unsigned int mc;
1135 +
1136 + if (!sp->phy_dev->link)
1137 + return;
1138 +
1139 + if (sp->phy_dev->duplex != sp->oldduplex) {
1140 + mc = readl(&sp->eth_regs->mac_control);
1141 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1142 + if (sp->phy_dev->duplex)
1143 + mc |= MAC_CONTROL_F;
1144 + else
1145 + mc |= MAC_CONTROL_DRO;
1146 + writel(mc, &sp->eth_regs->mac_control);
1147 + sp->oldduplex = sp->phy_dev->duplex;
1148 + }
1149 +}
1150 +
1151 +#define MII_ADDR(phy, reg) \
1152 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1153 +
1154 +static int
1155 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1156 +{
1157 + struct net_device *const dev = bus->priv;
1158 + struct ar231x_private *sp = netdev_priv(dev);
1159 + volatile MII *ethernet = sp->phy_regs;
1160 +
1161 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1162 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1163 + ;
1164 + return ethernet->mii_data >> MII_DATA_SHIFT;
1165 +}
1166 +
1167 +static int
1168 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1169 +{
1170 + struct net_device *const dev = bus->priv;
1171 + struct ar231x_private *sp = netdev_priv(dev);
1172 + volatile MII *ethernet = sp->phy_regs;
1173 +
1174 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1175 + ;
1176 + ethernet->mii_data = value << MII_DATA_SHIFT;
1177 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1178 +
1179 + return 0;
1180 +}
1181 +
1182 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1183 +{
1184 + struct net_device *const dev = bus->priv;
1185 +
1186 + ar231x_reset_reg(dev);
1187 +
1188 + return 0;
1189 +}
1190 +
1191 +static int ar231x_mdiobus_probe(struct net_device *dev)
1192 +{
1193 + struct ar231x_private *const sp = netdev_priv(dev);
1194 + struct phy_device *phydev = NULL;
1195 +
1196 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1197 + phydev = phy_find_first(sp->mii_bus);
1198 + if (!phydev) {
1199 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1200 + return -1;
1201 + }
1202 +
1203 + /* now we are supposed to have a proper phydev, to attach to... */
1204 + BUG_ON(phydev->attached_dev);
1205 +
1206 + phydev = phy_connect(dev, phydev_name(phydev), &ar231x_adjust_link,
1207 + PHY_INTERFACE_MODE_MII);
1208 + if (IS_ERR(phydev)) {
1209 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1210 + return PTR_ERR(phydev);
1211 + }
1212 +
1213 + /* mask with MAC supported features */
1214 + phydev->supported &= (SUPPORTED_10baseT_Half
1215 + | SUPPORTED_10baseT_Full
1216 + | SUPPORTED_100baseT_Half
1217 + | SUPPORTED_100baseT_Full
1218 + | SUPPORTED_Autoneg
1219 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1220 + | SUPPORTED_MII
1221 + | SUPPORTED_TP);
1222 +
1223 + phydev->advertising = phydev->supported;
1224 +
1225 + sp->oldduplex = -1;
1226 + sp->phy_dev = phydev;
1227 + sp->phy = phydev->mdio.addr;
1228 +
1229 + printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1230 + dev->name, phydev->drv->name, phydev_name(phydev));
1231 +
1232 + return 0;
1233 +}
1234 +
1235 --- /dev/null
1236 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1237 @@ -0,0 +1,288 @@
1238 +/*
1239 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1240 + *
1241 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1242 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1243 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
1244 + *
1245 + * Thanks to Atheros for providing hardware and documentation
1246 + * enabling me to write this driver.
1247 + *
1248 + * This program is free software; you can redistribute it and/or modify
1249 + * it under the terms of the GNU General Public License as published by
1250 + * the Free Software Foundation; either version 2 of the License, or
1251 + * (at your option) any later version.
1252 + */
1253 +
1254 +#ifndef _AR2313_H_
1255 +#define _AR2313_H_
1256 +
1257 +#include <linux/interrupt.h>
1258 +#include <generated/autoconf.h>
1259 +#include <linux/bitops.h>
1260 +#include <ath25_platform.h>
1261 +
1262 +/* probe link timer - 5 secs */
1263 +#define LINK_TIMER (5*HZ)
1264 +
1265 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1266 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1267 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1268 +
1269 +#define AR2313_TX_TIMEOUT (HZ/4)
1270 +
1271 +/* Rings */
1272 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1273 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1274 +
1275 +#define AR2313_MBGET 2
1276 +#define AR2313_MBSET 3
1277 +#define AR2313_PCI_RECONFIG 4
1278 +#define AR2313_PCI_DUMP 5
1279 +#define AR2313_TEST_PANIC 6
1280 +#define AR2313_TEST_NULLPTR 7
1281 +#define AR2313_READ_DATA 8
1282 +#define AR2313_WRITE_DATA 9
1283 +#define AR2313_GET_VERSION 10
1284 +#define AR2313_TEST_HANG 11
1285 +#define AR2313_SYNC 12
1286 +
1287 +#define DMA_RX_ERR_CRC BIT(1)
1288 +#define DMA_RX_ERR_DRIB BIT(2)
1289 +#define DMA_RX_ERR_MII BIT(3)
1290 +#define DMA_RX_EV2 BIT(5)
1291 +#define DMA_RX_ERR_COL BIT(6)
1292 +#define DMA_RX_LONG BIT(7)
1293 +#define DMA_RX_LS BIT(8) /* last descriptor */
1294 +#define DMA_RX_FS BIT(9) /* first descriptor */
1295 +#define DMA_RX_MF BIT(10) /* multicast frame */
1296 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1297 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1298 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1299 +#define DMA_RX_ERROR BIT(15) /* error summary */
1300 +#define DMA_RX_LEN_MASK 0x3fff0000
1301 +#define DMA_RX_LEN_SHIFT 16
1302 +#define DMA_RX_FILT BIT(30)
1303 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1304 +
1305 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1306 +#define DMA_RX1_BSIZE_SHIFT 0
1307 +#define DMA_RX1_CHAINED BIT(24)
1308 +#define DMA_RX1_RER BIT(25)
1309 +
1310 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1311 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1312 +#define DMA_TX_COL_MASK 0x78
1313 +#define DMA_TX_COL_SHIFT 3
1314 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1315 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1316 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1317 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1318 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1319 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1320 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1321 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1322 +
1323 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1324 +#define DMA_TX1_BSIZE_SHIFT 0
1325 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1326 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1327 +#define DMA_TX1_FS BIT(29) /* first segment */
1328 +#define DMA_TX1_LS BIT(30) /* last segment */
1329 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1330 +
1331 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1332 +
1333 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1334 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1335 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1336 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1337 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1338 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1339 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1340 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1341 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1342 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1343 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1344 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1345 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1346 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1347 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1348 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1349 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1350 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1351 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1352 +
1353 +#define MII_ADDR_BUSY BIT(0)
1354 +#define MII_ADDR_WRITE BIT(1)
1355 +#define MII_ADDR_REG_SHIFT 6
1356 +#define MII_ADDR_PHY_SHIFT 11
1357 +#define MII_DATA_SHIFT 0
1358 +
1359 +#define FLOW_CONTROL_FCE BIT(1)
1360 +
1361 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1362 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1363 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1364 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1365 +
1366 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1367 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1368 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1369 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1370 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1371 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1372 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1373 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1374 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1375 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1376 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1377 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1378 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1379 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1380 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1381 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1382 +
1383 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1384 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1385 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1386 +
1387 +typedef struct {
1388 + volatile unsigned int status; /* OWN, Device control and status. */
1389 + volatile unsigned int devcs; /* pkt Control bits + Length */
1390 + volatile unsigned int addr; /* Current Address. */
1391 + volatile unsigned int descr; /* Next descriptor in chain. */
1392 +} ar231x_descr_t;
1393 +
1394 +/**
1395 + * New Combo structure for Both Eth0 AND eth1
1396 + *
1397 + * Don't directly access MII related regs since phy chip could be actually
1398 + * connected to another ethernet block.
1399 + */
1400 +typedef struct {
1401 + volatile unsigned int mac_control; /* 0x00 */
1402 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1403 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1404 + volatile unsigned int __mii_addr; /* 0x14 */
1405 + volatile unsigned int __mii_data; /* 0x18 */
1406 + volatile unsigned int flow_control; /* 0x1c */
1407 + volatile unsigned int vlan_tag; /* 0x20 */
1408 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1409 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1410 +} ETHERNET_STRUCT;
1411 +
1412 +typedef struct {
1413 + volatile unsigned int mii_addr;
1414 + volatile unsigned int mii_data;
1415 +} MII;
1416 +
1417 +/********************************************************************
1418 + * Interrupt controller
1419 + ********************************************************************/
1420 +
1421 +typedef struct {
1422 + volatile unsigned int wdog_control; /* 0x08 */
1423 + volatile unsigned int wdog_timer; /* 0x0c */
1424 + volatile unsigned int misc_status; /* 0x10 */
1425 + volatile unsigned int misc_mask; /* 0x14 */
1426 + volatile unsigned int global_status; /* 0x18 */
1427 + volatile unsigned int reserved; /* 0x1c */
1428 + volatile unsigned int reset_control; /* 0x20 */
1429 +} INTERRUPT;
1430 +
1431 +/********************************************************************
1432 + * DMA controller
1433 + ********************************************************************/
1434 +typedef struct {
1435 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1436 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1437 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1438 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1439 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1440 + volatile unsigned int status; /* 0x14 (CSR5) */
1441 + volatile unsigned int control; /* 0x18 (CSR6) */
1442 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1443 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1444 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1445 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1446 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1447 +} DMA;
1448 +
1449 +/**
1450 + * Struct private for the Sibyte.
1451 + *
1452 + * Elements are grouped so variables used by the tx handling goes
1453 + * together, and will go into the same cache lines etc. in order to
1454 + * avoid cache line contention between the rx and tx handling on SMP.
1455 + *
1456 + * Frequently accessed variables are put at the beginning of the
1457 + * struct to help the compiler generate better/shorter code.
1458 + */
1459 +struct ar231x_private {
1460 + struct net_device *dev;
1461 + int version;
1462 + u32 mb[2];
1463 +
1464 + volatile MII *phy_regs;
1465 + volatile ETHERNET_STRUCT *eth_regs;
1466 + volatile DMA *dma_regs;
1467 + struct ar231x_eth *cfg;
1468 +
1469 + spinlock_t lock; /* Serialise access to device */
1470 +
1471 + /* RX and TX descriptors, must be adjacent */
1472 + ar231x_descr_t *rx_ring;
1473 + ar231x_descr_t *tx_ring;
1474 +
1475 + struct sk_buff **rx_skb;
1476 + struct sk_buff **tx_skb;
1477 +
1478 + /* RX elements */
1479 + u32 rx_skbprd;
1480 + u32 cur_rx;
1481 +
1482 + /* TX elements */
1483 + u32 tx_prd;
1484 + u32 tx_csm;
1485 +
1486 + /* Misc elements */
1487 + char name[48];
1488 + struct {
1489 + u32 address;
1490 + u32 length;
1491 + char *mapping;
1492 + } desc;
1493 +
1494 + struct timer_list link_timer;
1495 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1496 + unsigned short mac;
1497 + unsigned short link; /* 0 - link down, 1 - link up */
1498 + u16 phy_data;
1499 +
1500 + struct tasklet_struct rx_tasklet;
1501 + int unloading;
1502 +
1503 + struct phy_device *phy_dev;
1504 + struct mii_bus *mii_bus;
1505 + int oldduplex;
1506 +};
1507 +
1508 +/* Prototypes */
1509 +static int ar231x_init(struct net_device *dev);
1510 +#ifdef TX_TIMEOUT
1511 +static void ar231x_tx_timeout(struct net_device *dev);
1512 +#endif
1513 +static int ar231x_restart(struct net_device *dev);
1514 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1515 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1516 +static int ar231x_open(struct net_device *dev);
1517 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1518 +static int ar231x_close(struct net_device *dev);
1519 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1520 +static void ar231x_init_cleanup(struct net_device *dev);
1521 +static int ar231x_setup_timer(struct net_device *dev);
1522 +static void ar231x_link_timer_fn(unsigned long data);
1523 +static void ar231x_check_link(struct net_device *dev);
1524 +
1525 +#endif /* _AR2313_H_ */
1526 --- a/arch/mips/ath25/ar2315_regs.h
1527 +++ b/arch/mips/ath25/ar2315_regs.h
1528 @@ -57,6 +57,9 @@
1529 #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
1530 #define AR2315_PCI_EXT_SIZE 0x40000000
1531
1532 +/* MII registers offset inside Ethernet MMR region */
1533 +#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
1534 +
1535 /*
1536 * Configuration registers
1537 */
1538 --- a/arch/mips/ath25/ar5312_regs.h
1539 +++ b/arch/mips/ath25/ar5312_regs.h
1540 @@ -64,6 +64,10 @@
1541 #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1542 #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1543
1544 +/* MII registers offset inside Ethernet MMR region */
1545 +#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
1546 +#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
1547 +
1548 /* Reset/Timer Block Address Map */
1549 #define AR5312_TIMER 0x0000 /* countdown timer */
1550 #define AR5312_RELOAD 0x0004 /* timer reload value */
1551 --- a/arch/mips/ath25/ar2315.c
1552 +++ b/arch/mips/ath25/ar2315.c
1553 @@ -136,6 +136,8 @@ static void ar2315_irq_dispatch(void)
1554
1555 if (pending & CAUSEF_IP3)
1556 do_IRQ(AR2315_IRQ_WLAN0);
1557 + else if (pending & CAUSEF_IP4)
1558 + do_IRQ(AR2315_IRQ_ENET0);
1559 #ifdef CONFIG_PCI_AR2315
1560 else if (pending & CAUSEF_IP5)
1561 do_IRQ(AR2315_IRQ_LCBUS_PCI);
1562 @@ -169,6 +171,29 @@ void __init ar2315_arch_init_irq(void)
1563 ar2315_misc_irq_domain = domain;
1564 }
1565
1566 +static void ar2315_device_reset_set(u32 mask)
1567 +{
1568 + u32 val;
1569 +
1570 + val = ar2315_rst_reg_read(AR2315_RESET);
1571 + ar2315_rst_reg_write(AR2315_RESET, val | mask);
1572 +}
1573 +
1574 +static void ar2315_device_reset_clear(u32 mask)
1575 +{
1576 + u32 val;
1577 +
1578 + val = ar2315_rst_reg_read(AR2315_RESET);
1579 + ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
1580 +}
1581 +
1582 +static struct ar231x_eth ar2315_eth_data = {
1583 + .reset_set = ar2315_device_reset_set,
1584 + .reset_clear = ar2315_device_reset_clear,
1585 + .reset_mac = AR2315_RESET_ENET0,
1586 + .reset_phy = AR2315_RESET_EPHY0,
1587 +};
1588 +
1589 static struct resource ar2315_gpio_res[] = {
1590 {
1591 .name = "ar2315-gpio",
1592 @@ -205,6 +230,11 @@ void __init ar2315_init_devices(void)
1593 ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
1594 platform_device_register(&ar2315_gpio);
1595
1596 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
1597 + ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
1598 + AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
1599 + &ar2315_eth_data);
1600 +
1601 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
1602 }
1603
1604 --- a/arch/mips/ath25/ar5312.c
1605 +++ b/arch/mips/ath25/ar5312.c
1606 @@ -132,6 +132,10 @@ static void ar5312_irq_dispatch(void)
1607
1608 if (pending & CAUSEF_IP2)
1609 do_IRQ(AR5312_IRQ_WLAN0);
1610 + else if (pending & CAUSEF_IP3)
1611 + do_IRQ(AR5312_IRQ_ENET0);
1612 + else if (pending & CAUSEF_IP4)
1613 + do_IRQ(AR5312_IRQ_ENET1);
1614 else if (pending & CAUSEF_IP5)
1615 do_IRQ(AR5312_IRQ_WLAN1);
1616 else if (pending & CAUSEF_IP6)
1617 @@ -163,6 +167,36 @@ void __init ar5312_arch_init_irq(void)
1618 ar5312_misc_irq_domain = domain;
1619 }
1620
1621 +static void ar5312_device_reset_set(u32 mask)
1622 +{
1623 + u32 val;
1624 +
1625 + val = ar5312_rst_reg_read(AR5312_RESET);
1626 + ar5312_rst_reg_write(AR5312_RESET, val | mask);
1627 +}
1628 +
1629 +static void ar5312_device_reset_clear(u32 mask)
1630 +{
1631 + u32 val;
1632 +
1633 + val = ar5312_rst_reg_read(AR5312_RESET);
1634 + ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
1635 +}
1636 +
1637 +static struct ar231x_eth ar5312_eth0_data = {
1638 + .reset_set = ar5312_device_reset_set,
1639 + .reset_clear = ar5312_device_reset_clear,
1640 + .reset_mac = AR5312_RESET_ENET0,
1641 + .reset_phy = AR5312_RESET_EPHY0,
1642 +};
1643 +
1644 +static struct ar231x_eth ar5312_eth1_data = {
1645 + .reset_set = ar5312_device_reset_set,
1646 + .reset_clear = ar5312_device_reset_clear,
1647 + .reset_mac = AR5312_RESET_ENET1,
1648 + .reset_phy = AR5312_RESET_EPHY1,
1649 +};
1650 +
1651 static struct physmap_flash_data ar5312_flash_data = {
1652 .width = 2,
1653 };
1654 @@ -243,6 +277,7 @@ static void __init ar5312_flash_init(voi
1655 void __init ar5312_init_devices(void)
1656 {
1657 struct ath25_boarddata *config;
1658 + u8 *c;
1659
1660 ar5312_flash_init();
1661
1662 @@ -266,8 +301,30 @@ void __init ar5312_init_devices(void)
1663
1664 platform_device_register(&ar5312_gpio);
1665
1666 + /* Fix up MAC addresses if necessary */
1667 + if (is_broadcast_ether_addr(config->enet0_mac))
1668 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1669 +
1670 + /* If ENET0 and ENET1 have the same mac address,
1671 + * increment the one from ENET1 */
1672 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1673 + c = config->enet1_mac + 5;
1674 + while ((c >= config->enet1_mac) && !(++(*c)))
1675 + c--;
1676 + }
1677 +
1678 switch (ath25_soc) {
1679 case ATH25_SOC_AR5312:
1680 + ar5312_eth0_data.macaddr = config->enet0_mac;
1681 + ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
1682 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
1683 + &ar5312_eth0_data);
1684 +
1685 + ar5312_eth1_data.macaddr = config->enet1_mac;
1686 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
1687 + AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
1688 + &ar5312_eth1_data);
1689 +
1690 if (!ath25_board.radio)
1691 return;
1692
1693 @@ -276,8 +333,18 @@ void __init ar5312_init_devices(void)
1694
1695 ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1696 break;
1697 + /*
1698 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1699 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1700 + */
1701 case ATH25_SOC_AR2312:
1702 case ATH25_SOC_AR2313:
1703 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1704 + ar5312_eth1_data.macaddr = config->enet0_mac;
1705 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
1706 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
1707 + &ar5312_eth1_data);
1708 +
1709 if (!ath25_board.radio)
1710 return;
1711 break;
1712 --- a/arch/mips/ath25/devices.h
1713 +++ b/arch/mips/ath25/devices.h
1714 @@ -32,6 +32,8 @@ extern struct ar231x_board_config ath25_
1715 extern void (*ath25_irq_dispatch)(void);
1716
1717 int ath25_find_config(phys_addr_t offset, unsigned long size);
1718 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
1719 + int irq, void *pdata);
1720 void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
1721 int ath25_add_wmac(int nr, u32 base, int irq);
1722
1723 --- a/arch/mips/ath25/devices.c
1724 +++ b/arch/mips/ath25/devices.c
1725 @@ -12,6 +12,51 @@
1726 struct ar231x_board_config ath25_board;
1727 enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
1728
1729 +static struct resource ath25_eth0_res[] = {
1730 + {
1731 + .name = "eth0_membase",
1732 + .flags = IORESOURCE_MEM,
1733 + },
1734 + {
1735 + .name = "eth0_mii",
1736 + .flags = IORESOURCE_MEM,
1737 + },
1738 + {
1739 + .name = "eth0_irq",
1740 + .flags = IORESOURCE_IRQ,
1741 + }
1742 +};
1743 +
1744 +static struct resource ath25_eth1_res[] = {
1745 + {
1746 + .name = "eth1_membase",
1747 + .flags = IORESOURCE_MEM,
1748 + },
1749 + {
1750 + .name = "eth1_mii",
1751 + .flags = IORESOURCE_MEM,
1752 + },
1753 + {
1754 + .name = "eth1_irq",
1755 + .flags = IORESOURCE_IRQ,
1756 + }
1757 +};
1758 +
1759 +static struct platform_device ath25_eth[] = {
1760 + {
1761 + .id = 0,
1762 + .name = "ar231x-eth",
1763 + .resource = ath25_eth0_res,
1764 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
1765 + },
1766 + {
1767 + .id = 1,
1768 + .name = "ar231x-eth",
1769 + .resource = ath25_eth1_res,
1770 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
1771 + }
1772 +};
1773 +
1774 static struct resource ath25_wmac0_res[] = {
1775 {
1776 .name = "wmac0_membase",
1777 @@ -70,6 +115,25 @@ const char *get_system_type(void)
1778 return soc_type_strings[ath25_soc];
1779 }
1780
1781 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
1782 + u32 mii_base, int irq, void *pdata)
1783 +{
1784 + struct resource *res;
1785 +
1786 + ath25_eth[nr].dev.platform_data = pdata;
1787 + res = &ath25_eth[nr].resource[0];
1788 + res->start = base;
1789 + res->end = base + 0x2000 - 1;
1790 + res++;
1791 + res->name = mii_name;
1792 + res->start = mii_base;
1793 + res->end = mii_base + 8 - 1;
1794 + res++;
1795 + res->start = irq;
1796 + res->end = irq;
1797 + return platform_device_register(&ath25_eth[nr]);
1798 +}
1799 +
1800 void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
1801 {
1802 struct uart_port s;
1803 --- a/arch/mips/include/asm/mach-ath25/ath25_platform.h
1804 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
1805 @@ -70,4 +70,15 @@ struct ar231x_board_config {
1806 const char *radio;
1807 };
1808
1809 +/*
1810 + * Platform device information for the Ethernet MAC
1811 + */
1812 +struct ar231x_eth {
1813 + void (*reset_set)(u32);
1814 + void (*reset_clear)(u32);
1815 + u32 reset_mac;
1816 + u32 reset_phy;
1817 + char *macaddr;
1818 +};
1819 +
1820 #endif /* __ASM_MACH_ATH25_PLATFORM_H */
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