1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
10 compatible = "dlink,dir-825-b1", "qca,ar7161";
11 model = "D-Link DIR825B1";
14 led-boot = &orange_power;
15 led-failsafe = &orange_power;
16 led-running = &blue_power;
17 led-upgrade = &orange_power;
21 bootargs = "console=ttyS0,115200";
25 compatible = "fixed-clock";
27 clock-output-names = "ref";
28 clock-frequency = <40000000>;
32 compatible = "gpio-leds";
34 label = "d-link:blue:usb";
35 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
36 default-state = "off";
37 trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
38 linux,default-trigger = "usbport";
41 orange_power: orange_power {
42 label = "d-link:orange:power";
43 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
47 blue_power: blue_power {
48 label = "d-link:blue:power";
49 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
50 default-state = "off";
54 label = "d-link:blue:wps";
55 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
56 default-state = "off";
60 label = "d-link:orange:planet";
61 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
62 default-state = "off";
66 label = "d-link:blue:planet";
67 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
68 default-state = "off";
73 compatible = "gpio-leds";
76 label = "d-link:blue:wlan2g";
77 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
78 default-state = "off";
79 linux,default-trigger = "phy0tpt";
83 label = "d-link:blue:wlan5g";
84 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
85 default-state = "off";
86 linux,default-trigger = "phy1tpt";
92 compatible = "gpio-keys-polled";
97 linux,code = <KEY_RESTART>;
98 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
99 debounce-interval = <60>;
104 linux,code = <KEY_WPS_BUTTON>;
105 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
106 debounce-interval = <60>;
111 compatible = "realtek,rtl8366s";
112 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
113 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
114 realtek,initvals = <0x06 0x0108>;
117 #address-cells = <1>;
123 phy4: ethernet-phy@4 {
134 #address-cells = <1>;
138 usb_ochi_port: port@1 {
140 #trigger-source-cells = <0>;
145 #address-cells = <1>;
149 usb_echi_port: port@1 {
151 #trigger-source-cells = <0>;
163 compatible = "pci168c,0029";
164 reg = <0x8800 0 0 0 0>;
171 compatible = "pci168c,0029";
172 reg = <0x9000 0 0 0 0>;
192 compatible = "jedec,spi-nor";
194 spi-max-frequency = <25000000>;
197 compatible = "fixed-partitions";
198 #address-cells = <1>;
203 reg = <0x000000 0x040000>;
209 reg = <0x040000 0x010000>;
215 reg = <0x050000 0x610000>;
218 caldata: partition@60000 {
220 reg = <0x660000 0x010000>;
226 reg = <0x670000 0x190000>;
236 pll-data = <0x11110000 0x00001099 0x00991099>;
247 pll-data = <0x11110000 0x00001099 0x00991099>;
249 phy-handle = <&phy4>;