1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
10 compatible = "dlink,dir-825-b1", "qca,ar7161";
11 model = "D-Link DIR825B1";
14 led-boot = &orange_power;
15 led-failsafe = &orange_power;
16 led-running = &orange_power;
17 led-upgrade = &orange_power;
21 bootargs = "console=ttyS0,115200";
25 compatible = "fixed-clock";
27 clock-output-names = "ref";
28 clock-frequency = <40000000>;
32 compatible = "gpio-leds";
34 label = "d-link:blue:usb";
35 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
36 default-state = "off";
37 trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
38 linux,default-trigger = "usbport";
41 orange_power: orange_power {
42 label = "d-link:orange:power";
43 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
47 label = "d-link:blue:power";
48 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
49 default-state = "off";
53 label = "d-link:blue:wps";
54 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
55 default-state = "off";
59 label = "d-link:orange:planet";
60 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
61 default-state = "off";
65 label = "d-link:blue:planet";
66 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
67 default-state = "off";
72 compatible = "gpio-leds";
75 label = "d-link:blue:wlan2g";
76 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
77 default-state = "off";
78 linux,default-trigger = "phy0tpt";
82 label = "d-link:blue:wlan5g";
83 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
84 default-state = "off";
85 linux,default-trigger = "phy1tpt";
91 compatible = "gpio-keys-polled";
96 linux,code = <KEY_RESTART>;
97 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
98 debounce-interval = <60>;
103 linux,code = <KEY_WPS_BUTTON>;
104 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
105 debounce-interval = <60>;
110 compatible = "realtek,rtl8366s";
111 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
112 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
113 realtek,initvals = <0x06 0x0108>;
116 #address-cells = <1>;
122 phy4: ethernet-phy@4 {
133 #address-cells = <1>;
137 usb_ochi_port: port@1 {
139 #trigger-source-cells = <0>;
144 #address-cells = <1>;
148 usb_echi_port: port@1 {
150 #trigger-source-cells = <0>;
162 compatible = "pci168c,0029";
163 reg = <0x8800 0 0 0 0>;
170 compatible = "pci168c,0029";
171 reg = <0x9000 0 0 0 0>;
191 compatible = "jedec,spi-nor";
193 spi-max-frequency = <25000000>;
196 compatible = "fixed-partitions";
197 #address-cells = <1>;
202 reg = <0x000000 0x040000>;
208 reg = <0x040000 0x010000>;
214 reg = <0x050000 0x610000>;
217 caldata: partition@60000 {
219 reg = <0x660000 0x010000>;
225 reg = <0x670000 0x190000>;
235 pll-data = <0x11110000 0x00001099 0x00991099>;
246 pll-data = <0x11110000 0x00001099 0x00991099>;
248 phy-handle = <&phy4>;