ath79: Define firmware partition format to all boards where applicable
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7161_dlink_dir-825-b1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 #include "ar7100.dtsi"
8
9 / {
10 compatible = "dlink,dir-825-b1", "qca,ar7161";
11 model = "D-Link DIR825B1";
12
13 aliases {
14 led-boot = &orange_power;
15 led-failsafe = &orange_power;
16 led-running = &blue_power;
17 led-upgrade = &orange_power;
18 };
19
20 chosen {
21 bootargs = "console=ttyS0,115200";
22 };
23
24 extosc: ref {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-output-names = "ref";
28 clock-frequency = <40000000>;
29 };
30
31 leds {
32 compatible = "gpio-leds";
33 blue_usb {
34 label = "d-link:blue:usb";
35 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
36 default-state = "off";
37 trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
38 linux,default-trigger = "usbport";
39 };
40
41 orange_power: orange_power {
42 label = "d-link:orange:power";
43 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
44 default-state = "on";
45 };
46
47 blue_power: blue_power {
48 label = "d-link:blue:power";
49 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
50 default-state = "off";
51 };
52
53 blue_wps {
54 label = "d-link:blue:wps";
55 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
56 default-state = "off";
57 };
58
59 orange_planet {
60 label = "d-link:orange:planet";
61 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
62 default-state = "off";
63 };
64
65 blue_planet {
66 label = "d-link:blue:planet";
67 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
68 default-state = "off";
69 };
70 };
71
72 ath9k-leds {
73 compatible = "gpio-leds";
74
75 wlan2g {
76 label = "d-link:blue:wlan2g";
77 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
78 default-state = "off";
79 linux,default-trigger = "phy0tpt";
80 };
81
82 wlan5g {
83 label = "d-link:blue:wlan5g";
84 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
85 default-state = "off";
86 linux,default-trigger = "phy1tpt";
87 };
88 };
89
90 keys {
91 compatible = "gpio-keys-polled";
92 poll-interval = <20>;
93
94 reset {
95 label = "reset";
96 linux,code = <KEY_RESTART>;
97 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
98 debounce-interval = <60>;
99 };
100
101 wps {
102 label = "wps";
103 linux,code = <KEY_WPS_BUTTON>;
104 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
105 debounce-interval = <60>;
106 };
107 };
108
109 rtl8366s {
110 compatible = "realtek,rtl8366s";
111 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
112 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
113 realtek,initvals = <0x06 0x0108>;
114
115 mdio-bus {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 status = "okay";
119
120 phy-mask = <0x10>;
121
122 phy4: ethernet-phy@4 {
123 reg = <4>;
124 phy-mode = "rgmii";
125 };
126 };
127 };
128 };
129
130
131 &usb1 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 status = "okay";
135
136 usb_ochi_port: port@1 {
137 reg = <1>;
138 #trigger-source-cells = <0>;
139 };
140 };
141
142 &usb2 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 status = "okay";
146
147 usb_echi_port: port@1 {
148 reg = <1>;
149 #trigger-source-cells = <0>;
150 };
151 };
152
153 &usb_phy {
154 status = "okay";
155 };
156
157 &pcie0 {
158 status = "okay";
159
160 ath9k0: wifi@0,11 {
161 compatible = "pci168c,0029";
162 reg = <0x8800 0 0 0 0>;
163 qca,no-eeprom;
164 #gpio-cells = <2>;
165 gpio-controller;
166 };
167
168 ath9k1: wifi@0,12 {
169 compatible = "pci168c,0029";
170 reg = <0x9000 0 0 0 0>;
171 qca,no-eeprom;
172 #gpio-cells = <2>;
173 gpio-controller;
174 };
175 };
176
177 &uart {
178 status = "okay";
179 };
180
181 &pll {
182 clocks = <&extosc>;
183 };
184
185 &spi {
186 status = "okay";
187 num-cs = <1>;
188
189 flash@0 {
190 compatible = "jedec,spi-nor";
191 reg = <0>;
192 spi-max-frequency = <25000000>;
193
194 partitions {
195 compatible = "fixed-partitions";
196 #address-cells = <1>;
197 #size-cells = <1>;
198
199 partition@0 {
200 label = "u-boot";
201 reg = <0x000000 0x040000>;
202 read-only;
203 };
204
205 partition@40000 {
206 label = "config";
207 reg = <0x040000 0x010000>;
208 read-only;
209 };
210
211 partition@50000 {
212 compatible = "denx,uimage";
213 label = "firmware";
214 reg = <0x050000 0x610000>;
215 };
216
217 caldata: partition@60000 {
218 label = "caldata";
219 reg = <0x660000 0x010000>;
220 read-only;
221 };
222
223 partition@670000 {
224 label = "unknown";
225 reg = <0x670000 0x190000>;
226 read-only;
227 };
228 };
229 };
230 };
231
232
233 &eth0 {
234 status = "okay";
235 pll-data = <0x11110000 0x00001099 0x00991099>;
236
237 fixed-link {
238 speed = <1000>;
239 full-duplex;
240 };
241 };
242
243 &eth1 {
244 status = "okay";
245 pll-data = <0x11110000 0x00001099 0x00991099>;
246
247 phy-handle = <&phy4>;
248 };